memhelpers.hh revision 11608
112391Sjason@lowepower.com/* 212391Sjason@lowepower.com * Copyright (c) 2013 ARM Limited 312391Sjason@lowepower.com * All rights reserved 412391Sjason@lowepower.com * 512391Sjason@lowepower.com * The license below extends only to copyright in the software and shall 612391Sjason@lowepower.com * not be construed as granting a license to any other intellectual 712391Sjason@lowepower.com * property including but not limited to intellectual property relating 812391Sjason@lowepower.com * to a hardware implementation of the functionality of the software 912391Sjason@lowepower.com * licensed hereunder. You may use the software subject to the license 1012391Sjason@lowepower.com * terms below provided that you ensure that this notice is replicated 1112391Sjason@lowepower.com * unmodified and in its entirety in all distributions of the software, 1212391Sjason@lowepower.com * modified or unmodified, in source code or in binary form. 1312391Sjason@lowepower.com * 1412391Sjason@lowepower.com * Copyright (c) 2011 Google 1512391Sjason@lowepower.com * All rights reserved. 1612391Sjason@lowepower.com * 1712391Sjason@lowepower.com * Redistribution and use in source and binary forms, with or without 1812391Sjason@lowepower.com * modification, are permitted provided that the following conditions are 1912391Sjason@lowepower.com * met: redistributions of source code must retain the above copyright 2012391Sjason@lowepower.com * notice, this list of conditions and the following disclaimer; 2112391Sjason@lowepower.com * redistributions in binary form must reproduce the above copyright 2212391Sjason@lowepower.com * notice, this list of conditions and the following disclaimer in the 2312391Sjason@lowepower.com * documentation and/or other materials provided with the distribution; 2412391Sjason@lowepower.com * neither the name of the copyright holders nor the names of its 2512391Sjason@lowepower.com * contributors may be used to endorse or promote products derived from 2612391Sjason@lowepower.com * this software without specific prior written permission. 2712391Sjason@lowepower.com * 2812391Sjason@lowepower.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2912391Sjason@lowepower.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3012391Sjason@lowepower.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3112391Sjason@lowepower.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3212391Sjason@lowepower.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3312391Sjason@lowepower.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3412391Sjason@lowepower.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3512391Sjason@lowepower.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3612391Sjason@lowepower.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3712391Sjason@lowepower.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3812391Sjason@lowepower.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3912391Sjason@lowepower.com * 4012391Sjason@lowepower.com * Authors: Gabe Black 4112391Sjason@lowepower.com */ 4212391Sjason@lowepower.com 4312391Sjason@lowepower.com#ifndef __ARCH_GENERIC_MEMHELPERS_HH__ 4412391Sjason@lowepower.com#define __ARCH_GENERIC_MEMHELPERS_HH__ 4512391Sjason@lowepower.com 4612391Sjason@lowepower.com#include "base/types.hh" 4712391Sjason@lowepower.com#include "mem/request.hh" 4812391Sjason@lowepower.com#include "sim/byteswap.hh" 4912391Sjason@lowepower.com#include "sim/insttracer.hh" 5012391Sjason@lowepower.com 5112391Sjason@lowepower.com/// Initiate a read from memory in timing mode. Note that the 'mem' 5212391Sjason@lowepower.com/// parameter is unused; only the type of that parameter is used 5312391Sjason@lowepower.com/// to determine the size of the access. 5412391Sjason@lowepower.comtemplate <class XC, class MemT> 5512391Sjason@lowepower.comFault 5612391Sjason@lowepower.cominitiateMemRead(XC *xc, Trace::InstRecord *traceData, Addr addr, 5712391Sjason@lowepower.com MemT &mem, Request::Flags flags) 5812391Sjason@lowepower.com{ 5912391Sjason@lowepower.com return xc->initiateMemRead(addr, sizeof(MemT), flags); 6012391Sjason@lowepower.com} 6112391Sjason@lowepower.com 6212391Sjason@lowepower.com/// Extract the data returned from a timing mode read. 6312391Sjason@lowepower.comtemplate <class MemT> 6412391Sjason@lowepower.comvoid 6512391Sjason@lowepower.comgetMem(PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData) 6612391Sjason@lowepower.com{ 6712391Sjason@lowepower.com mem = pkt->get<MemT>(); 6812391Sjason@lowepower.com if (traceData) 6912391Sjason@lowepower.com traceData->setData(mem); 7012391Sjason@lowepower.com} 7112391Sjason@lowepower.com 7212391Sjason@lowepower.com/// Read from memory in atomic mode. 7312391Sjason@lowepower.comtemplate <class XC, class MemT> 7412391Sjason@lowepower.comFault 7512391Sjason@lowepower.comreadMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem, 7612391Sjason@lowepower.com Request::Flags flags) 7712391Sjason@lowepower.com{ 7812391Sjason@lowepower.com memset(&mem, 0, sizeof(mem)); 7912391Sjason@lowepower.com Fault fault = xc->readMem(addr, (uint8_t *)&mem, sizeof(MemT), flags); 8012391Sjason@lowepower.com if (fault == NoFault) { 8112391Sjason@lowepower.com mem = TheISA::gtoh(mem); 8212391Sjason@lowepower.com if (traceData) 8312391Sjason@lowepower.com traceData->setData(mem); 8412391Sjason@lowepower.com } 8512391Sjason@lowepower.com return fault; 8612391Sjason@lowepower.com} 8712391Sjason@lowepower.com 8812391Sjason@lowepower.com/// Write to memory in timing mode. 8912391Sjason@lowepower.comtemplate <class XC, class MemT> 9012391Sjason@lowepower.comFault 9112391Sjason@lowepower.comwriteMemTiming(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr, 9212391Sjason@lowepower.com Request::Flags flags, uint64_t *res) 9312391Sjason@lowepower.com{ 9412391Sjason@lowepower.com if (traceData) { 9512391Sjason@lowepower.com traceData->setData(mem); 9612391Sjason@lowepower.com } 9712391Sjason@lowepower.com mem = TheISA::htog(mem); 9812391Sjason@lowepower.com return xc->writeMem((uint8_t *)&mem, sizeof(MemT), addr, flags, res); 9912391Sjason@lowepower.com} 10012391Sjason@lowepower.com 10112391Sjason@lowepower.com/// Write to memory in atomic mode. 10212391Sjason@lowepower.comtemplate <class XC, class MemT> 10312391Sjason@lowepower.comFault 10412391Sjason@lowepower.comwriteMemAtomic(XC *xc, Trace::InstRecord *traceData, const MemT &mem, 10512391Sjason@lowepower.com Addr addr, Request::Flags flags, uint64_t *res) 10612391Sjason@lowepower.com{ 10712391Sjason@lowepower.com if (traceData) { 10812391Sjason@lowepower.com traceData->setData(mem); 10912391Sjason@lowepower.com } 11012391Sjason@lowepower.com MemT host_mem = TheISA::htog(mem); 11112391Sjason@lowepower.com Fault fault = 11212391Sjason@lowepower.com xc->writeMem((uint8_t *)&host_mem, sizeof(MemT), addr, flags, res); 113 if (fault == NoFault && res != NULL) { 114 if (flags & Request::MEM_SWAP || flags & Request::MEM_SWAP_COND) 115 *res = TheISA::gtoh((MemT)*res); 116 else 117 *res = TheISA::gtoh(*res); 118 } 119 return fault; 120} 121 122#endif 123