memhelpers.hh revision 11303
1/* 2 * Copyright (c) 2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2011 Google 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Gabe Black 41 */ 42 43#ifndef __ARCH_GENERIC_MEMHELPERS_HH__ 44#define __ARCH_GENERIC_MEMHELPERS_HH__ 45 46#include "base/types.hh" 47#include "mem/request.hh" 48#include "sim/byteswap.hh" 49#include "sim/insttracer.hh" 50 51/// Initiate a read from memory in timing mode. Note that the 'mem' 52/// parameter is unused; only the type of that parameter is used 53/// to determine the size of the access. 54template <class XC, class MemT> 55Fault 56initiateMemRead(XC *xc, Trace::InstRecord *traceData, Addr addr, 57 MemT &mem, unsigned flags) 58{ 59 return xc->initiateMemRead(addr, sizeof(MemT), flags); 60} 61 62/// Extract the data returned from a timing mode read. 63template <class MemT> 64void 65getMem(PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData) 66{ 67 mem = pkt->get<MemT>(); 68 if (traceData) 69 traceData->setData(mem); 70} 71 72/// Read from memory in atomic mode. 73template <class XC, class MemT> 74Fault 75readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem, 76 unsigned flags) 77{ 78 memset(&mem, 0, sizeof(mem)); 79 Fault fault = xc->readMem(addr, (uint8_t *)&mem, sizeof(MemT), flags); 80 if (fault == NoFault) { 81 mem = TheISA::gtoh(mem); 82 if (traceData) 83 traceData->setData(mem); 84 } 85 return fault; 86} 87 88/// Write to memory in timing mode. 89template <class XC, class MemT> 90Fault 91writeMemTiming(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr, 92 unsigned flags, uint64_t *res) 93{ 94 if (traceData) { 95 traceData->setData(mem); 96 } 97 mem = TheISA::htog(mem); 98 return xc->writeMem((uint8_t *)&mem, sizeof(MemT), addr, flags, res); 99} 100 101/// Write to memory in atomic mode. 102template <class XC, class MemT> 103Fault 104writeMemAtomic(XC *xc, Trace::InstRecord *traceData, const MemT &mem, 105 Addr addr, unsigned flags, uint64_t *res) 106{ 107 if (traceData) { 108 traceData->setData(mem); 109 } 110 MemT host_mem = TheISA::htog(mem); 111 Fault fault = 112 xc->writeMem((uint8_t *)&host_mem, sizeof(MemT), addr, flags, res); 113 if (fault == NoFault && res != NULL) { 114 if (flags & Request::MEM_SWAP || flags & Request::MEM_SWAP_COND) 115 *res = TheISA::gtoh((MemT)*res); 116 else 117 *res = TheISA::gtoh(*res); 118 } 119 return fault; 120} 121 122#endif 123