memhelpers.hh revision 13234
12348SN/A/*
22348SN/A * Copyright (c) 2013 ARM Limited
32348SN/A * All rights reserved
42348SN/A *
52348SN/A * The license below extends only to copyright in the software and shall
62348SN/A * not be construed as granting a license to any other intellectual
72348SN/A * property including but not limited to intellectual property relating
82348SN/A * to a hardware implementation of the functionality of the software
92348SN/A * licensed hereunder.  You may use the software subject to the license
102348SN/A * terms below provided that you ensure that this notice is replicated
112348SN/A * unmodified and in its entirety in all distributions of the software,
122348SN/A * modified or unmodified, in source code or in binary form.
132348SN/A *
142348SN/A * Copyright (c) 2011 Google
152348SN/A * All rights reserved.
162348SN/A *
172348SN/A * Redistribution and use in source and binary forms, with or without
182348SN/A * modification, are permitted provided that the following conditions are
192348SN/A * met: redistributions of source code must retain the above copyright
202348SN/A * notice, this list of conditions and the following disclaimer;
212348SN/A * redistributions in binary form must reproduce the above copyright
222348SN/A * notice, this list of conditions and the following disclaimer in the
232348SN/A * documentation and/or other materials provided with the distribution;
242348SN/A * neither the name of the copyright holders nor the names of its
252348SN/A * contributors may be used to endorse or promote products derived from
262348SN/A * this software without specific prior written permission.
272689Sktlim@umich.edu *
282689Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
292348SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
302325SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
315804Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
323918Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
338229Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
347813Ssteve.reinhardt@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
358232Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
362325SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
375804Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
385804Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
395804Snate@binkert.org *
405804Snate@binkert.org * Authors: Gabe Black
415804Snate@binkert.org */
425804Snate@binkert.org
435804Snate@binkert.org#ifndef __ARCH_GENERIC_MEMHELPERS_HH__
442325SN/A#define __ARCH_GENERIC_MEMHELPERS_HH__
452325SN/A
463918Ssaidi@eecs.umich.edu#include "arch/isa_traits.hh"
472325SN/A#include "base/types.hh"
482325SN/A#include "mem/packet.hh"
492325SN/A#include "mem/request.hh"
502325SN/A#include "sim/byteswap.hh"
512325SN/A#include "sim/insttracer.hh"
522348SN/A
532348SN/A/// Initiate a read from memory in timing mode.  Note that the 'mem'
542325SN/A/// parameter is unused; only the type of that parameter is used
552325SN/A/// to determine the size of the access.
562325SN/Atemplate <class XC, class MemT>
572325SN/AFault
582325SN/AinitiateMemRead(XC *xc, Trace::InstRecord *traceData, Addr addr,
592325SN/A                MemT &mem, Request::Flags flags)
602325SN/A{
612325SN/A    return xc->initiateMemRead(addr, sizeof(MemT), flags);
622325SN/A}
632325SN/A
642325SN/A/// Extract the data returned from a timing mode read.
652325SN/Atemplate <class MemT>
662325SN/Avoid
672325SN/AgetMem(PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData)
682348SN/A{
692348SN/A    mem = pkt->get<MemT>(TheISA::GuestByteOrder);
702325SN/A    if (traceData)
712325SN/A        traceData->setData(mem);
722325SN/A}
732325SN/A
742325SN/A/// Read from memory in atomic mode.
752325SN/Atemplate <class XC, class MemT>
762325SN/AFault
772325SN/AreadMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem,
782325SN/A              Request::Flags flags)
792325SN/A{
802325SN/A    memset(&mem, 0, sizeof(mem));
812325SN/A    Fault fault = xc->readMem(addr, (uint8_t *)&mem, sizeof(MemT), flags);
822325SN/A    if (fault == NoFault) {
832325SN/A        mem = TheISA::gtoh(mem);
842325SN/A        if (traceData)
852325SN/A            traceData->setData(mem);
862325SN/A    }
872325SN/A    return fault;
882348SN/A}
892325SN/A
902325SN/A/// Write to memory in timing mode.
912325SN/Atemplate <class XC, class MemT>
922325SN/AFault
932325SN/AwriteMemTiming(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr,
942325SN/A               Request::Flags flags, uint64_t *res)
952325SN/A{
962325SN/A    if (traceData) {
972325SN/A        traceData->setData(mem);
982325SN/A    }
992325SN/A    mem = TheISA::htog(mem);
1002325SN/A    return xc->writeMem((uint8_t *)&mem, sizeof(MemT), addr, flags, res);
1012325SN/A}
1022325SN/A
1032325SN/A/// Write to memory in atomic mode.
1042325SN/Atemplate <class XC, class MemT>
1052348SN/AFault
1062325SN/AwriteMemAtomic(XC *xc, Trace::InstRecord *traceData, const MemT &mem,
1072325SN/A               Addr addr, Request::Flags flags, uint64_t *res)
1082325SN/A{
1092325SN/A    if (traceData) {
1102325SN/A        traceData->setData(mem);
1112325SN/A    }
1122325SN/A    MemT host_mem = TheISA::htog(mem);
1132325SN/A    Fault fault =
1142325SN/A          xc->writeMem((uint8_t *)&host_mem, sizeof(MemT), addr, flags, res);
1152325SN/A    if (fault == NoFault && res != NULL) {
1162325SN/A        if (flags & Request::MEM_SWAP || flags & Request::MEM_SWAP_COND)
1172325SN/A            *(MemT *)res = TheISA::gtoh(*(MemT *)res);
1182325SN/A        else
1192325SN/A            *res = TheISA::gtoh(*res);
1202325SN/A    }
1212325SN/A    return fault;
1222325SN/A}
1233918Ssaidi@eecs.umich.edu
1242325SN/A/// Do atomic read-modify-write (AMO) in atomic mode
1252325SN/Atemplate <class XC, class MemT>
1262325SN/AFault
1272325SN/AamoMemAtomic(XC *xc, Trace::InstRecord *traceData, MemT &mem, Addr addr,
1282325SN/A             Request::Flags flags, AtomicOpFunctor *amo_op)
1292325SN/A{
1302325SN/A    assert(amo_op);
1312325SN/A
1322325SN/A    // mem will hold the previous value at addr after the AMO completes
1332325SN/A    memset(&mem, 0, sizeof(mem));
1342325SN/A
1352325SN/A    Fault fault = xc->amoMem(addr, (uint8_t *)&mem, sizeof(MemT), flags,
1362325SN/A                             amo_op);
1372325SN/A
1382325SN/A    if (fault == NoFault) {
1392325SN/A        mem = TheISA::gtoh(mem);
1402325SN/A        if (traceData)
1412325SN/A            traceData->setData(mem);
1422325SN/A    }
1432325SN/A    return fault;
1442325SN/A}
1452325SN/A
1462325SN/A/// Do atomic read-modify-wrote (AMO) in timing mode
1472325SN/Atemplate <class XC, class MemT>
1482325SN/AFault
1492325SN/AinitiateMemAMO(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT& mem,
1502325SN/A               Request::Flags flags, AtomicOpFunctor *amo_op)
1512325SN/A{
1522325SN/A    assert(amo_op);
1532325SN/A    return xc->initiateMemAMO(addr, sizeof(MemT), flags, amo_op);
1542325SN/A}
1552325SN/A
1562325SN/A#endif
1572325SN/A