utility.hh revision 6242
16019Shines@cs.fsu.edu/* 26019Shines@cs.fsu.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 36019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 46019Shines@cs.fsu.edu * All rights reserved. 56019Shines@cs.fsu.edu * 66019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 76019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 86019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 96019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 106019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 116019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 126019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 136019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 146019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 156019Shines@cs.fsu.edu * this software without specific prior written permission. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286019Shines@cs.fsu.edu * 296019Shines@cs.fsu.edu * Authors: Korey Sewell 306019Shines@cs.fsu.edu * Stephen Hines 316019Shines@cs.fsu.edu */ 326019Shines@cs.fsu.edu 336019Shines@cs.fsu.edu#ifndef __ARCH_ARM_UTILITY_HH__ 346019Shines@cs.fsu.edu#define __ARCH_ARM_UTILITY_HH__ 356019Shines@cs.fsu.edu 366242Sgblack@eecs.umich.edu#include "arch/arm/miscregs.hh" 376019Shines@cs.fsu.edu#include "arch/arm/types.hh" 386019Shines@cs.fsu.edu#include "base/misc.hh" 396216Snate@binkert.org#include "base/types.hh" 406019Shines@cs.fsu.edu#include "config/full_system.hh" 416019Shines@cs.fsu.edu#include "cpu/thread_context.hh" 426019Shines@cs.fsu.edu 436019Shines@cs.fsu.educlass ThreadContext; 446019Shines@cs.fsu.edu 456019Shines@cs.fsu.edunamespace ArmISA { 466019Shines@cs.fsu.edu 476242Sgblack@eecs.umich.edu inline bool 486242Sgblack@eecs.umich.edu testPredicate(CPSR cpsr, ConditionCode code) 496242Sgblack@eecs.umich.edu { 506242Sgblack@eecs.umich.edu switch (code) 516242Sgblack@eecs.umich.edu { 526242Sgblack@eecs.umich.edu case COND_EQ: return cpsr.z; 536242Sgblack@eecs.umich.edu case COND_NE: return !cpsr.z; 546242Sgblack@eecs.umich.edu case COND_CS: return cpsr.c; 556242Sgblack@eecs.umich.edu case COND_CC: return !cpsr.c; 566242Sgblack@eecs.umich.edu case COND_MI: return cpsr.n; 576242Sgblack@eecs.umich.edu case COND_PL: return !cpsr.n; 586242Sgblack@eecs.umich.edu case COND_VS: return cpsr.v; 596242Sgblack@eecs.umich.edu case COND_VC: return !cpsr.v; 606242Sgblack@eecs.umich.edu case COND_HI: return (cpsr.c && !cpsr.z); 616242Sgblack@eecs.umich.edu case COND_LS: return !(cpsr.c && !cpsr.z); 626242Sgblack@eecs.umich.edu case COND_GE: return !(cpsr.n ^ cpsr.v); 636242Sgblack@eecs.umich.edu case COND_LT: return (cpsr.n ^ cpsr.v); 646242Sgblack@eecs.umich.edu case COND_GT: return !(cpsr.n ^ cpsr.v || cpsr.z); 656242Sgblack@eecs.umich.edu case COND_LE: return (cpsr.n ^ cpsr.v || cpsr.z); 666242Sgblack@eecs.umich.edu case COND_AL: return true; 676242Sgblack@eecs.umich.edu case COND_NV: return false; 686242Sgblack@eecs.umich.edu default: 696242Sgblack@eecs.umich.edu panic("Unhandled predicate condition: %d\n", code); 706242Sgblack@eecs.umich.edu } 716242Sgblack@eecs.umich.edu } 726242Sgblack@eecs.umich.edu 736019Shines@cs.fsu.edu //Floating Point Utility Functions 746019Shines@cs.fsu.edu uint64_t fpConvert(ConvertType cvt_type, double fp_val); 756019Shines@cs.fsu.edu double roundFP(double val, int digits); 766019Shines@cs.fsu.edu double truncFP(double val); 776019Shines@cs.fsu.edu 786019Shines@cs.fsu.edu bool getCondCode(uint32_t fcsr, int cc); 796019Shines@cs.fsu.edu uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val); 806019Shines@cs.fsu.edu uint32_t genInvalidVector(uint32_t fcsr); 816019Shines@cs.fsu.edu 826019Shines@cs.fsu.edu bool isNan(void *val_ptr, int size); 836019Shines@cs.fsu.edu bool isQnan(void *val_ptr, int size); 846019Shines@cs.fsu.edu bool isSnan(void *val_ptr, int size); 856019Shines@cs.fsu.edu 866019Shines@cs.fsu.edu /** 876019Shines@cs.fsu.edu * Function to insure ISA semantics about 0 registers. 886019Shines@cs.fsu.edu * @param tc The thread context. 896019Shines@cs.fsu.edu */ 906019Shines@cs.fsu.edu template <class TC> 916019Shines@cs.fsu.edu void zeroRegisters(TC *tc); 926019Shines@cs.fsu.edu 936019Shines@cs.fsu.edu // Instruction address compression hooks 946019Shines@cs.fsu.edu static inline Addr realPCToFetchPC(const Addr &addr) { 956019Shines@cs.fsu.edu return addr; 966019Shines@cs.fsu.edu } 976019Shines@cs.fsu.edu 986019Shines@cs.fsu.edu static inline Addr fetchPCToRealPC(const Addr &addr) { 996019Shines@cs.fsu.edu return addr; 1006019Shines@cs.fsu.edu } 1016019Shines@cs.fsu.edu 1026019Shines@cs.fsu.edu // the size of "fetched" instructions 1036019Shines@cs.fsu.edu static inline size_t fetchInstSize() { 1046019Shines@cs.fsu.edu return sizeof(MachInst); 1056019Shines@cs.fsu.edu } 1066019Shines@cs.fsu.edu 1076019Shines@cs.fsu.edu static inline MachInst makeRegisterCopy(int dest, int src) { 1086019Shines@cs.fsu.edu panic("makeRegisterCopy not implemented"); 1096019Shines@cs.fsu.edu return 0; 1106019Shines@cs.fsu.edu } 1116019Shines@cs.fsu.edu 1126019Shines@cs.fsu.edu inline void startupCPU(ThreadContext *tc, int cpuId) 1136019Shines@cs.fsu.edu { 1146019Shines@cs.fsu.edu tc->activate(0); 1156019Shines@cs.fsu.edu } 1166019Shines@cs.fsu.edu}; 1176019Shines@cs.fsu.edu 1186019Shines@cs.fsu.edu 1196019Shines@cs.fsu.edu#endif 120