utility.hh revision 12494
16019Shines@cs.fsu.edu/* 212494Schuan.zhu@arm.com * Copyright (c) 2010, 2012-2013, 2016-2017 ARM Limited 37111Sgblack@eecs.umich.edu * All rights reserved 47111Sgblack@eecs.umich.edu * 57111Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67111Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77111Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87111Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97111Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107111Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117111Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127111Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137111Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 166019Shines@cs.fsu.edu * All rights reserved. 176019Shines@cs.fsu.edu * 186019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu * this software without specific prior written permission. 286019Shines@cs.fsu.edu * 296019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu * 416019Shines@cs.fsu.edu * Authors: Korey Sewell 426019Shines@cs.fsu.edu * Stephen Hines 436019Shines@cs.fsu.edu */ 446019Shines@cs.fsu.edu 456019Shines@cs.fsu.edu#ifndef __ARCH_ARM_UTILITY_HH__ 466019Shines@cs.fsu.edu#define __ARCH_ARM_UTILITY_HH__ 476019Shines@cs.fsu.edu 487692SAli.Saidi@ARM.com#include "arch/arm/isa_traits.hh" 496242Sgblack@eecs.umich.edu#include "arch/arm/miscregs.hh" 506019Shines@cs.fsu.edu#include "arch/arm/types.hh" 5112334Sgabeblack@google.com#include "base/logging.hh" 527408Sgblack@eecs.umich.edu#include "base/trace.hh" 536216Snate@binkert.org#include "base/types.hh" 547720Sgblack@eecs.umich.edu#include "cpu/static_inst.hh" 556019Shines@cs.fsu.edu#include "cpu/thread_context.hh" 566019Shines@cs.fsu.edu 5710037SARM gem5 Developersclass ArmSystem; 5810037SARM gem5 Developers 596019Shines@cs.fsu.edunamespace ArmISA { 606019Shines@cs.fsu.edu 617751SAli.Saidi@ARM.cominline PCState 627751SAli.Saidi@ARM.combuildRetPC(const PCState &curPC, const PCState &callPC) 637751SAli.Saidi@ARM.com{ 647751SAli.Saidi@ARM.com PCState retPC = callPC; 657751SAli.Saidi@ARM.com retPC.uEnd(); 667751SAli.Saidi@ARM.com return retPC; 677751SAli.Saidi@ARM.com} 687751SAli.Saidi@ARM.com 697751SAli.Saidi@ARM.cominline bool 708303SAli.Saidi@ARM.comtestPredicate(uint32_t nz, uint32_t c, uint32_t v, ConditionCode code) 717751SAli.Saidi@ARM.com{ 728303SAli.Saidi@ARM.com bool n = (nz & 0x2); 738303SAli.Saidi@ARM.com bool z = (nz & 0x1); 748303SAli.Saidi@ARM.com 757751SAli.Saidi@ARM.com switch (code) 767720Sgblack@eecs.umich.edu { 778303SAli.Saidi@ARM.com case COND_EQ: return z; 788303SAli.Saidi@ARM.com case COND_NE: return !z; 798303SAli.Saidi@ARM.com case COND_CS: return c; 808303SAli.Saidi@ARM.com case COND_CC: return !c; 818303SAli.Saidi@ARM.com case COND_MI: return n; 828303SAli.Saidi@ARM.com case COND_PL: return !n; 838303SAli.Saidi@ARM.com case COND_VS: return v; 848303SAli.Saidi@ARM.com case COND_VC: return !v; 858303SAli.Saidi@ARM.com case COND_HI: return (c && !z); 868303SAli.Saidi@ARM.com case COND_LS: return !(c && !z); 878303SAli.Saidi@ARM.com case COND_GE: return !(n ^ v); 888303SAli.Saidi@ARM.com case COND_LT: return (n ^ v); 898303SAli.Saidi@ARM.com case COND_GT: return !(n ^ v || z); 908303SAli.Saidi@ARM.com case COND_LE: return (n ^ v || z); 917751SAli.Saidi@ARM.com case COND_AL: return true; 927751SAli.Saidi@ARM.com case COND_UC: return true; 937751SAli.Saidi@ARM.com default: 947751SAli.Saidi@ARM.com panic("Unhandled predicate condition: %d\n", code); 957720Sgblack@eecs.umich.edu } 967751SAli.Saidi@ARM.com} 977720Sgblack@eecs.umich.edu 987751SAli.Saidi@ARM.com/** 997751SAli.Saidi@ARM.com * Function to insure ISA semantics about 0 registers. 1007751SAli.Saidi@ARM.com * @param tc The thread context. 1017751SAli.Saidi@ARM.com */ 1027751SAli.Saidi@ARM.comtemplate <class TC> 1037751SAli.Saidi@ARM.comvoid zeroRegisters(TC *tc); 1046242Sgblack@eecs.umich.edu 1057751SAli.Saidi@ARM.cominline void startupCPU(ThreadContext *tc, int cpuId) 1067751SAli.Saidi@ARM.com{ 10710407Smitch.hayenga@arm.com tc->activate(); 1087751SAli.Saidi@ARM.com} 1096019Shines@cs.fsu.edu 1107751SAli.Saidi@ARM.comvoid copyRegs(ThreadContext *src, ThreadContext *dest); 1116246Sgblack@eecs.umich.edu 1127751SAli.Saidi@ARM.comstatic inline void 1137751SAli.Saidi@ARM.comcopyMiscRegs(ThreadContext *src, ThreadContext *dest) 1147751SAli.Saidi@ARM.com{ 1157751SAli.Saidi@ARM.com panic("Copy Misc. Regs Not Implemented Yet\n"); 1167751SAli.Saidi@ARM.com} 1176329Sgblack@eecs.umich.edu 1187751SAli.Saidi@ARM.comvoid initCPU(ThreadContext *tc, int cpuId); 1196757SAli.Saidi@ARM.com 1207751SAli.Saidi@ARM.comstatic inline bool 1217751SAli.Saidi@ARM.cominUserMode(CPSR cpsr) 1227751SAli.Saidi@ARM.com{ 12310037SARM gem5 Developers return cpsr.mode == MODE_USER || cpsr.mode == MODE_EL0T; 1247751SAli.Saidi@ARM.com} 1257638Sgblack@eecs.umich.edu 1267751SAli.Saidi@ARM.comstatic inline bool 1277751SAli.Saidi@ARM.cominUserMode(ThreadContext *tc) 1287751SAli.Saidi@ARM.com{ 1297751SAli.Saidi@ARM.com return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR)); 1307751SAli.Saidi@ARM.com} 1317638Sgblack@eecs.umich.edu 1327751SAli.Saidi@ARM.comstatic inline bool 1337751SAli.Saidi@ARM.cominPrivilegedMode(CPSR cpsr) 1347751SAli.Saidi@ARM.com{ 1357751SAli.Saidi@ARM.com return !inUserMode(cpsr); 1367751SAli.Saidi@ARM.com} 1377638Sgblack@eecs.umich.edu 1387751SAli.Saidi@ARM.comstatic inline bool 1397751SAli.Saidi@ARM.cominPrivilegedMode(ThreadContext *tc) 1407751SAli.Saidi@ARM.com{ 1417751SAli.Saidi@ARM.com return !inUserMode(tc); 1427751SAli.Saidi@ARM.com} 1436757SAli.Saidi@ARM.com 14410037SARM gem5 Developersbool inAArch64(ThreadContext *tc); 14510037SARM gem5 Developers 14610037SARM gem5 Developersstatic inline OperatingMode 14710037SARM gem5 DeveloperscurrOpMode(ThreadContext *tc) 1487751SAli.Saidi@ARM.com{ 14910037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 15010037SARM gem5 Developers return (OperatingMode) (uint8_t) cpsr.mode; 1517751SAli.Saidi@ARM.com} 1527640Sgblack@eecs.umich.edu 15310037SARM gem5 Developersstatic inline ExceptionLevel 15410037SARM gem5 DeveloperscurrEL(ThreadContext *tc) 1557751SAli.Saidi@ARM.com{ 15610037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 15710037SARM gem5 Developers return (ExceptionLevel) (uint8_t) cpsr.el; 1587751SAli.Saidi@ARM.com} 1597640Sgblack@eecs.umich.edu 16012494Schuan.zhu@arm.combool ELIs32(ThreadContext *tc, ExceptionLevel el); 16112494Schuan.zhu@arm.com 16210037SARM gem5 Developersbool ELIs64(ThreadContext *tc, ExceptionLevel el); 16310037SARM gem5 Developers 16410037SARM gem5 Developersbool isBigEndian64(ThreadContext *tc); 16510037SARM gem5 Developers 16611514Sandreas.sandberg@arm.comstatic inline uint8_t 16711514Sandreas.sandberg@arm.comitState(CPSR psr) 16811514Sandreas.sandberg@arm.com{ 16911514Sandreas.sandberg@arm.com ITSTATE it = 0; 17011514Sandreas.sandberg@arm.com it.top6 = psr.it2; 17111514Sandreas.sandberg@arm.com it.bottom2 = psr.it1; 17211514Sandreas.sandberg@arm.com 17311514Sandreas.sandberg@arm.com return (uint8_t)it; 17411514Sandreas.sandberg@arm.com} 17511514Sandreas.sandberg@arm.com 17610037SARM gem5 Developers/** 17710037SARM gem5 Developers * Removes the tag from tagged addresses if that mode is enabled. 17810037SARM gem5 Developers * @param addr The address to be purified. 17910037SARM gem5 Developers * @param tc The thread context. 18010037SARM gem5 Developers * @param el The controlled exception level. 18110037SARM gem5 Developers * @return The purified address. 18210037SARM gem5 Developers */ 18310854SNathanael.Premillieu@arm.comAddr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el, 18410854SNathanael.Premillieu@arm.com TTBCR tcr); 18510037SARM gem5 DevelopersAddr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el); 18610037SARM gem5 Developers 1877751SAli.Saidi@ARM.comstatic inline bool 18810037SARM gem5 DevelopersinSecureState(SCR scr, CPSR cpsr) 1897751SAli.Saidi@ARM.com{ 19010037SARM gem5 Developers switch ((OperatingMode) (uint8_t) cpsr.mode) { 19110037SARM gem5 Developers case MODE_MON: 19210037SARM gem5 Developers case MODE_EL3T: 19310037SARM gem5 Developers case MODE_EL3H: 19410037SARM gem5 Developers return true; 19510037SARM gem5 Developers case MODE_HYP: 19610037SARM gem5 Developers case MODE_EL2T: 19710037SARM gem5 Developers case MODE_EL2H: 19810037SARM gem5 Developers return false; 19910037SARM gem5 Developers default: 20010037SARM gem5 Developers return !scr.ns; 20110037SARM gem5 Developers } 2027751SAli.Saidi@ARM.com} 2037640Sgblack@eecs.umich.edu 20410037SARM gem5 Developersbool longDescFormatInUse(ThreadContext *tc); 20510037SARM gem5 Developers 20610037SARM gem5 Developersbool inSecureState(ThreadContext *tc); 20710037SARM gem5 Developers 20810037SARM gem5 Developersuint32_t getMPIDR(ArmSystem *arm_sys, ThreadContext *tc); 20910037SARM gem5 Developers 21010037SARM gem5 Developersstatic inline uint32_t 21110037SARM gem5 DevelopersmcrMrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn, 21210037SARM gem5 Developers uint32_t opc1, uint32_t opc2) 21310037SARM gem5 Developers{ 21410037SARM gem5 Developers return (isRead << 0) | 21510037SARM gem5 Developers (crm << 1) | 21610037SARM gem5 Developers (rt << 5) | 21710037SARM gem5 Developers (crn << 10) | 21810037SARM gem5 Developers (opc1 << 14) | 21910037SARM gem5 Developers (opc2 << 17); 22010037SARM gem5 Developers} 22110037SARM gem5 Developers 22210037SARM gem5 Developersstatic inline void 22310037SARM gem5 DevelopersmcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt, 22410037SARM gem5 Developers uint32_t &crn, uint32_t &opc1, uint32_t &opc2) 22510037SARM gem5 Developers{ 22610037SARM gem5 Developers isRead = (iss >> 0) & 0x1; 22710037SARM gem5 Developers crm = (iss >> 1) & 0xF; 22810037SARM gem5 Developers rt = (IntRegIndex) ((iss >> 5) & 0xF); 22910037SARM gem5 Developers crn = (iss >> 10) & 0xF; 23010037SARM gem5 Developers opc1 = (iss >> 14) & 0x7; 23110037SARM gem5 Developers opc2 = (iss >> 17) & 0x7; 23210037SARM gem5 Developers} 23310037SARM gem5 Developers 23410037SARM gem5 Developersstatic inline uint32_t 23510037SARM gem5 DevelopersmcrrMrrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, IntRegIndex rt2, 23610037SARM gem5 Developers uint32_t opc1) 23710037SARM gem5 Developers{ 23810037SARM gem5 Developers return (isRead << 0) | 23910037SARM gem5 Developers (crm << 1) | 24010037SARM gem5 Developers (rt << 5) | 24110037SARM gem5 Developers (rt2 << 10) | 24210037SARM gem5 Developers (opc1 << 16); 24310037SARM gem5 Developers} 24410037SARM gem5 Developers 24510037SARM gem5 Developersstatic inline uint32_t 24610037SARM gem5 DevelopersmsrMrs64IssBuild(bool isRead, uint32_t op0, uint32_t op1, uint32_t crn, 24710037SARM gem5 Developers uint32_t crm, uint32_t op2, IntRegIndex rt) 24810037SARM gem5 Developers{ 24910037SARM gem5 Developers return isRead | 25010037SARM gem5 Developers (crm << 1) | 25110037SARM gem5 Developers (rt << 5) | 25210037SARM gem5 Developers (crn << 10) | 25310037SARM gem5 Developers (op1 << 14) | 25410037SARM gem5 Developers (op2 << 17) | 25510037SARM gem5 Developers (op0 << 20); 25610037SARM gem5 Developers} 25710037SARM gem5 Developers 25810037SARM gem5 Developersbool 25910037SARM gem5 DevelopersmcrMrc15TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, 26010037SARM gem5 Developers HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss); 26110037SARM gem5 Developersbool 26210037SARM gem5 DevelopersmcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, 26310037SARM gem5 Developers HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss); 26410037SARM gem5 Developersbool 26510037SARM gem5 DevelopersmcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr, 26610037SARM gem5 Developers HCR hcr, uint32_t iss); 26710037SARM gem5 Developers 26810037SARM gem5 Developersbool msrMrs64TrapToSup(const MiscRegIndex miscReg, ExceptionLevel el, 26910037SARM gem5 Developers CPACR cpacr); 27011582SDylan.Johnson@ARM.combool msrMrs64TrapToHyp(const MiscRegIndex miscReg, ExceptionLevel el, 27111582SDylan.Johnson@ARM.com bool isRead, CPTR cptr, HCR hcr, bool * isVfpNeon); 27210037SARM gem5 Developersbool msrMrs64TrapToMon(const MiscRegIndex miscReg, CPTR cptr, 27310037SARM gem5 Developers ExceptionLevel el, bool * isVfpNeon); 27410037SARM gem5 Developers 27510037SARM gem5 Developersbool SPAlignmentCheckEnabled(ThreadContext* tc); 27610037SARM gem5 Developers 2777707Sgblack@eecs.umich.eduuint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp); 2786757SAli.Saidi@ARM.com 2797693SAli.Saidi@ARM.comvoid skipFunction(ThreadContext *tc); 2807693SAli.Saidi@ARM.com 2817720Sgblack@eecs.umich.eduinline void 28210417Sandreas.hansson@arm.comadvancePC(PCState &pc, const StaticInstPtr &inst) 2837720Sgblack@eecs.umich.edu{ 2847720Sgblack@eecs.umich.edu inst->advancePC(pc); 2857720Sgblack@eecs.umich.edu} 2867720Sgblack@eecs.umich.edu 2877752SWilliam.Wang@arm.comAddr truncPage(Addr addr); 2887752SWilliam.Wang@arm.comAddr roundPage(Addr addr); 2897752SWilliam.Wang@arm.com 2908300Schander.sudanthi@arm.cominline uint64_t 2918300Schander.sudanthi@arm.comgetExecutingAsid(ThreadContext *tc) 2928300Schander.sudanthi@arm.com{ 2938300Schander.sudanthi@arm.com return tc->readMiscReg(MISCREG_CONTEXTIDR); 2948300Schander.sudanthi@arm.com} 2958300Schander.sudanthi@arm.com 29610037SARM gem5 Developers// Decodes the register index to access based on the fields used in a MSR 29710037SARM gem5 Developers// or MRS instruction 29810037SARM gem5 Developersbool 29910037SARM gem5 DevelopersdecodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int ®Idx, 30010037SARM gem5 Developers CPSR cpsr, SCR scr, NSACR nsacr, 30110037SARM gem5 Developers bool checkSecurity = true); 30210037SARM gem5 Developers 30310037SARM gem5 Developers// This wrapper function is used to turn the register index into a source 30410037SARM gem5 Developers// parameter for the instruction. See Operands.isa 30510037SARM gem5 Developersstatic inline int 30610037SARM gem5 DevelopersdecodeMrsMsrBankedIntRegIndex(uint8_t sysM, bool r) 30710037SARM gem5 Developers{ 30810037SARM gem5 Developers int regIdx; 30910037SARM gem5 Developers bool isIntReg; 31010037SARM gem5 Developers bool validReg; 31110037SARM gem5 Developers 31210037SARM gem5 Developers validReg = decodeMrsMsrBankedReg(sysM, r, isIntReg, regIdx, 0, 0, 0, false); 31310037SARM gem5 Developers return (validReg && isIntReg) ? regIdx : INTREG_DUMMY; 31410037SARM gem5 Developers} 31510037SARM gem5 Developers 31610037SARM gem5 Developers/** 31710037SARM gem5 Developers * Returns the n. of PA bits corresponding to the specified encoding. 31810037SARM gem5 Developers */ 31910037SARM gem5 Developersint decodePhysAddrRange64(uint8_t pa_enc); 32010037SARM gem5 Developers 32110037SARM gem5 Developers/** 32210037SARM gem5 Developers * Returns the encoding corresponding to the specified n. of PA bits. 32310037SARM gem5 Developers */ 32410037SARM gem5 Developersuint8_t encodePhysAddrRange64(int pa_size); 32510037SARM gem5 Developers 3268902Sandreas.hansson@arm.com} 3276019Shines@cs.fsu.edu 3286019Shines@cs.fsu.edu#endif 329