utility.cc revision 8886:5e8d2d7162b0 
1/*
2 * Copyright (c) 2009-2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40
41#include "arch/arm/faults.hh"
42#include "arch/arm/isa_traits.hh"
43#include "arch/arm/tlb.hh"
44#include "arch/arm/utility.hh"
45#include "arch/arm/vtophys.hh"
46#include "config/use_checker.hh"
47#include "cpu/base.hh"
48#include "cpu/thread_context.hh"
49#include "mem/fs_translating_port_proxy.hh"
50#include "params/BaseCPU.hh"
51#include "sim/full_system.hh"
52
53namespace ArmISA {
54
55void
56initCPU(ThreadContext *tc, int cpuId)
57{
58    // Reset CP15?? What does that mean -- ali
59
60    // FPEXC.EN = 0
61    if (tc->getCpuPtr()->params()->defer_registration)
62       return;
63
64    static Fault reset = new Reset;
65    reset->invoke(tc);
66}
67
68uint64_t
69getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
70{
71    if (!FullSystem) {
72        panic("getArgument() only implemented for full system mode.\n");
73        M5_DUMMY_RETURN
74    }
75
76    if (size == (uint16_t)(-1))
77        size = ArmISA::MachineBytes;
78    if (fp)
79        panic("getArgument(): Floating point arguments not implemented\n");
80
81    if (number < NumArgumentRegs) {
82        // If the argument is 64 bits, it must be in an even regiser
83        // number. Increment the number here if it isn't even.
84        if (size == sizeof(uint64_t)) {
85            if ((number % 2) != 0)
86                number++;
87            // Read the two halves of the data. Number is inc here to
88            // get the second half of the 64 bit reg.
89            uint64_t tmp;
90            tmp = tc->readIntReg(number++);
91            tmp |= tc->readIntReg(number) << 32;
92            return tmp;
93        } else {
94           return tc->readIntReg(number);
95        }
96    } else {
97        Addr sp = tc->readIntReg(StackPointerReg);
98        FSTranslatingPortProxy &vp = tc->getVirtProxy();
99        uint64_t arg;
100        if (size == sizeof(uint64_t)) {
101            // If the argument is even it must be aligned
102            if ((number % 2) != 0)
103                number++;
104            arg = vp.read<uint64_t>(sp +
105                    (number-NumArgumentRegs) * sizeof(uint32_t));
106            // since two 32 bit args == 1 64 bit arg, increment number
107            number++;
108        } else {
109            arg = vp.read<uint32_t>(sp +
110                           (number-NumArgumentRegs) * sizeof(uint32_t));
111        }
112        return arg;
113    }
114}
115
116void
117skipFunction(ThreadContext *tc)
118{
119    TheISA::PCState newPC = tc->pcState();
120    newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1));
121#if USE_CHECKER
122    tc->pcStateNoRecord(newPC);
123#else
124    tc->pcState(newPC);
125#endif
126}
127
128void
129copyRegs(ThreadContext *src, ThreadContext *dest)
130{
131    int i;
132
133    int saved_mode = ((CPSR)src->readMiscReg(MISCREG_CPSR)).mode;
134
135    // Make sure we're in user mode, so we can easily see all the registers
136    // in the copy loop
137    src->setMiscReg(MISCREG_CPSR_MODE, MODE_USER);
138    dest->setMiscReg(MISCREG_CPSR_MODE, MODE_USER);
139
140    for(i = 0; i < TheISA::NumIntRegs; i++)
141        dest->setIntReg(i, src->readIntReg(i));
142
143    // Restore us back to the old mode
144    src->setMiscReg(MISCREG_CPSR_MODE, saved_mode);
145    dest->setMiscReg(MISCREG_CPSR_MODE, saved_mode);
146
147    for(i = 0; i < TheISA::NumFloatRegs; i++)
148        dest->setFloatReg(i, src->readFloatReg(i));
149    for(i = 0; i < TheISA::NumMiscRegs; i++)
150        dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
151
152    // setMiscReg "with effect" will set the misc register mapping correctly.
153    // e.g. updateRegMap(val)
154    dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
155
156    // Copy over the PC State
157    dest->pcState(src->pcState());
158
159    // Invalidate the tlb misc register cache
160    dest->getITBPtr()->invalidateMiscReg();
161    dest->getDTBPtr()->invalidateMiscReg();
162}
163
164Addr
165truncPage(Addr addr)
166{
167    return addr & ~(PageBytes - 1);
168}
169
170Addr
171roundPage(Addr addr)
172{
173    return (addr + PageBytes - 1) & ~(PageBytes - 1);
174}
175
176} // namespace ArmISA
177