utility.cc revision 7749:859e8bc1cdc2
1/* 2 * Copyright (c) 2009-2010 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Ali Saidi 38 */ 39 40 41#include "arch/arm/faults.hh" 42#include "arch/arm/isa_traits.hh" 43#include "arch/arm/utility.hh" 44#include "cpu/thread_context.hh" 45 46#if FULL_SYSTEM 47#include "arch/arm/vtophys.hh" 48#include "mem/vport.hh" 49#endif 50 51#include "arch/arm/tlb.hh" 52 53namespace ArmISA { 54 55void 56initCPU(ThreadContext *tc, int cpuId) 57{ 58 // Reset CP15?? What does that mean -- ali 59 60 // FPEXC.EN = 0 61 62 static Fault reset = new Reset; 63 if (cpuId == 0) 64 reset->invoke(tc); 65} 66 67uint64_t 68getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) 69{ 70#if FULL_SYSTEM 71 if (size == (uint16_t)(-1)) 72 size = ArmISA::MachineBytes; 73 if (fp) 74 panic("getArgument(): Floating point arguments not implemented\n"); 75 76 if (number < NumArgumentRegs) { 77 // If the argument is 64 bits, it must be in an even regiser number 78 // Increment the number here if it isn't even 79 if (size == sizeof(uint64_t)) { 80 if ((number % 2) != 0) 81 number++; 82 // Read the two halves of the data 83 // number is inc here to get the second half of the 64 bit reg 84 uint64_t tmp; 85 tmp = tc->readIntReg(number++); 86 tmp |= tc->readIntReg(number) << 32; 87 return tmp; 88 } else { 89 return tc->readIntReg(number); 90 } 91 } else { 92 Addr sp = tc->readIntReg(StackPointerReg); 93 VirtualPort *vp = tc->getVirtPort(); 94 uint64_t arg; 95 if (size == sizeof(uint64_t)) { 96 // If the argument is even it must be aligned 97 if ((number % 2) != 0) 98 number++; 99 arg = vp->read<uint64_t>(sp + 100 (number-NumArgumentRegs) * sizeof(uint32_t)); 101 // since two 32 bit args == 1 64 bit arg, increment number 102 number++; 103 } else { 104 arg = vp->read<uint32_t>(sp + 105 (number-NumArgumentRegs) * sizeof(uint32_t)); 106 } 107 return arg; 108 } 109#else 110 panic("getArgument() only implemented for FULL_SYSTEM\n"); 111 M5_DUMMY_RETURN 112#endif 113} 114 115Fault 116setCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2) 117{ 118 return new UnimpFault(csprintf("MCR CP15: CRn: %d opc1: %d CRm: %d opc1: %d\n", 119 CRn, opc1, CRm, opc2)); 120} 121 122Fault 123readCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2) 124{ 125 return new UnimpFault(csprintf("MRC CP15: CRn: %d opc1: %d CRm: %d opc1: %d\n", 126 CRn, opc1, CRm, opc2)); 127 128} 129 130void 131skipFunction(ThreadContext *tc) 132{ 133 TheISA::PCState newPC = tc->pcState(); 134 newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1)); 135 tc->pcState(newPC); 136} 137 138void 139copyRegs(ThreadContext *src, ThreadContext *dest) 140{ 141 int i; 142 for(i = 0; i < TheISA::NumIntRegs; i++) 143 dest->setIntReg(i, src->readIntReg(i)); 144 for(i = 0; i < TheISA::NumFloatRegs; i++) 145 dest->setFloatReg(i, src->readFloatReg(i)); 146 for(i = 0; i < TheISA::NumMiscRegs; i++) 147 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); 148 149 // setMiscReg "with effect" will set the misc register mapping correctly. 150 // e.g. updateRegMap(val) 151 dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR)); 152 153 // Copy over the PC State 154 dest->pcState(src->pcState()); 155 156 // Invalidate the tlb misc register cache 157 dest->getITBPtr()->invalidateMiscReg(); 158 dest->getDTBPtr()->invalidateMiscReg(); 159} 160} 161