utility.cc revision 13759 
1/*
2 * Copyright (c) 2009-2014, 2016-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#include "arch/arm/utility.hh"
41
42#include <memory>
43
44#include "arch/arm/faults.hh"
45#include "arch/arm/isa_traits.hh"
46#include "arch/arm/system.hh"
47#include "arch/arm/tlb.hh"
48#include "arch/arm/vtophys.hh"
49#include "cpu/base.hh"
50#include "cpu/checker/cpu.hh"
51#include "cpu/thread_context.hh"
52#include "mem/fs_translating_port_proxy.hh"
53#include "sim/full_system.hh"
54
55namespace ArmISA {
56
57void
58initCPU(ThreadContext *tc, int cpuId)
59{
60    // Reset CP15?? What does that mean -- ali
61
62    // FPEXC.EN = 0
63
64    static Fault reset = std::make_shared<Reset>();
65    reset->invoke(tc);
66}
67
68uint64_t
69getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
70{
71    if (!FullSystem) {
72        panic("getArgument() only implemented for full system mode.\n");
73        M5_DUMMY_RETURN
74    }
75
76    if (fp)
77        panic("getArgument(): Floating point arguments not implemented\n");
78
79    if (inAArch64(tc)) {
80        if (size == (uint16_t)(-1))
81            size = sizeof(uint64_t);
82
83        if (number < 8 /*NumArgumentRegs64*/) {
84               return tc->readIntReg(number);
85        } else {
86            panic("getArgument(): No support reading stack args for AArch64\n");
87        }
88    } else {
89        if (size == (uint16_t)(-1))
90            // todo: should this not be sizeof(uint32_t) rather?
91            size = ArmISA::MachineBytes;
92
93        if (number < NumArgumentRegs) {
94            // If the argument is 64 bits, it must be in an even regiser
95            // number. Increment the number here if it isn't even.
96            if (size == sizeof(uint64_t)) {
97                if ((number % 2) != 0)
98                    number++;
99                // Read the two halves of the data. Number is inc here to
100                // get the second half of the 64 bit reg.
101                uint64_t tmp;
102                tmp = tc->readIntReg(number++);
103                tmp |= tc->readIntReg(number) << 32;
104                return tmp;
105            } else {
106               return tc->readIntReg(number);
107            }
108        } else {
109            Addr sp = tc->readIntReg(StackPointerReg);
110            FSTranslatingPortProxy &vp = tc->getVirtProxy();
111            uint64_t arg;
112            if (size == sizeof(uint64_t)) {
113                // If the argument is even it must be aligned
114                if ((number % 2) != 0)
115                    number++;
116                arg = vp.read<uint64_t>(sp +
117                        (number-NumArgumentRegs) * sizeof(uint32_t));
118                // since two 32 bit args == 1 64 bit arg, increment number
119                number++;
120            } else {
121                arg = vp.read<uint32_t>(sp +
122                               (number-NumArgumentRegs) * sizeof(uint32_t));
123            }
124            return arg;
125        }
126    }
127    panic("getArgument() should always return\n");
128}
129
130void
131skipFunction(ThreadContext *tc)
132{
133    PCState newPC = tc->pcState();
134    if (inAArch64(tc)) {
135        newPC.set(tc->readIntReg(INTREG_X30));
136    } else {
137        newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1));
138    }
139
140    CheckerCPU *checker = tc->getCheckerCpuPtr();
141    if (checker) {
142        tc->pcStateNoRecord(newPC);
143    } else {
144        tc->pcState(newPC);
145    }
146}
147
148static void
149copyVecRegs(ThreadContext *src, ThreadContext *dest)
150{
151    auto src_mode = RenameMode<ArmISA::ISA>::mode(src->pcState());
152
153    // The way vector registers are copied (VecReg vs VecElem) is relevant
154    // in the O3 model only.
155    if (src_mode == Enums::Full) {
156        for (auto idx = 0; idx < NumVecRegs; idx++)
157            dest->setVecRegFlat(idx, src->readVecRegFlat(idx));
158    } else {
159        for (auto idx = 0; idx < NumVecRegs; idx++)
160            for (auto elem_idx = 0; elem_idx < NumVecElemPerVecReg; elem_idx++)
161                dest->setVecElemFlat(
162                    idx, elem_idx, src->readVecElemFlat(idx, elem_idx));
163    }
164}
165
166void
167copyRegs(ThreadContext *src, ThreadContext *dest)
168{
169    for (int i = 0; i < NumIntRegs; i++)
170        dest->setIntRegFlat(i, src->readIntRegFlat(i));
171
172    for (int i = 0; i < NumFloatRegs; i++)
173        dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
174
175    for (int i = 0; i < NumCCRegs; i++)
176        dest->setCCReg(i, src->readCCReg(i));
177
178    for (int i = 0; i < NumMiscRegs; i++)
179        dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
180
181    copyVecRegs(src, dest);
182
183    // setMiscReg "with effect" will set the misc register mapping correctly.
184    // e.g. updateRegMap(val)
185    dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
186
187    // Copy over the PC State
188    dest->pcState(src->pcState());
189
190    // Invalidate the tlb misc register cache
191    dynamic_cast<TLB *>(dest->getITBPtr())->invalidateMiscReg();
192    dynamic_cast<TLB *>(dest->getDTBPtr())->invalidateMiscReg();
193}
194
195bool
196inSecureState(ThreadContext *tc)
197{
198    SCR scr = inAArch64(tc) ? tc->readMiscReg(MISCREG_SCR_EL3) :
199        tc->readMiscReg(MISCREG_SCR);
200    return ArmSystem::haveSecurity(tc) && inSecureState(
201        scr, tc->readMiscReg(MISCREG_CPSR));
202}
203
204inline bool
205isSecureBelowEL3(ThreadContext *tc)
206{
207    SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
208    return ArmSystem::haveEL(tc, EL3) && scr.ns == 0;
209}
210
211bool
212inAArch64(ThreadContext *tc)
213{
214    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
215    return opModeIs64((OperatingMode) (uint8_t) cpsr.mode);
216}
217
218bool
219longDescFormatInUse(ThreadContext *tc)
220{
221    TTBCR ttbcr = tc->readMiscReg(MISCREG_TTBCR);
222    return ArmSystem::haveLPAE(tc) && ttbcr.eae;
223}
224
225RegVal
226readMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
227{
228    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
229    const ExceptionLevel current_el =
230        opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
231
232    const bool is_secure = isSecureBelowEL3(tc);
233
234    switch (current_el) {
235      case EL0:
236        // Note: in MsrMrs instruction we read the register value before
237        // checking access permissions. This means that EL0 entry must
238        // be part of the table even if MPIDR is not accessible in user
239        // mode.
240        warn_once("Trying to read MPIDR at EL0\n");
241        M5_FALLTHROUGH;
242      case EL1:
243        if (ArmSystem::haveEL(tc, EL2) && !is_secure)
244            return tc->readMiscReg(MISCREG_VMPIDR_EL2);
245        else
246            return getMPIDR(arm_sys, tc);
247      case EL2:
248      case EL3:
249        return getMPIDR(arm_sys, tc);
250      default:
251        panic("Invalid EL for reading MPIDR register\n");
252    }
253}
254
255RegVal
256getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
257{
258    // Multiprocessor Affinity Register MPIDR from Cortex(tm)-A15 Technical
259    // Reference Manual
260    //
261    // bit   31 - Multi-processor extensions available
262    // bit   30 - Uni-processor system
263    // bit   24 - Multi-threaded cores
264    // bit 11-8 - Cluster ID
265    // bit  1-0 - CPU ID
266    //
267    // We deliberately extend both the Cluster ID and CPU ID fields to allow
268    // for simulation of larger systems
269    assert((0 <= tc->cpuId()) && (tc->cpuId() < 256));
270    assert(tc->socketId() < 65536);
271    if (arm_sys->multiThread) {
272       return 0x80000000 | // multiprocessor extensions available
273              0x01000000 | // multi-threaded cores
274              tc->contextId();
275    } else if (arm_sys->multiProc) {
276       return 0x80000000 | // multiprocessor extensions available
277              tc->cpuId() | tc->socketId() << 8;
278    } else {
279       return 0x80000000 |  // multiprocessor extensions available
280              0x40000000 |  // in up system
281              tc->cpuId() | tc->socketId() << 8;
282    }
283}
284
285bool
286ELIs64(ThreadContext *tc, ExceptionLevel el)
287{
288    return !ELIs32(tc, el);
289}
290
291bool
292ELIs32(ThreadContext *tc, ExceptionLevel el)
293{
294    bool known, aarch32;
295    std::tie(known, aarch32) = ELUsingAArch32K(tc, el);
296    panic_if(!known, "EL state is UNKNOWN");
297    return aarch32;
298}
299
300bool
301ELIsInHost(ThreadContext *tc, ExceptionLevel el)
302{
303    if (!ArmSystem::haveVirtualization(tc)) {
304        return false;
305    }
306    HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
307    return (!isSecureBelowEL3(tc) && !ELIs32(tc, EL2) && hcr.e2h == 1 &&
308            (el == EL2 || (el == EL0 && hcr.tge == 1)));
309}
310
311std::pair<bool, bool>
312ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el)
313{
314    // Return true if the specified EL is in aarch32 state.
315    const bool have_el3 = ArmSystem::haveSecurity(tc);
316    const bool have_el2 = ArmSystem::haveVirtualization(tc);
317
318    panic_if(el == EL2 && !have_el2, "Asking for EL2 when it doesn't exist");
319    panic_if(el == EL3 && !have_el3, "Asking for EL3 when it doesn't exist");
320
321    bool known, aarch32;
322    known = aarch32 = false;
323    if (ArmSystem::highestELIs64(tc) && ArmSystem::highestEL(tc) == el) {
324        // Target EL is the highest one in a system where
325        // the highest is using AArch64.
326        known = true; aarch32 = false;
327    } else if (!ArmSystem::highestELIs64(tc)) {
328        // All ELs are using AArch32:
329        known = true; aarch32 = true;
330    } else {
331        SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
332        bool aarch32_below_el3 = (have_el3 && scr.rw == 0);
333
334        HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
335        bool aarch32_at_el1 = (aarch32_below_el3
336                               || (have_el2
337                               && !isSecureBelowEL3(tc) && hcr.rw == 0));
338
339        // Only know if EL0 using AArch32 from PSTATE
340        if (el == EL0 && !aarch32_at_el1) {
341            // EL0 controlled by PSTATE
342            CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
343
344            known = (cpsr.el == EL0);
345            aarch32 = (cpsr.width == 1);
346        } else {
347            known = true;
348            aarch32 = (aarch32_below_el3 && el != EL3)
349                      || (aarch32_at_el1 && (el == EL0 || el == EL1) );
350        }
351    }
352
353    return std::make_pair(known, aarch32);
354}
355
356bool
357isBigEndian64(ThreadContext *tc)
358{
359    switch (opModeToEL(currOpMode(tc))) {
360      case EL3:
361        return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).ee;
362      case EL2:
363        return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).ee;
364      case EL1:
365        return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).ee;
366      case EL0:
367        return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).e0e;
368      default:
369        panic("Invalid exception level");
370        break;
371    }
372}
373
374bool
375badMode32(ThreadContext *tc, OperatingMode mode)
376{
377    return unknownMode32(mode) || !ArmSystem::haveEL(tc, opModeToEL(mode));
378}
379
380bool
381badMode(ThreadContext *tc, OperatingMode mode)
382{
383    return unknownMode(mode) || !ArmSystem::haveEL(tc, opModeToEL(mode));
384}
385
386Addr
387purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
388                 TTBCR tcr)
389{
390    switch (el) {
391      case EL0:
392      case EL1:
393        if (bits(addr, 55, 48) == 0xFF && tcr.tbi1)
394            return addr | mask(63, 55);
395        else if (!bits(addr, 55, 48) && tcr.tbi0)
396            return bits(addr,55, 0);
397        break;
398      case EL2:
399        assert(ArmSystem::haveVirtualization(tc));
400        tcr = tc->readMiscReg(MISCREG_TCR_EL2);
401        if (tcr.tbi)
402            return addr & mask(56);
403        break;
404      case EL3:
405        assert(ArmSystem::haveSecurity(tc));
406        if (tcr.tbi)
407            return addr & mask(56);
408        break;
409      default:
410        panic("Invalid exception level");
411        break;
412    }
413
414    return addr;  // Nothing to do if this is not a tagged address
415}
416
417Addr
418purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el)
419{
420    TTBCR tcr;
421
422    switch (el) {
423      case EL0:
424      case EL1:
425        tcr = tc->readMiscReg(MISCREG_TCR_EL1);
426        if (bits(addr, 55, 48) == 0xFF && tcr.tbi1)
427            return addr | mask(63, 55);
428        else if (!bits(addr, 55, 48) && tcr.tbi0)
429            return bits(addr,55, 0);
430        break;
431      case EL2:
432        assert(ArmSystem::haveVirtualization(tc));
433        tcr = tc->readMiscReg(MISCREG_TCR_EL2);
434        if (tcr.tbi)
435            return addr & mask(56);
436        break;
437      case EL3:
438        assert(ArmSystem::haveSecurity(tc));
439        tcr = tc->readMiscReg(MISCREG_TCR_EL3);
440        if (tcr.tbi)
441            return addr & mask(56);
442        break;
443      default:
444        panic("Invalid exception level");
445        break;
446    }
447
448    return addr;  // Nothing to do if this is not a tagged address
449}
450
451Addr
452truncPage(Addr addr)
453{
454    return addr & ~(PageBytes - 1);
455}
456
457Addr
458roundPage(Addr addr)
459{
460    return (addr + PageBytes - 1) & ~(PageBytes - 1);
461}
462
463bool
464mcrMrc15TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
465                  HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
466{
467    bool        isRead;
468    uint32_t    crm;
469    IntRegIndex rt;
470    uint32_t    crn;
471    uint32_t    opc1;
472    uint32_t    opc2;
473    bool        trapToHype = false;
474
475
476    if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
477        mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
478        trapToHype  = ((uint32_t) hstr) & (1 << crn);
479        trapToHype |= hdcr.tpm  && (crn == 9) && (crm >= 12);
480        trapToHype |= hcr.tidcp && (
481            ((crn ==  9) && ((crm <= 2) || ((crm >= 5) && (crm <= 8)))) ||
482            ((crn == 10) && ((crm <= 1) ||  (crm == 4) || (crm == 8)))  ||
483            ((crn == 11) && ((crm <= 8) ||  (crm == 15)))               );
484
485        if (!trapToHype) {
486            switch (unflattenMiscReg(miscReg)) {
487              case MISCREG_CPACR:
488                trapToHype = hcptr.tcpac;
489                break;
490              case MISCREG_REVIDR:
491              case MISCREG_TCMTR:
492              case MISCREG_TLBTR:
493              case MISCREG_AIDR:
494                trapToHype = hcr.tid1;
495                break;
496              case MISCREG_CTR:
497              case MISCREG_CCSIDR:
498              case MISCREG_CLIDR:
499              case MISCREG_CSSELR:
500                trapToHype = hcr.tid2;
501                break;
502              case MISCREG_ID_PFR0:
503              case MISCREG_ID_PFR1:
504              case MISCREG_ID_DFR0:
505              case MISCREG_ID_AFR0:
506              case MISCREG_ID_MMFR0:
507              case MISCREG_ID_MMFR1:
508              case MISCREG_ID_MMFR2:
509              case MISCREG_ID_MMFR3:
510              case MISCREG_ID_ISAR0:
511              case MISCREG_ID_ISAR1:
512              case MISCREG_ID_ISAR2:
513              case MISCREG_ID_ISAR3:
514              case MISCREG_ID_ISAR4:
515              case MISCREG_ID_ISAR5:
516                trapToHype = hcr.tid3;
517                break;
518              case MISCREG_DCISW:
519              case MISCREG_DCCSW:
520              case MISCREG_DCCISW:
521                trapToHype = hcr.tsw;
522                break;
523              case MISCREG_DCIMVAC:
524              case MISCREG_DCCIMVAC:
525              case MISCREG_DCCMVAC:
526                trapToHype = hcr.tpc;
527                break;
528              case MISCREG_ICIMVAU:
529              case MISCREG_ICIALLU:
530              case MISCREG_ICIALLUIS:
531              case MISCREG_DCCMVAU:
532                trapToHype = hcr.tpu;
533                break;
534              case MISCREG_TLBIALLIS:
535              case MISCREG_TLBIMVAIS:
536              case MISCREG_TLBIASIDIS:
537              case MISCREG_TLBIMVAAIS:
538              case MISCREG_TLBIMVALIS:
539              case MISCREG_TLBIMVAALIS:
540              case MISCREG_DTLBIALL:
541              case MISCREG_ITLBIALL:
542              case MISCREG_DTLBIMVA:
543              case MISCREG_ITLBIMVA:
544              case MISCREG_DTLBIASID:
545              case MISCREG_ITLBIASID:
546              case MISCREG_TLBIMVAA:
547              case MISCREG_TLBIALL:
548              case MISCREG_TLBIMVA:
549              case MISCREG_TLBIMVAL:
550              case MISCREG_TLBIMVAAL:
551              case MISCREG_TLBIASID:
552                trapToHype = hcr.ttlb;
553                break;
554              case MISCREG_ACTLR:
555                trapToHype = hcr.tac;
556                break;
557              case MISCREG_SCTLR:
558              case MISCREG_TTBR0:
559              case MISCREG_TTBR1:
560              case MISCREG_TTBCR:
561              case MISCREG_DACR:
562              case MISCREG_DFSR:
563              case MISCREG_IFSR:
564              case MISCREG_DFAR:
565              case MISCREG_IFAR:
566              case MISCREG_ADFSR:
567              case MISCREG_AIFSR:
568              case MISCREG_PRRR:
569              case MISCREG_NMRR:
570              case MISCREG_MAIR0:
571              case MISCREG_MAIR1:
572              case MISCREG_CONTEXTIDR:
573                trapToHype = hcr.tvm & !isRead;
574                break;
575              case MISCREG_PMCR:
576                trapToHype = hdcr.tpmcr;
577                break;
578              // No default action needed
579              default:
580                break;
581            }
582        }
583    }
584    return trapToHype;
585}
586
587
588bool
589mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
590                  HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
591{
592    bool        isRead;
593    uint32_t    crm;
594    IntRegIndex rt;
595    uint32_t    crn;
596    uint32_t    opc1;
597    uint32_t    opc2;
598    bool        trapToHype = false;
599
600    if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
601        mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
602        inform("trap check M:%x N:%x 1:%x 2:%x hdcr %x, hcptr %x, hstr %x\n",
603                crm, crn, opc1, opc2, hdcr, hcptr, hstr);
604        trapToHype  = hdcr.tda  && (opc1 == 0);
605        trapToHype |= hcptr.tta && (opc1 == 1);
606        if (!trapToHype) {
607            switch (unflattenMiscReg(miscReg)) {
608              case MISCREG_DBGOSLSR:
609              case MISCREG_DBGOSLAR:
610              case MISCREG_DBGOSDLR:
611              case MISCREG_DBGPRCR:
612                trapToHype = hdcr.tdosa;
613                break;
614              case MISCREG_DBGDRAR:
615              case MISCREG_DBGDSAR:
616                trapToHype = hdcr.tdra;
617                break;
618              case MISCREG_JIDR:
619                trapToHype = hcr.tid0;
620                break;
621              case MISCREG_JOSCR:
622              case MISCREG_JMCR:
623                trapToHype = hstr.tjdbx;
624                break;
625              case MISCREG_TEECR:
626              case MISCREG_TEEHBR:
627                trapToHype = hstr.ttee;
628                break;
629              // No default action needed
630              default:
631                break;
632            }
633        }
634    }
635    return trapToHype;
636}
637
638bool
639mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr,
640                    HCR hcr, uint32_t iss)
641{
642    uint32_t    crm;
643    IntRegIndex rt;
644    uint32_t    crn;
645    uint32_t    opc1;
646    uint32_t    opc2;
647    bool        isRead;
648    bool        trapToHype = false;
649
650    if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
651        // This is technically the wrong function, but we can re-use it for
652        // the moment because we only need one field, which overlaps with the
653        // mcrmrc layout
654        mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
655        trapToHype = ((uint32_t) hstr) & (1 << crm);
656
657        if (!trapToHype) {
658            switch (unflattenMiscReg(miscReg)) {
659              case MISCREG_SCTLR:
660              case MISCREG_TTBR0:
661              case MISCREG_TTBR1:
662              case MISCREG_TTBCR:
663              case MISCREG_DACR:
664              case MISCREG_DFSR:
665              case MISCREG_IFSR:
666              case MISCREG_DFAR:
667              case MISCREG_IFAR:
668              case MISCREG_ADFSR:
669              case MISCREG_AIFSR:
670              case MISCREG_PRRR:
671              case MISCREG_NMRR:
672              case MISCREG_MAIR0:
673              case MISCREG_MAIR1:
674              case MISCREG_CONTEXTIDR:
675                trapToHype = hcr.tvm & !isRead;
676                break;
677              // No default action needed
678              default:
679                break;
680            }
681        }
682    }
683    return trapToHype;
684}
685
686bool
687decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx,
688                      CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
689{
690    OperatingMode mode = MODE_UNDEFINED;
691    bool          ok = true;
692
693    // R mostly indicates if its a int register or a misc reg, we override
694    // below if the few corner cases
695    isIntReg = !r;
696    // Loosely based on ARM ARM issue C section B9.3.10
697    if (r) {
698        switch (sysM)
699        {
700          case 0xE:
701            regIdx = MISCREG_SPSR_FIQ;
702            mode   = MODE_FIQ;
703            break;
704          case 0x10:
705            regIdx = MISCREG_SPSR_IRQ;
706            mode   = MODE_IRQ;
707            break;
708          case 0x12:
709            regIdx = MISCREG_SPSR_SVC;
710            mode   = MODE_SVC;
711            break;
712          case 0x14:
713            regIdx = MISCREG_SPSR_ABT;
714            mode   = MODE_ABORT;
715            break;
716          case 0x16:
717            regIdx = MISCREG_SPSR_UND;
718            mode   = MODE_UNDEFINED;
719            break;
720          case 0x1C:
721            regIdx = MISCREG_SPSR_MON;
722            mode   = MODE_MON;
723            break;
724          case 0x1E:
725            regIdx = MISCREG_SPSR_HYP;
726            mode   = MODE_HYP;
727            break;
728          default:
729            ok = false;
730            break;
731        }
732    } else {
733        int sysM4To3 = bits(sysM, 4, 3);
734
735        if (sysM4To3 == 0) {
736            mode = MODE_USER;
737            regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8);
738        } else if (sysM4To3 == 1) {
739            mode = MODE_FIQ;
740            regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8);
741        } else if (sysM4To3 == 3) {
742            if (bits(sysM, 1) == 0) {
743                mode = MODE_MON;
744                regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
745            } else {
746                mode = MODE_HYP;
747                if (bits(sysM, 0) == 1) {
748                    regIdx = intRegInMode(mode, 13); // R13 in HYP
749                } else {
750                    isIntReg = false;
751                    regIdx   = MISCREG_ELR_HYP;
752                }
753            }
754        } else { // Other Banked registers
755            int sysM2 = bits(sysM, 2);
756            int sysM1 = bits(sysM, 1);
757
758            mode  = (OperatingMode) ( ((sysM2 ||  sysM1) << 0) |
759                                      (1                 << 1) |
760                                      ((sysM2 && !sysM1) << 2) |
761                                      ((sysM2 &&  sysM1) << 3) |
762                                      (1                 << 4) );
763            regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
764            // Don't flatten the register here. This is going to go through
765            // setIntReg() which will do the flattening
766            ok &= mode != cpsr.mode;
767        }
768    }
769
770    // Check that the requested register is accessable from the current mode
771    if (ok && checkSecurity && mode != cpsr.mode) {
772        switch (cpsr.mode)
773        {
774          case MODE_USER:
775            ok = false;
776            break;
777          case MODE_FIQ:
778            ok &=  mode != MODE_HYP;
779            ok &= (mode != MODE_MON) || !scr.ns;
780            break;
781          case MODE_HYP:
782            ok &=  mode != MODE_MON;
783            ok &= (mode != MODE_FIQ) || !nsacr.rfr;
784            break;
785          case MODE_IRQ:
786          case MODE_SVC:
787          case MODE_ABORT:
788          case MODE_UNDEFINED:
789          case MODE_SYSTEM:
790            ok &=  mode != MODE_HYP;
791            ok &= (mode != MODE_MON) || !scr.ns;
792            ok &= (mode != MODE_FIQ) || !nsacr.rfr;
793            break;
794          // can access everything, no further checks required
795          case MODE_MON:
796            break;
797          default:
798            panic("unknown Mode 0x%x\n", cpsr.mode);
799            break;
800        }
801    }
802    return (ok);
803}
804
805bool
806SPAlignmentCheckEnabled(ThreadContext* tc)
807{
808    switch (opModeToEL(currOpMode(tc))) {
809      case EL3:
810        return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).sa;
811      case EL2:
812        return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).sa;
813      case EL1:
814        return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa;
815      case EL0:
816        return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa0;
817      default:
818        panic("Invalid exception level");
819        break;
820    }
821}
822
823int
824decodePhysAddrRange64(uint8_t pa_enc)
825{
826    switch (pa_enc) {
827      case 0x0:
828        return 32;
829      case 0x1:
830        return 36;
831      case 0x2:
832        return 40;
833      case 0x3:
834        return 42;
835      case 0x4:
836        return 44;
837      case 0x5:
838      case 0x6:
839      case 0x7:
840        return 48;
841      default:
842        panic("Invalid phys. address range encoding");
843    }
844}
845
846uint8_t
847encodePhysAddrRange64(int pa_size)
848{
849    switch (pa_size) {
850      case 32:
851        return 0x0;
852      case 36:
853        return 0x1;
854      case 40:
855        return 0x2;
856      case 42:
857        return 0x3;
858      case 44:
859        return 0x4;
860      case 48:
861        return 0x5;
862      default:
863        panic("Invalid phys. address range");
864    }
865}
866
867} // namespace ArmISA
868