utility.cc revision 13364:055bf0fa0f02 
1/*
2 * Copyright (c) 2009-2014, 2016-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#include "arch/arm/utility.hh"
41
42#include <memory>
43
44#include "arch/arm/faults.hh"
45#include "arch/arm/isa_traits.hh"
46#include "arch/arm/system.hh"
47#include "arch/arm/tlb.hh"
48#include "arch/arm/vtophys.hh"
49#include "cpu/base.hh"
50#include "cpu/checker/cpu.hh"
51#include "cpu/thread_context.hh"
52#include "mem/fs_translating_port_proxy.hh"
53#include "sim/full_system.hh"
54
55namespace ArmISA {
56
57void
58initCPU(ThreadContext *tc, int cpuId)
59{
60    // Reset CP15?? What does that mean -- ali
61
62    // FPEXC.EN = 0
63
64    static Fault reset = std::make_shared<Reset>();
65    reset->invoke(tc);
66}
67
68uint64_t
69getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
70{
71    if (!FullSystem) {
72        panic("getArgument() only implemented for full system mode.\n");
73        M5_DUMMY_RETURN
74    }
75
76    if (fp)
77        panic("getArgument(): Floating point arguments not implemented\n");
78
79    if (inAArch64(tc)) {
80        if (size == (uint16_t)(-1))
81            size = sizeof(uint64_t);
82
83        if (number < 8 /*NumArgumentRegs64*/) {
84               return tc->readIntReg(number);
85        } else {
86            panic("getArgument(): No support reading stack args for AArch64\n");
87        }
88    } else {
89        if (size == (uint16_t)(-1))
90            // todo: should this not be sizeof(uint32_t) rather?
91            size = ArmISA::MachineBytes;
92
93        if (number < NumArgumentRegs) {
94            // If the argument is 64 bits, it must be in an even regiser
95            // number. Increment the number here if it isn't even.
96            if (size == sizeof(uint64_t)) {
97                if ((number % 2) != 0)
98                    number++;
99                // Read the two halves of the data. Number is inc here to
100                // get the second half of the 64 bit reg.
101                uint64_t tmp;
102                tmp = tc->readIntReg(number++);
103                tmp |= tc->readIntReg(number) << 32;
104                return tmp;
105            } else {
106               return tc->readIntReg(number);
107            }
108        } else {
109            Addr sp = tc->readIntReg(StackPointerReg);
110            FSTranslatingPortProxy &vp = tc->getVirtProxy();
111            uint64_t arg;
112            if (size == sizeof(uint64_t)) {
113                // If the argument is even it must be aligned
114                if ((number % 2) != 0)
115                    number++;
116                arg = vp.read<uint64_t>(sp +
117                        (number-NumArgumentRegs) * sizeof(uint32_t));
118                // since two 32 bit args == 1 64 bit arg, increment number
119                number++;
120            } else {
121                arg = vp.read<uint32_t>(sp +
122                               (number-NumArgumentRegs) * sizeof(uint32_t));
123            }
124            return arg;
125        }
126    }
127    panic("getArgument() should always return\n");
128}
129
130void
131skipFunction(ThreadContext *tc)
132{
133    PCState newPC = tc->pcState();
134    if (inAArch64(tc)) {
135        newPC.set(tc->readIntReg(INTREG_X30));
136    } else {
137        newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1));
138    }
139
140    CheckerCPU *checker = tc->getCheckerCpuPtr();
141    if (checker) {
142        tc->pcStateNoRecord(newPC);
143    } else {
144        tc->pcState(newPC);
145    }
146}
147
148void
149copyRegs(ThreadContext *src, ThreadContext *dest)
150{
151    for (int i = 0; i < NumIntRegs; i++)
152        dest->setIntRegFlat(i, src->readIntRegFlat(i));
153
154    for (int i = 0; i < NumFloatRegs; i++)
155        dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
156
157    for (int i = 0; i < NumVecRegs; i++)
158        dest->setVecRegFlat(i, src->readVecRegFlat(i));
159
160    for (int i = 0; i < NumCCRegs; i++)
161        dest->setCCReg(i, src->readCCReg(i));
162
163    for (int i = 0; i < NumMiscRegs; i++)
164        dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
165
166    // setMiscReg "with effect" will set the misc register mapping correctly.
167    // e.g. updateRegMap(val)
168    dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
169
170    // Copy over the PC State
171    dest->pcState(src->pcState());
172
173    // Invalidate the tlb misc register cache
174    dynamic_cast<TLB *>(dest->getITBPtr())->invalidateMiscReg();
175    dynamic_cast<TLB *>(dest->getDTBPtr())->invalidateMiscReg();
176}
177
178bool
179inSecureState(ThreadContext *tc)
180{
181    SCR scr = inAArch64(tc) ? tc->readMiscReg(MISCREG_SCR_EL3) :
182        tc->readMiscReg(MISCREG_SCR);
183    return ArmSystem::haveSecurity(tc) && inSecureState(
184        scr, tc->readMiscReg(MISCREG_CPSR));
185}
186
187inline bool
188isSecureBelowEL3(ThreadContext *tc)
189{
190    SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
191    return ArmSystem::haveEL(tc, EL3) && scr.ns == 0;
192}
193
194bool
195inAArch64(ThreadContext *tc)
196{
197    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
198    return opModeIs64((OperatingMode) (uint8_t) cpsr.mode);
199}
200
201bool
202longDescFormatInUse(ThreadContext *tc)
203{
204    TTBCR ttbcr = tc->readMiscReg(MISCREG_TTBCR);
205    return ArmSystem::haveLPAE(tc) && ttbcr.eae;
206}
207
208uint32_t
209getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
210{
211    // Multiprocessor Affinity Register MPIDR from Cortex(tm)-A15 Technical
212    // Reference Manual
213    //
214    // bit   31 - Multi-processor extensions available
215    // bit   30 - Uni-processor system
216    // bit   24 - Multi-threaded cores
217    // bit 11-8 - Cluster ID
218    // bit  1-0 - CPU ID
219    //
220    // We deliberately extend both the Cluster ID and CPU ID fields to allow
221    // for simulation of larger systems
222    assert((0 <= tc->cpuId()) && (tc->cpuId() < 256));
223    assert(tc->socketId() < 65536);
224    if (arm_sys->multiThread) {
225       return 0x80000000 | // multiprocessor extensions available
226              0x01000000 | // multi-threaded cores
227              tc->contextId();
228    } else if (arm_sys->multiProc) {
229       return 0x80000000 | // multiprocessor extensions available
230              tc->cpuId() | tc->socketId() << 8;
231    } else {
232       return 0x80000000 |  // multiprocessor extensions available
233              0x40000000 |  // in up system
234              tc->cpuId() | tc->socketId() << 8;
235    }
236}
237
238bool
239ELIs64(ThreadContext *tc, ExceptionLevel el)
240{
241    return !ELIs32(tc, el);
242}
243
244bool
245ELIs32(ThreadContext *tc, ExceptionLevel el)
246{
247    bool known, aarch32;
248    std::tie(known, aarch32) = ELUsingAArch32K(tc, el);
249    panic_if(!known, "EL state is UNKNOWN");
250    return aarch32;
251}
252
253std::pair<bool, bool>
254ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el)
255{
256    // Return true if the specified EL is in aarch32 state.
257    const bool have_el3 = ArmSystem::haveSecurity(tc);
258    const bool have_el2 = ArmSystem::haveVirtualization(tc);
259
260    panic_if(el == EL2 && !have_el2, "Asking for EL2 when it doesn't exist");
261    panic_if(el == EL3 && !have_el3, "Asking for EL3 when it doesn't exist");
262
263    bool known, aarch32;
264    known = aarch32 = false;
265    if (ArmSystem::highestELIs64(tc) && ArmSystem::highestEL(tc) == el) {
266        // Target EL is the highest one in a system where
267        // the highest is using AArch64.
268        known = true; aarch32 = false;
269    } else if (!ArmSystem::highestELIs64(tc)) {
270        // All ELs are using AArch32:
271        known = true; aarch32 = true;
272    } else {
273        SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
274        bool aarch32_below_el3 = (have_el3 && scr.rw == 0);
275
276        HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
277        bool aarch32_at_el1 = (aarch32_below_el3
278                               || (have_el2
279                               && !isSecureBelowEL3(tc) && hcr.rw == 0));
280
281        // Only know if EL0 using AArch32 from PSTATE
282        if (el == EL0 && !aarch32_at_el1) {
283            // EL0 controlled by PSTATE
284            CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
285
286            known = (cpsr.el == EL0);
287            aarch32 = (cpsr.width == 1);
288        } else {
289            known = true;
290            aarch32 = (aarch32_below_el3 && el != EL3)
291                      || (aarch32_at_el1 && (el == EL0 || el == EL1) );
292        }
293    }
294
295    return std::make_pair(known, aarch32);
296}
297
298bool
299isBigEndian64(ThreadContext *tc)
300{
301    switch (opModeToEL(currOpMode(tc))) {
302      case EL3:
303        return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).ee;
304      case EL2:
305        return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).ee;
306      case EL1:
307        return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).ee;
308      case EL0:
309        return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).e0e;
310      default:
311        panic("Invalid exception level");
312        break;
313    }
314}
315
316bool
317badMode32(ThreadContext *tc, OperatingMode mode)
318{
319    return unknownMode32(mode) || !ArmSystem::haveEL(tc, opModeToEL(mode));
320}
321
322bool
323badMode(ThreadContext *tc, OperatingMode mode)
324{
325    return unknownMode(mode) || !ArmSystem::haveEL(tc, opModeToEL(mode));
326}
327
328Addr
329purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
330                 TTBCR tcr)
331{
332    switch (el) {
333      case EL0:
334      case EL1:
335        if (bits(addr, 55, 48) == 0xFF && tcr.tbi1)
336            return addr | mask(63, 55);
337        else if (!bits(addr, 55, 48) && tcr.tbi0)
338            return bits(addr,55, 0);
339        break;
340      case EL2:
341        assert(ArmSystem::haveVirtualization(tc));
342        tcr = tc->readMiscReg(MISCREG_TCR_EL2);
343        if (tcr.tbi)
344            return addr & mask(56);
345        break;
346      case EL3:
347        assert(ArmSystem::haveSecurity(tc));
348        if (tcr.tbi)
349            return addr & mask(56);
350        break;
351      default:
352        panic("Invalid exception level");
353        break;
354    }
355
356    return addr;  // Nothing to do if this is not a tagged address
357}
358
359Addr
360purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el)
361{
362    TTBCR tcr;
363
364    switch (el) {
365      case EL0:
366      case EL1:
367        tcr = tc->readMiscReg(MISCREG_TCR_EL1);
368        if (bits(addr, 55, 48) == 0xFF && tcr.tbi1)
369            return addr | mask(63, 55);
370        else if (!bits(addr, 55, 48) && tcr.tbi0)
371            return bits(addr,55, 0);
372        break;
373      case EL2:
374        assert(ArmSystem::haveVirtualization(tc));
375        tcr = tc->readMiscReg(MISCREG_TCR_EL2);
376        if (tcr.tbi)
377            return addr & mask(56);
378        break;
379      case EL3:
380        assert(ArmSystem::haveSecurity(tc));
381        tcr = tc->readMiscReg(MISCREG_TCR_EL3);
382        if (tcr.tbi)
383            return addr & mask(56);
384        break;
385      default:
386        panic("Invalid exception level");
387        break;
388    }
389
390    return addr;  // Nothing to do if this is not a tagged address
391}
392
393Addr
394truncPage(Addr addr)
395{
396    return addr & ~(PageBytes - 1);
397}
398
399Addr
400roundPage(Addr addr)
401{
402    return (addr + PageBytes - 1) & ~(PageBytes - 1);
403}
404
405bool
406mcrMrc15TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
407                  HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
408{
409    bool        isRead;
410    uint32_t    crm;
411    IntRegIndex rt;
412    uint32_t    crn;
413    uint32_t    opc1;
414    uint32_t    opc2;
415    bool        trapToHype = false;
416
417
418    if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
419        mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
420        trapToHype  = ((uint32_t) hstr) & (1 << crn);
421        trapToHype |= hdcr.tpm  && (crn == 9) && (crm >= 12);
422        trapToHype |= hcr.tidcp && (
423            ((crn ==  9) && ((crm <= 2) || ((crm >= 5) && (crm <= 8)))) ||
424            ((crn == 10) && ((crm <= 1) ||  (crm == 4) || (crm == 8)))  ||
425            ((crn == 11) && ((crm <= 8) ||  (crm == 15)))               );
426
427        if (!trapToHype) {
428            switch (unflattenMiscReg(miscReg)) {
429              case MISCREG_CPACR:
430                trapToHype = hcptr.tcpac;
431                break;
432              case MISCREG_REVIDR:
433              case MISCREG_TCMTR:
434              case MISCREG_TLBTR:
435              case MISCREG_AIDR:
436                trapToHype = hcr.tid1;
437                break;
438              case MISCREG_CTR:
439              case MISCREG_CCSIDR:
440              case MISCREG_CLIDR:
441              case MISCREG_CSSELR:
442                trapToHype = hcr.tid2;
443                break;
444              case MISCREG_ID_PFR0:
445              case MISCREG_ID_PFR1:
446              case MISCREG_ID_DFR0:
447              case MISCREG_ID_AFR0:
448              case MISCREG_ID_MMFR0:
449              case MISCREG_ID_MMFR1:
450              case MISCREG_ID_MMFR2:
451              case MISCREG_ID_MMFR3:
452              case MISCREG_ID_ISAR0:
453              case MISCREG_ID_ISAR1:
454              case MISCREG_ID_ISAR2:
455              case MISCREG_ID_ISAR3:
456              case MISCREG_ID_ISAR4:
457              case MISCREG_ID_ISAR5:
458                trapToHype = hcr.tid3;
459                break;
460              case MISCREG_DCISW:
461              case MISCREG_DCCSW:
462              case MISCREG_DCCISW:
463                trapToHype = hcr.tsw;
464                break;
465              case MISCREG_DCIMVAC:
466              case MISCREG_DCCIMVAC:
467              case MISCREG_DCCMVAC:
468                trapToHype = hcr.tpc;
469                break;
470              case MISCREG_ICIMVAU:
471              case MISCREG_ICIALLU:
472              case MISCREG_ICIALLUIS:
473              case MISCREG_DCCMVAU:
474                trapToHype = hcr.tpu;
475                break;
476              case MISCREG_TLBIALLIS:
477              case MISCREG_TLBIMVAIS:
478              case MISCREG_TLBIASIDIS:
479              case MISCREG_TLBIMVAAIS:
480              case MISCREG_TLBIMVALIS:
481              case MISCREG_TLBIMVAALIS:
482              case MISCREG_DTLBIALL:
483              case MISCREG_ITLBIALL:
484              case MISCREG_DTLBIMVA:
485              case MISCREG_ITLBIMVA:
486              case MISCREG_DTLBIASID:
487              case MISCREG_ITLBIASID:
488              case MISCREG_TLBIMVAA:
489              case MISCREG_TLBIALL:
490              case MISCREG_TLBIMVA:
491              case MISCREG_TLBIMVAL:
492              case MISCREG_TLBIMVAAL:
493              case MISCREG_TLBIASID:
494                trapToHype = hcr.ttlb;
495                break;
496              case MISCREG_ACTLR:
497                trapToHype = hcr.tac;
498                break;
499              case MISCREG_SCTLR:
500              case MISCREG_TTBR0:
501              case MISCREG_TTBR1:
502              case MISCREG_TTBCR:
503              case MISCREG_DACR:
504              case MISCREG_DFSR:
505              case MISCREG_IFSR:
506              case MISCREG_DFAR:
507              case MISCREG_IFAR:
508              case MISCREG_ADFSR:
509              case MISCREG_AIFSR:
510              case MISCREG_PRRR:
511              case MISCREG_NMRR:
512              case MISCREG_MAIR0:
513              case MISCREG_MAIR1:
514              case MISCREG_CONTEXTIDR:
515                trapToHype = hcr.tvm & !isRead;
516                break;
517              case MISCREG_PMCR:
518                trapToHype = hdcr.tpmcr;
519                break;
520              // No default action needed
521              default:
522                break;
523            }
524        }
525    }
526    return trapToHype;
527}
528
529
530bool
531mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
532                  HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
533{
534    bool        isRead;
535    uint32_t    crm;
536    IntRegIndex rt;
537    uint32_t    crn;
538    uint32_t    opc1;
539    uint32_t    opc2;
540    bool        trapToHype = false;
541
542    if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
543        mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
544        inform("trap check M:%x N:%x 1:%x 2:%x hdcr %x, hcptr %x, hstr %x\n",
545                crm, crn, opc1, opc2, hdcr, hcptr, hstr);
546        trapToHype  = hdcr.tda  && (opc1 == 0);
547        trapToHype |= hcptr.tta && (opc1 == 1);
548        if (!trapToHype) {
549            switch (unflattenMiscReg(miscReg)) {
550              case MISCREG_DBGOSLSR:
551              case MISCREG_DBGOSLAR:
552              case MISCREG_DBGOSDLR:
553              case MISCREG_DBGPRCR:
554                trapToHype = hdcr.tdosa;
555                break;
556              case MISCREG_DBGDRAR:
557              case MISCREG_DBGDSAR:
558                trapToHype = hdcr.tdra;
559                break;
560              case MISCREG_JIDR:
561                trapToHype = hcr.tid0;
562                break;
563              case MISCREG_JOSCR:
564              case MISCREG_JMCR:
565                trapToHype = hstr.tjdbx;
566                break;
567              case MISCREG_TEECR:
568              case MISCREG_TEEHBR:
569                trapToHype = hstr.ttee;
570                break;
571              // No default action needed
572              default:
573                break;
574            }
575        }
576    }
577    return trapToHype;
578}
579
580bool
581mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr,
582                    HCR hcr, uint32_t iss)
583{
584    uint32_t    crm;
585    IntRegIndex rt;
586    uint32_t    crn;
587    uint32_t    opc1;
588    uint32_t    opc2;
589    bool        isRead;
590    bool        trapToHype = false;
591
592    if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
593        // This is technically the wrong function, but we can re-use it for
594        // the moment because we only need one field, which overlaps with the
595        // mcrmrc layout
596        mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
597        trapToHype = ((uint32_t) hstr) & (1 << crm);
598
599        if (!trapToHype) {
600            switch (unflattenMiscReg(miscReg)) {
601              case MISCREG_SCTLR:
602              case MISCREG_TTBR0:
603              case MISCREG_TTBR1:
604              case MISCREG_TTBCR:
605              case MISCREG_DACR:
606              case MISCREG_DFSR:
607              case MISCREG_IFSR:
608              case MISCREG_DFAR:
609              case MISCREG_IFAR:
610              case MISCREG_ADFSR:
611              case MISCREG_AIFSR:
612              case MISCREG_PRRR:
613              case MISCREG_NMRR:
614              case MISCREG_MAIR0:
615              case MISCREG_MAIR1:
616              case MISCREG_CONTEXTIDR:
617                trapToHype = hcr.tvm & !isRead;
618                break;
619              // No default action needed
620              default:
621                break;
622            }
623        }
624    }
625    return trapToHype;
626}
627
628bool
629decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx,
630                      CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
631{
632    OperatingMode mode = MODE_UNDEFINED;
633    bool          ok = true;
634
635    // R mostly indicates if its a int register or a misc reg, we override
636    // below if the few corner cases
637    isIntReg = !r;
638    // Loosely based on ARM ARM issue C section B9.3.10
639    if (r) {
640        switch (sysM)
641        {
642          case 0xE:
643            regIdx = MISCREG_SPSR_FIQ;
644            mode   = MODE_FIQ;
645            break;
646          case 0x10:
647            regIdx = MISCREG_SPSR_IRQ;
648            mode   = MODE_IRQ;
649            break;
650          case 0x12:
651            regIdx = MISCREG_SPSR_SVC;
652            mode   = MODE_SVC;
653            break;
654          case 0x14:
655            regIdx = MISCREG_SPSR_ABT;
656            mode   = MODE_ABORT;
657            break;
658          case 0x16:
659            regIdx = MISCREG_SPSR_UND;
660            mode   = MODE_UNDEFINED;
661            break;
662          case 0x1C:
663            regIdx = MISCREG_SPSR_MON;
664            mode   = MODE_MON;
665            break;
666          case 0x1E:
667            regIdx = MISCREG_SPSR_HYP;
668            mode   = MODE_HYP;
669            break;
670          default:
671            ok = false;
672            break;
673        }
674    } else {
675        int sysM4To3 = bits(sysM, 4, 3);
676
677        if (sysM4To3 == 0) {
678            mode = MODE_USER;
679            regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8);
680        } else if (sysM4To3 == 1) {
681            mode = MODE_FIQ;
682            regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8);
683        } else if (sysM4To3 == 3) {
684            if (bits(sysM, 1) == 0) {
685                mode = MODE_MON;
686                regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
687            } else {
688                mode = MODE_HYP;
689                if (bits(sysM, 0) == 1) {
690                    regIdx = intRegInMode(mode, 13); // R13 in HYP
691                } else {
692                    isIntReg = false;
693                    regIdx   = MISCREG_ELR_HYP;
694                }
695            }
696        } else { // Other Banked registers
697            int sysM2 = bits(sysM, 2);
698            int sysM1 = bits(sysM, 1);
699
700            mode  = (OperatingMode) ( ((sysM2 ||  sysM1) << 0) |
701                                      (1                 << 1) |
702                                      ((sysM2 && !sysM1) << 2) |
703                                      ((sysM2 &&  sysM1) << 3) |
704                                      (1                 << 4) );
705            regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
706            // Don't flatten the register here. This is going to go through
707            // setIntReg() which will do the flattening
708            ok &= mode != cpsr.mode;
709        }
710    }
711
712    // Check that the requested register is accessable from the current mode
713    if (ok && checkSecurity && mode != cpsr.mode) {
714        switch (cpsr.mode)
715        {
716          case MODE_USER:
717            ok = false;
718            break;
719          case MODE_FIQ:
720            ok &=  mode != MODE_HYP;
721            ok &= (mode != MODE_MON) || !scr.ns;
722            break;
723          case MODE_HYP:
724            ok &=  mode != MODE_MON;
725            ok &= (mode != MODE_FIQ) || !nsacr.rfr;
726            break;
727          case MODE_IRQ:
728          case MODE_SVC:
729          case MODE_ABORT:
730          case MODE_UNDEFINED:
731          case MODE_SYSTEM:
732            ok &=  mode != MODE_HYP;
733            ok &= (mode != MODE_MON) || !scr.ns;
734            ok &= (mode != MODE_FIQ) || !nsacr.rfr;
735            break;
736          // can access everything, no further checks required
737          case MODE_MON:
738            break;
739          default:
740            panic("unknown Mode 0x%x\n", cpsr.mode);
741            break;
742        }
743    }
744    return (ok);
745}
746
747bool
748SPAlignmentCheckEnabled(ThreadContext* tc)
749{
750    switch (opModeToEL(currOpMode(tc))) {
751      case EL3:
752        return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).sa;
753      case EL2:
754        return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).sa;
755      case EL1:
756        return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa;
757      case EL0:
758        return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa0;
759      default:
760        panic("Invalid exception level");
761        break;
762    }
763}
764
765int
766decodePhysAddrRange64(uint8_t pa_enc)
767{
768    switch (pa_enc) {
769      case 0x0:
770        return 32;
771      case 0x1:
772        return 36;
773      case 0x2:
774        return 40;
775      case 0x3:
776        return 42;
777      case 0x4:
778        return 44;
779      case 0x5:
780      case 0x6:
781      case 0x7:
782        return 48;
783      default:
784        panic("Invalid phys. address range encoding");
785    }
786}
787
788uint8_t
789encodePhysAddrRange64(int pa_size)
790{
791    switch (pa_size) {
792      case 32:
793        return 0x0;
794      case 36:
795        return 0x1;
796      case 40:
797        return 0x2;
798      case 42:
799        return 0x3;
800      case 44:
801        return 0x4;
802      case 48:
803        return 0x5;
804      default:
805        panic("Invalid phys. address range");
806    }
807}
808
809} // namespace ArmISA
810