utility.cc revision 12496:e7bc841e521c 
1/*
2 * Copyright (c) 2009-2014, 2016-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#include "arch/arm/utility.hh"
41
42#include <memory>
43
44#include "arch/arm/faults.hh"
45#include "arch/arm/isa_traits.hh"
46#include "arch/arm/system.hh"
47#include "arch/arm/tlb.hh"
48#include "arch/arm/vtophys.hh"
49#include "cpu/base.hh"
50#include "cpu/checker/cpu.hh"
51#include "cpu/thread_context.hh"
52#include "mem/fs_translating_port_proxy.hh"
53#include "sim/full_system.hh"
54
55namespace ArmISA {
56
57void
58initCPU(ThreadContext *tc, int cpuId)
59{
60    // Reset CP15?? What does that mean -- ali
61
62    // FPEXC.EN = 0
63
64    static Fault reset = std::make_shared<Reset>();
65    reset->invoke(tc);
66}
67
68uint64_t
69getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
70{
71    if (!FullSystem) {
72        panic("getArgument() only implemented for full system mode.\n");
73        M5_DUMMY_RETURN
74    }
75
76    if (fp)
77        panic("getArgument(): Floating point arguments not implemented\n");
78
79    if (inAArch64(tc)) {
80        if (size == (uint16_t)(-1))
81            size = sizeof(uint64_t);
82
83        if (number < 8 /*NumArgumentRegs64*/) {
84               return tc->readIntReg(number);
85        } else {
86            panic("getArgument(): No support reading stack args for AArch64\n");
87        }
88    } else {
89        if (size == (uint16_t)(-1))
90            // todo: should this not be sizeof(uint32_t) rather?
91            size = ArmISA::MachineBytes;
92
93        if (number < NumArgumentRegs) {
94            // If the argument is 64 bits, it must be in an even regiser
95            // number. Increment the number here if it isn't even.
96            if (size == sizeof(uint64_t)) {
97                if ((number % 2) != 0)
98                    number++;
99                // Read the two halves of the data. Number is inc here to
100                // get the second half of the 64 bit reg.
101                uint64_t tmp;
102                tmp = tc->readIntReg(number++);
103                tmp |= tc->readIntReg(number) << 32;
104                return tmp;
105            } else {
106               return tc->readIntReg(number);
107            }
108        } else {
109            Addr sp = tc->readIntReg(StackPointerReg);
110            FSTranslatingPortProxy &vp = tc->getVirtProxy();
111            uint64_t arg;
112            if (size == sizeof(uint64_t)) {
113                // If the argument is even it must be aligned
114                if ((number % 2) != 0)
115                    number++;
116                arg = vp.read<uint64_t>(sp +
117                        (number-NumArgumentRegs) * sizeof(uint32_t));
118                // since two 32 bit args == 1 64 bit arg, increment number
119                number++;
120            } else {
121                arg = vp.read<uint32_t>(sp +
122                               (number-NumArgumentRegs) * sizeof(uint32_t));
123            }
124            return arg;
125        }
126    }
127    panic("getArgument() should always return\n");
128}
129
130void
131skipFunction(ThreadContext *tc)
132{
133    PCState newPC = tc->pcState();
134    if (inAArch64(tc)) {
135        newPC.set(tc->readIntReg(INTREG_X30));
136    } else {
137        newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1));
138    }
139
140    CheckerCPU *checker = tc->getCheckerCpuPtr();
141    if (checker) {
142        tc->pcStateNoRecord(newPC);
143    } else {
144        tc->pcState(newPC);
145    }
146}
147
148void
149copyRegs(ThreadContext *src, ThreadContext *dest)
150{
151    for (int i = 0; i < NumIntRegs; i++)
152        dest->setIntRegFlat(i, src->readIntRegFlat(i));
153
154    for (int i = 0; i < NumFloatRegs; i++)
155        dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
156
157    for (int i = 0; i < NumVecRegs; i++)
158        dest->setVecRegFlat(i, src->readVecRegFlat(i));
159
160    for (int i = 0; i < NumCCRegs; i++)
161        dest->setCCReg(i, src->readCCReg(i));
162
163    for (int i = 0; i < NumMiscRegs; i++)
164        dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
165
166    // setMiscReg "with effect" will set the misc register mapping correctly.
167    // e.g. updateRegMap(val)
168    dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
169
170    // Copy over the PC State
171    dest->pcState(src->pcState());
172
173    // Invalidate the tlb misc register cache
174    dynamic_cast<TLB *>(dest->getITBPtr())->invalidateMiscReg();
175    dynamic_cast<TLB *>(dest->getDTBPtr())->invalidateMiscReg();
176}
177
178bool
179inSecureState(ThreadContext *tc)
180{
181    SCR scr = inAArch64(tc) ? tc->readMiscReg(MISCREG_SCR_EL3) :
182        tc->readMiscReg(MISCREG_SCR);
183    return ArmSystem::haveSecurity(tc) && inSecureState(
184        scr, tc->readMiscReg(MISCREG_CPSR));
185}
186
187inline bool
188isSecureBelowEL3(ThreadContext *tc)
189{
190    SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
191    return ArmSystem::haveEL(tc, EL3) && scr.ns == 0;
192}
193
194bool
195inAArch64(ThreadContext *tc)
196{
197    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
198    return opModeIs64((OperatingMode) (uint8_t) cpsr.mode);
199}
200
201bool
202longDescFormatInUse(ThreadContext *tc)
203{
204    TTBCR ttbcr = tc->readMiscReg(MISCREG_TTBCR);
205    return ArmSystem::haveLPAE(tc) && ttbcr.eae;
206}
207
208uint32_t
209getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
210{
211    // Multiprocessor Affinity Register MPIDR from Cortex(tm)-A15 Technical
212    // Reference Manual
213    //
214    // bit   31 - Multi-processor extensions available
215    // bit   30 - Uni-processor system
216    // bit   24 - Multi-threaded cores
217    // bit 11-8 - Cluster ID
218    // bit  1-0 - CPU ID
219    //
220    // We deliberately extend both the Cluster ID and CPU ID fields to allow
221    // for simulation of larger systems
222    assert((0 <= tc->cpuId()) && (tc->cpuId() < 256));
223    assert(tc->socketId() < 65536);
224    if (arm_sys->multiThread) {
225       return 0x80000000 | // multiprocessor extensions available
226              tc->contextId();
227    } else if (arm_sys->multiProc) {
228       return 0x80000000 | // multiprocessor extensions available
229              tc->cpuId() | tc->socketId() << 8;
230    } else {
231       return 0x80000000 |  // multiprocessor extensions available
232              0x40000000 |  // in up system
233              tc->cpuId() | tc->socketId() << 8;
234    }
235}
236
237bool
238ELIs64(ThreadContext *tc, ExceptionLevel el)
239{
240    return !ELIs32(tc, el);
241}
242
243bool
244ELIs32(ThreadContext *tc, ExceptionLevel el)
245{
246    bool known, aarch32;
247    std::tie(known, aarch32) = ELUsingAArch32K(tc, el);
248    panic_if(!known, "EL state is UNKNOWN");
249    return aarch32;
250}
251
252std::pair<bool, bool>
253ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el)
254{
255    // Return true if the specified EL is in aarch32 state.
256    const bool have_el3 = ArmSystem::haveSecurity(tc);
257    const bool have_el2 = ArmSystem::haveVirtualization(tc);
258
259    panic_if(el == EL2 && !have_el2, "Asking for EL2 when it doesn't exist");
260    panic_if(el == EL3 && !have_el3, "Asking for EL3 when it doesn't exist");
261
262    bool known, aarch32;
263    known = aarch32 = false;
264    if (ArmSystem::highestELIs64(tc) && ArmSystem::highestEL(tc) == el) {
265        // Target EL is the highest one in a system where
266        // the highest is using AArch64.
267        known = true; aarch32 = false;
268    } else if (!ArmSystem::highestELIs64(tc)) {
269        // All ELs are using AArch32:
270        known = true; aarch32 = true;
271    } else {
272        SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
273        bool aarch32_below_el3 = (have_el3 && scr.rw == 0);
274
275        HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
276        bool aarch32_at_el1 = (aarch32_below_el3
277                               || (have_el2
278                               && !isSecureBelowEL3(tc) && hcr.rw == 0));
279
280        // Only know if EL0 using AArch32 from PSTATE
281        if (el == EL0 && !aarch32_at_el1) {
282            // EL0 controlled by PSTATE
283            CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
284
285            known = (cpsr.el == EL0);
286            aarch32 = (cpsr.width == 1);
287        } else {
288            known = true;
289            aarch32 = (aarch32_below_el3 && el != EL3)
290                      || (aarch32_at_el1 && (el == EL0 || el == EL1) );
291        }
292    }
293
294    return std::make_pair(known, aarch32);
295}
296
297bool
298isBigEndian64(ThreadContext *tc)
299{
300    switch (opModeToEL(currOpMode(tc))) {
301      case EL3:
302        return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).ee;
303      case EL2:
304        return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).ee;
305      case EL1:
306        return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).ee;
307      case EL0:
308        return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).e0e;
309      default:
310        panic("Invalid exception level");
311        break;
312    }
313}
314
315Addr
316purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
317                 TTBCR tcr)
318{
319    switch (el) {
320      case EL0:
321      case EL1:
322        if (bits(addr, 55, 48) == 0xFF && tcr.tbi1)
323            return addr | mask(63, 55);
324        else if (!bits(addr, 55, 48) && tcr.tbi0)
325            return bits(addr,55, 0);
326        break;
327      case EL2:
328        assert(ArmSystem::haveVirtualization(tc));
329        tcr = tc->readMiscReg(MISCREG_TCR_EL2);
330        if (tcr.tbi)
331            return addr & mask(56);
332        break;
333      case EL3:
334        assert(ArmSystem::haveSecurity(tc));
335        if (tcr.tbi)
336            return addr & mask(56);
337        break;
338      default:
339        panic("Invalid exception level");
340        break;
341    }
342
343    return addr;  // Nothing to do if this is not a tagged address
344}
345
346Addr
347purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el)
348{
349    TTBCR tcr;
350
351    switch (el) {
352      case EL0:
353      case EL1:
354        tcr = tc->readMiscReg(MISCREG_TCR_EL1);
355        if (bits(addr, 55, 48) == 0xFF && tcr.tbi1)
356            return addr | mask(63, 55);
357        else if (!bits(addr, 55, 48) && tcr.tbi0)
358            return bits(addr,55, 0);
359        break;
360      case EL2:
361        assert(ArmSystem::haveVirtualization(tc));
362        tcr = tc->readMiscReg(MISCREG_TCR_EL2);
363        if (tcr.tbi)
364            return addr & mask(56);
365        break;
366      case EL3:
367        assert(ArmSystem::haveSecurity(tc));
368        tcr = tc->readMiscReg(MISCREG_TCR_EL3);
369        if (tcr.tbi)
370            return addr & mask(56);
371        break;
372      default:
373        panic("Invalid exception level");
374        break;
375    }
376
377    return addr;  // Nothing to do if this is not a tagged address
378}
379
380Addr
381truncPage(Addr addr)
382{
383    return addr & ~(PageBytes - 1);
384}
385
386Addr
387roundPage(Addr addr)
388{
389    return (addr + PageBytes - 1) & ~(PageBytes - 1);
390}
391
392bool
393mcrMrc15TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
394                  HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
395{
396    bool        isRead;
397    uint32_t    crm;
398    IntRegIndex rt;
399    uint32_t    crn;
400    uint32_t    opc1;
401    uint32_t    opc2;
402    bool        trapToHype = false;
403
404
405    if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
406        mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
407        trapToHype  = ((uint32_t) hstr) & (1 << crn);
408        trapToHype |= hdcr.tpm  && (crn == 9) && (crm >= 12);
409        trapToHype |= hcr.tidcp && (
410            ((crn ==  9) && ((crm <= 2) || ((crm >= 5) && (crm <= 8)))) ||
411            ((crn == 10) && ((crm <= 1) ||  (crm == 4) || (crm == 8)))  ||
412            ((crn == 11) && ((crm <= 8) ||  (crm == 15)))               );
413
414        if (!trapToHype) {
415            switch (unflattenMiscReg(miscReg)) {
416              case MISCREG_CPACR:
417                trapToHype = hcptr.tcpac;
418                break;
419              case MISCREG_REVIDR:
420              case MISCREG_TCMTR:
421              case MISCREG_TLBTR:
422              case MISCREG_AIDR:
423                trapToHype = hcr.tid1;
424                break;
425              case MISCREG_CTR:
426              case MISCREG_CCSIDR:
427              case MISCREG_CLIDR:
428              case MISCREG_CSSELR:
429                trapToHype = hcr.tid2;
430                break;
431              case MISCREG_ID_PFR0:
432              case MISCREG_ID_PFR1:
433              case MISCREG_ID_DFR0:
434              case MISCREG_ID_AFR0:
435              case MISCREG_ID_MMFR0:
436              case MISCREG_ID_MMFR1:
437              case MISCREG_ID_MMFR2:
438              case MISCREG_ID_MMFR3:
439              case MISCREG_ID_ISAR0:
440              case MISCREG_ID_ISAR1:
441              case MISCREG_ID_ISAR2:
442              case MISCREG_ID_ISAR3:
443              case MISCREG_ID_ISAR4:
444              case MISCREG_ID_ISAR5:
445                trapToHype = hcr.tid3;
446                break;
447              case MISCREG_DCISW:
448              case MISCREG_DCCSW:
449              case MISCREG_DCCISW:
450                trapToHype = hcr.tsw;
451                break;
452              case MISCREG_DCIMVAC:
453              case MISCREG_DCCIMVAC:
454              case MISCREG_DCCMVAC:
455                trapToHype = hcr.tpc;
456                break;
457              case MISCREG_ICIMVAU:
458              case MISCREG_ICIALLU:
459              case MISCREG_ICIALLUIS:
460              case MISCREG_DCCMVAU:
461                trapToHype = hcr.tpu;
462                break;
463              case MISCREG_TLBIALLIS:
464              case MISCREG_TLBIMVAIS:
465              case MISCREG_TLBIASIDIS:
466              case MISCREG_TLBIMVAAIS:
467              case MISCREG_DTLBIALL:
468              case MISCREG_ITLBIALL:
469              case MISCREG_DTLBIMVA:
470              case MISCREG_ITLBIMVA:
471              case MISCREG_DTLBIASID:
472              case MISCREG_ITLBIASID:
473              case MISCREG_TLBIMVAA:
474              case MISCREG_TLBIALL:
475              case MISCREG_TLBIMVA:
476              case MISCREG_TLBIASID:
477                trapToHype = hcr.ttlb;
478                break;
479              case MISCREG_ACTLR:
480                trapToHype = hcr.tac;
481                break;
482              case MISCREG_SCTLR:
483              case MISCREG_TTBR0:
484              case MISCREG_TTBR1:
485              case MISCREG_TTBCR:
486              case MISCREG_DACR:
487              case MISCREG_DFSR:
488              case MISCREG_IFSR:
489              case MISCREG_DFAR:
490              case MISCREG_IFAR:
491              case MISCREG_ADFSR:
492              case MISCREG_AIFSR:
493              case MISCREG_PRRR:
494              case MISCREG_NMRR:
495              case MISCREG_MAIR0:
496              case MISCREG_MAIR1:
497              case MISCREG_CONTEXTIDR:
498                trapToHype = hcr.tvm & !isRead;
499                break;
500              case MISCREG_PMCR:
501                trapToHype = hdcr.tpmcr;
502                break;
503              // No default action needed
504              default:
505                break;
506            }
507        }
508    }
509    return trapToHype;
510}
511
512
513bool
514mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
515                  HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
516{
517    bool        isRead;
518    uint32_t    crm;
519    IntRegIndex rt;
520    uint32_t    crn;
521    uint32_t    opc1;
522    uint32_t    opc2;
523    bool        trapToHype = false;
524
525    if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
526        mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
527        inform("trap check M:%x N:%x 1:%x 2:%x hdcr %x, hcptr %x, hstr %x\n",
528                crm, crn, opc1, opc2, hdcr, hcptr, hstr);
529        trapToHype  = hdcr.tda  && (opc1 == 0);
530        trapToHype |= hcptr.tta && (opc1 == 1);
531        if (!trapToHype) {
532            switch (unflattenMiscReg(miscReg)) {
533              case MISCREG_DBGOSLSR:
534              case MISCREG_DBGOSLAR:
535              case MISCREG_DBGOSDLR:
536              case MISCREG_DBGPRCR:
537                trapToHype = hdcr.tdosa;
538                break;
539              case MISCREG_DBGDRAR:
540              case MISCREG_DBGDSAR:
541                trapToHype = hdcr.tdra;
542                break;
543              case MISCREG_JIDR:
544                trapToHype = hcr.tid0;
545                break;
546              case MISCREG_JOSCR:
547              case MISCREG_JMCR:
548                trapToHype = hstr.tjdbx;
549                break;
550              case MISCREG_TEECR:
551              case MISCREG_TEEHBR:
552                trapToHype = hstr.ttee;
553                break;
554              // No default action needed
555              default:
556                break;
557            }
558        }
559    }
560    return trapToHype;
561}
562
563bool
564mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr,
565                    HCR hcr, uint32_t iss)
566{
567    uint32_t    crm;
568    IntRegIndex rt;
569    uint32_t    crn;
570    uint32_t    opc1;
571    uint32_t    opc2;
572    bool        isRead;
573    bool        trapToHype = false;
574
575    if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
576        // This is technically the wrong function, but we can re-use it for
577        // the moment because we only need one field, which overlaps with the
578        // mcrmrc layout
579        mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
580        trapToHype = ((uint32_t) hstr) & (1 << crm);
581
582        if (!trapToHype) {
583            switch (unflattenMiscReg(miscReg)) {
584              case MISCREG_SCTLR:
585              case MISCREG_TTBR0:
586              case MISCREG_TTBR1:
587              case MISCREG_TTBCR:
588              case MISCREG_DACR:
589              case MISCREG_DFSR:
590              case MISCREG_IFSR:
591              case MISCREG_DFAR:
592              case MISCREG_IFAR:
593              case MISCREG_ADFSR:
594              case MISCREG_AIFSR:
595              case MISCREG_PRRR:
596              case MISCREG_NMRR:
597              case MISCREG_MAIR0:
598              case MISCREG_MAIR1:
599              case MISCREG_CONTEXTIDR:
600                trapToHype = hcr.tvm & !isRead;
601                break;
602              // No default action needed
603              default:
604                break;
605            }
606        }
607    }
608    return trapToHype;
609}
610
611bool
612msrMrs64TrapToSup(const MiscRegIndex miscReg, ExceptionLevel el,
613                  CPACR cpacr /* CPACR_EL1 */)
614{
615    bool trapToSup = false;
616    switch (miscReg) {
617      case MISCREG_FPCR:
618      case MISCREG_FPSR:
619      case MISCREG_FPEXC32_EL2:
620        if ((el == EL0 && cpacr.fpen != 0x3) ||
621            (el == EL1 && !(cpacr.fpen & 0x1)))
622            trapToSup = true;
623        break;
624      default:
625        break;
626    }
627    return trapToSup;
628}
629
630bool
631msrMrs64TrapToHyp(const MiscRegIndex miscReg,
632                  ExceptionLevel el,
633                  bool isRead,
634                  CPTR cptr /* CPTR_EL2 */,
635                  HCR hcr /* HCR_EL2 */,
636                  bool * isVfpNeon)
637{
638    bool trapToHyp = false;
639    *isVfpNeon = false;
640
641    switch (miscReg) {
642      // FP/SIMD regs
643      case MISCREG_FPCR:
644      case MISCREG_FPSR:
645      case MISCREG_FPEXC32_EL2:
646        trapToHyp = cptr.tfp;
647        *isVfpNeon = true;
648        break;
649      // CPACR
650      case MISCREG_CPACR_EL1:
651        trapToHyp = cptr.tcpac && el == EL1;
652        break;
653      // Virtual memory control regs
654      case MISCREG_SCTLR_EL1:
655      case MISCREG_TTBR0_EL1:
656      case MISCREG_TTBR1_EL1:
657      case MISCREG_TCR_EL1:
658      case MISCREG_ESR_EL1:
659      case MISCREG_FAR_EL1:
660      case MISCREG_AFSR0_EL1:
661      case MISCREG_AFSR1_EL1:
662      case MISCREG_MAIR_EL1:
663      case MISCREG_AMAIR_EL1:
664      case MISCREG_CONTEXTIDR_EL1:
665        trapToHyp = ((hcr.trvm && isRead) || (hcr.tvm && !isRead))
666                    && el == EL1;
667        break;
668      // TLB maintenance instructions
669      case MISCREG_TLBI_VMALLE1:
670      case MISCREG_TLBI_VAE1_Xt:
671      case MISCREG_TLBI_ASIDE1_Xt:
672      case MISCREG_TLBI_VAAE1_Xt:
673      case MISCREG_TLBI_VALE1_Xt:
674      case MISCREG_TLBI_VAALE1_Xt:
675      case MISCREG_TLBI_VMALLE1IS:
676      case MISCREG_TLBI_VAE1IS_Xt:
677      case MISCREG_TLBI_ASIDE1IS_Xt:
678      case MISCREG_TLBI_VAAE1IS_Xt:
679      case MISCREG_TLBI_VALE1IS_Xt:
680      case MISCREG_TLBI_VAALE1IS_Xt:
681        trapToHyp = hcr.ttlb && el == EL1;
682        break;
683      // Cache maintenance instructions to the point of unification
684      case MISCREG_IC_IVAU_Xt:
685      case MISCREG_ICIALLU:
686      case MISCREG_ICIALLUIS:
687      case MISCREG_DC_CVAU_Xt:
688        trapToHyp = hcr.tpu && el <= EL1;
689        break;
690      // Data/Unified cache maintenance instructions to the point of coherency
691      case MISCREG_DC_IVAC_Xt:
692      case MISCREG_DC_CIVAC_Xt:
693      case MISCREG_DC_CVAC_Xt:
694        trapToHyp = hcr.tpc && el <= EL1;
695        break;
696      // Data/Unified cache maintenance instructions by set/way
697      case MISCREG_DC_ISW_Xt:
698      case MISCREG_DC_CSW_Xt:
699      case MISCREG_DC_CISW_Xt:
700        trapToHyp = hcr.tsw && el == EL1;
701        break;
702      // ACTLR
703      case MISCREG_ACTLR_EL1:
704        trapToHyp = hcr.tacr && el == EL1;
705        break;
706
707      // @todo: Trap implementation-dependent functionality based on
708      // hcr.tidcp
709
710      // ID regs, group 3
711      case MISCREG_ID_PFR0_EL1:
712      case MISCREG_ID_PFR1_EL1:
713      case MISCREG_ID_DFR0_EL1:
714      case MISCREG_ID_AFR0_EL1:
715      case MISCREG_ID_MMFR0_EL1:
716      case MISCREG_ID_MMFR1_EL1:
717      case MISCREG_ID_MMFR2_EL1:
718      case MISCREG_ID_MMFR3_EL1:
719      case MISCREG_ID_ISAR0_EL1:
720      case MISCREG_ID_ISAR1_EL1:
721      case MISCREG_ID_ISAR2_EL1:
722      case MISCREG_ID_ISAR3_EL1:
723      case MISCREG_ID_ISAR4_EL1:
724      case MISCREG_ID_ISAR5_EL1:
725      case MISCREG_MVFR0_EL1:
726      case MISCREG_MVFR1_EL1:
727      case MISCREG_MVFR2_EL1:
728      case MISCREG_ID_AA64PFR0_EL1:
729      case MISCREG_ID_AA64PFR1_EL1:
730      case MISCREG_ID_AA64DFR0_EL1:
731      case MISCREG_ID_AA64DFR1_EL1:
732      case MISCREG_ID_AA64ISAR0_EL1:
733      case MISCREG_ID_AA64ISAR1_EL1:
734      case MISCREG_ID_AA64MMFR0_EL1:
735      case MISCREG_ID_AA64MMFR1_EL1:
736      case MISCREG_ID_AA64AFR0_EL1:
737      case MISCREG_ID_AA64AFR1_EL1:
738        assert(isRead);
739        trapToHyp = hcr.tid3 && el == EL1;
740        break;
741      // ID regs, group 2
742      case MISCREG_CTR_EL0:
743      case MISCREG_CCSIDR_EL1:
744      case MISCREG_CLIDR_EL1:
745      case MISCREG_CSSELR_EL1:
746        trapToHyp = hcr.tid2 && el <= EL1;
747        break;
748      // ID regs, group 1
749      case MISCREG_AIDR_EL1:
750      case MISCREG_REVIDR_EL1:
751        assert(isRead);
752        trapToHyp = hcr.tid1 && el == EL1;
753        break;
754      default:
755        break;
756    }
757    return trapToHyp;
758}
759
760bool
761msrMrs64TrapToMon(const MiscRegIndex miscReg, CPTR cptr /* CPTR_EL3 */,
762                  ExceptionLevel el, bool * isVfpNeon)
763{
764    bool trapToMon = false;
765    *isVfpNeon = false;
766
767    switch (miscReg) {
768      // FP/SIMD regs
769      case MISCREG_FPCR:
770      case MISCREG_FPSR:
771      case MISCREG_FPEXC32_EL2:
772        trapToMon = cptr.tfp;
773        *isVfpNeon = true;
774        break;
775      // CPACR, CPTR
776      case MISCREG_CPACR_EL1:
777        if (el == EL1) {
778           trapToMon = cptr.tcpac;
779        }
780        break;
781      case MISCREG_CPTR_EL2:
782        if (el == EL2) {
783            trapToMon = cptr.tcpac;
784        }
785        break;
786      default:
787        break;
788    }
789    return trapToMon;
790}
791
792bool
793decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx,
794                      CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
795{
796    OperatingMode mode = MODE_UNDEFINED;
797    bool          ok = true;
798
799    // R mostly indicates if its a int register or a misc reg, we override
800    // below if the few corner cases
801    isIntReg = !r;
802    // Loosely based on ARM ARM issue C section B9.3.10
803    if (r) {
804        switch (sysM)
805        {
806          case 0xE:
807            regIdx = MISCREG_SPSR_FIQ;
808            mode   = MODE_FIQ;
809            break;
810          case 0x10:
811            regIdx = MISCREG_SPSR_IRQ;
812            mode   = MODE_IRQ;
813            break;
814          case 0x12:
815            regIdx = MISCREG_SPSR_SVC;
816            mode   = MODE_SVC;
817            break;
818          case 0x14:
819            regIdx = MISCREG_SPSR_ABT;
820            mode   = MODE_ABORT;
821            break;
822          case 0x16:
823            regIdx = MISCREG_SPSR_UND;
824            mode   = MODE_UNDEFINED;
825            break;
826          case 0x1C:
827            regIdx = MISCREG_SPSR_MON;
828            mode   = MODE_MON;
829            break;
830          case 0x1E:
831            regIdx = MISCREG_SPSR_HYP;
832            mode   = MODE_HYP;
833            break;
834          default:
835            ok = false;
836            break;
837        }
838    } else {
839        int sysM4To3 = bits(sysM, 4, 3);
840
841        if (sysM4To3 == 0) {
842            mode = MODE_USER;
843            regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8);
844        } else if (sysM4To3 == 1) {
845            mode = MODE_FIQ;
846            regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8);
847        } else if (sysM4To3 == 3) {
848            if (bits(sysM, 1) == 0) {
849                mode = MODE_MON;
850                regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
851            } else {
852                mode = MODE_HYP;
853                if (bits(sysM, 0) == 1) {
854                    regIdx = intRegInMode(mode, 13); // R13 in HYP
855                } else {
856                    isIntReg = false;
857                    regIdx   = MISCREG_ELR_HYP;
858                }
859            }
860        } else { // Other Banked registers
861            int sysM2 = bits(sysM, 2);
862            int sysM1 = bits(sysM, 1);
863
864            mode  = (OperatingMode) ( ((sysM2 ||  sysM1) << 0) |
865                                      (1                 << 1) |
866                                      ((sysM2 && !sysM1) << 2) |
867                                      ((sysM2 &&  sysM1) << 3) |
868                                      (1                 << 4) );
869            regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
870            // Don't flatten the register here. This is going to go through
871            // setIntReg() which will do the flattening
872            ok &= mode != cpsr.mode;
873        }
874    }
875
876    // Check that the requested register is accessable from the current mode
877    if (ok && checkSecurity && mode != cpsr.mode) {
878        switch (cpsr.mode)
879        {
880          case MODE_USER:
881            ok = false;
882            break;
883          case MODE_FIQ:
884            ok &=  mode != MODE_HYP;
885            ok &= (mode != MODE_MON) || !scr.ns;
886            break;
887          case MODE_HYP:
888            ok &=  mode != MODE_MON;
889            ok &= (mode != MODE_FIQ) || !nsacr.rfr;
890            break;
891          case MODE_IRQ:
892          case MODE_SVC:
893          case MODE_ABORT:
894          case MODE_UNDEFINED:
895          case MODE_SYSTEM:
896            ok &=  mode != MODE_HYP;
897            ok &= (mode != MODE_MON) || !scr.ns;
898            ok &= (mode != MODE_FIQ) || !nsacr.rfr;
899            break;
900          // can access everything, no further checks required
901          case MODE_MON:
902            break;
903          default:
904            panic("unknown Mode 0x%x\n", cpsr.mode);
905            break;
906        }
907    }
908    return (ok);
909}
910
911bool
912SPAlignmentCheckEnabled(ThreadContext* tc)
913{
914    switch (opModeToEL(currOpMode(tc))) {
915      case EL3:
916        return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).sa;
917      case EL2:
918        return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).sa;
919      case EL1:
920        return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa;
921      case EL0:
922        return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa0;
923      default:
924        panic("Invalid exception level");
925        break;
926    }
927}
928
929int
930decodePhysAddrRange64(uint8_t pa_enc)
931{
932    switch (pa_enc) {
933      case 0x0:
934        return 32;
935      case 0x1:
936        return 36;
937      case 0x2:
938        return 40;
939      case 0x3:
940        return 42;
941      case 0x4:
942        return 44;
943      case 0x5:
944      case 0x6:
945      case 0x7:
946        return 48;
947      default:
948        panic("Invalid phys. address range encoding");
949    }
950}
951
952uint8_t
953encodePhysAddrRange64(int pa_size)
954{
955    switch (pa_size) {
956      case 32:
957        return 0x0;
958      case 36:
959        return 0x1;
960      case 40:
961        return 0x2;
962      case 42:
963        return 0x3;
964      case 44:
965        return 0x4;
966      case 48:
967        return 0x5;
968      default:
969        panic("Invalid phys. address range");
970    }
971}
972
973} // namespace ArmISA
974