utility.cc revision 8806
16757SAli.Saidi@ARM.com/* 27650SAli.Saidi@ARM.com * Copyright (c) 2009-2010 ARM Limited 36757SAli.Saidi@ARM.com * All rights reserved. 46757SAli.Saidi@ARM.com * 57111Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67111Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77111Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87111Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97111Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107111Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117111Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127111Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137111Sgblack@eecs.umich.edu * 146757SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 156757SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 166757SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 176757SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 186757SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 196757SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 206757SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 216757SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 226757SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 236757SAli.Saidi@ARM.com * this software without specific prior written permission. 246757SAli.Saidi@ARM.com * 256757SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 266757SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 276757SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 286757SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 296757SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 306757SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 316757SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 326757SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 336757SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 346757SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 356757SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 366757SAli.Saidi@ARM.com * 376757SAli.Saidi@ARM.com * Authors: Ali Saidi 386757SAli.Saidi@ARM.com */ 396735Sgblack@eecs.umich.edu 406757SAli.Saidi@ARM.com 416757SAli.Saidi@ARM.com#include "arch/arm/faults.hh" 427707Sgblack@eecs.umich.edu#include "arch/arm/isa_traits.hh" 438782Sgblack@eecs.umich.edu#include "arch/arm/tlb.hh" 446757SAli.Saidi@ARM.com#include "arch/arm/utility.hh" 458782Sgblack@eecs.umich.edu#include "arch/arm/vtophys.hh" 466757SAli.Saidi@ARM.com#include "cpu/thread_context.hh" 478706Sandreas.hansson@arm.com#include "mem/fs_translating_port_proxy.hh" 488782Sgblack@eecs.umich.edu#include "sim/full_system.hh" 497749SAli.Saidi@ARM.com 506735Sgblack@eecs.umich.edunamespace ArmISA { 516735Sgblack@eecs.umich.edu 526735Sgblack@eecs.umich.eduvoid 536735Sgblack@eecs.umich.eduinitCPU(ThreadContext *tc, int cpuId) 546735Sgblack@eecs.umich.edu{ 556735Sgblack@eecs.umich.edu // Reset CP15?? What does that mean -- ali 566735Sgblack@eecs.umich.edu 576735Sgblack@eecs.umich.edu // FPEXC.EN = 0 586735Sgblack@eecs.umich.edu 596757SAli.Saidi@ARM.com static Fault reset = new Reset; 608286SAli.Saidi@ARM.com reset->invoke(tc); 616735Sgblack@eecs.umich.edu} 626735Sgblack@eecs.umich.edu 637707Sgblack@eecs.umich.eduuint64_t 647707Sgblack@eecs.umich.edugetArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) 657707Sgblack@eecs.umich.edu{ 668806Sgblack@eecs.umich.edu if (!FullSystem) { 678806Sgblack@eecs.umich.edu panic("getArgument() only implemented for full system mode.\n"); 688806Sgblack@eecs.umich.edu M5_DUMMY_RETURN 698806Sgblack@eecs.umich.edu } 707693SAli.Saidi@ARM.com 718806Sgblack@eecs.umich.edu if (size == (uint16_t)(-1)) 728806Sgblack@eecs.umich.edu size = ArmISA::MachineBytes; 738806Sgblack@eecs.umich.edu if (fp) 748806Sgblack@eecs.umich.edu panic("getArgument(): Floating point arguments not implemented\n"); 758806Sgblack@eecs.umich.edu 768806Sgblack@eecs.umich.edu if (number < NumArgumentRegs) { 778806Sgblack@eecs.umich.edu // If the argument is 64 bits, it must be in an even regiser 788806Sgblack@eecs.umich.edu // number. Increment the number here if it isn't even. 798806Sgblack@eecs.umich.edu if (size == sizeof(uint64_t)) { 808806Sgblack@eecs.umich.edu if ((number % 2) != 0) 818806Sgblack@eecs.umich.edu number++; 828806Sgblack@eecs.umich.edu // Read the two halves of the data. Number is inc here to 838806Sgblack@eecs.umich.edu // get the second half of the 64 bit reg. 848806Sgblack@eecs.umich.edu uint64_t tmp; 858806Sgblack@eecs.umich.edu tmp = tc->readIntReg(number++); 868806Sgblack@eecs.umich.edu tmp |= tc->readIntReg(number) << 32; 878806Sgblack@eecs.umich.edu return tmp; 888782Sgblack@eecs.umich.edu } else { 898806Sgblack@eecs.umich.edu return tc->readIntReg(number); 907693SAli.Saidi@ARM.com } 917693SAli.Saidi@ARM.com } else { 928806Sgblack@eecs.umich.edu Addr sp = tc->readIntReg(StackPointerReg); 938806Sgblack@eecs.umich.edu FSTranslatingPortProxy* vp = tc->getVirtProxy(); 948806Sgblack@eecs.umich.edu uint64_t arg; 958806Sgblack@eecs.umich.edu if (size == sizeof(uint64_t)) { 968806Sgblack@eecs.umich.edu // If the argument is even it must be aligned 978806Sgblack@eecs.umich.edu if ((number % 2) != 0) 988806Sgblack@eecs.umich.edu number++; 998806Sgblack@eecs.umich.edu arg = vp->read<uint64_t>(sp + 1008806Sgblack@eecs.umich.edu (number-NumArgumentRegs) * sizeof(uint32_t)); 1018806Sgblack@eecs.umich.edu // since two 32 bit args == 1 64 bit arg, increment number 1028806Sgblack@eecs.umich.edu number++; 1038806Sgblack@eecs.umich.edu } else { 1048806Sgblack@eecs.umich.edu arg = vp->read<uint32_t>(sp + 1058806Sgblack@eecs.umich.edu (number-NumArgumentRegs) * sizeof(uint32_t)); 1068806Sgblack@eecs.umich.edu } 1078806Sgblack@eecs.umich.edu return arg; 1087650SAli.Saidi@ARM.com } 1096757SAli.Saidi@ARM.com} 1106757SAli.Saidi@ARM.com 1117693SAli.Saidi@ARM.comvoid 1127693SAli.Saidi@ARM.comskipFunction(ThreadContext *tc) 1137693SAli.Saidi@ARM.com{ 1147720Sgblack@eecs.umich.edu TheISA::PCState newPC = tc->pcState(); 1157720Sgblack@eecs.umich.edu newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1)); 1167720Sgblack@eecs.umich.edu tc->pcState(newPC); 1177693SAli.Saidi@ARM.com} 1187693SAli.Saidi@ARM.com 1197748SAli.Saidi@ARM.comvoid 1207748SAli.Saidi@ARM.comcopyRegs(ThreadContext *src, ThreadContext *dest) 1217748SAli.Saidi@ARM.com{ 1227748SAli.Saidi@ARM.com int i; 1238208SAli.Saidi@ARM.com 1248208SAli.Saidi@ARM.com int saved_mode = ((CPSR)src->readMiscReg(MISCREG_CPSR)).mode; 1258208SAli.Saidi@ARM.com 1268208SAli.Saidi@ARM.com // Make sure we're in user mode, so we can easily see all the registers 1278208SAli.Saidi@ARM.com // in the copy loop 1288208SAli.Saidi@ARM.com src->setMiscReg(MISCREG_CPSR_MODE, MODE_USER); 1298208SAli.Saidi@ARM.com dest->setMiscReg(MISCREG_CPSR_MODE, MODE_USER); 1308208SAli.Saidi@ARM.com 1317748SAli.Saidi@ARM.com for(i = 0; i < TheISA::NumIntRegs; i++) 1327748SAli.Saidi@ARM.com dest->setIntReg(i, src->readIntReg(i)); 1338208SAli.Saidi@ARM.com 1348208SAli.Saidi@ARM.com // Restore us back to the old mode 1358208SAli.Saidi@ARM.com src->setMiscReg(MISCREG_CPSR_MODE, saved_mode); 1368208SAli.Saidi@ARM.com dest->setMiscReg(MISCREG_CPSR_MODE, saved_mode); 1378208SAli.Saidi@ARM.com 1387748SAli.Saidi@ARM.com for(i = 0; i < TheISA::NumFloatRegs; i++) 1397748SAli.Saidi@ARM.com dest->setFloatReg(i, src->readFloatReg(i)); 1407748SAli.Saidi@ARM.com for(i = 0; i < TheISA::NumMiscRegs; i++) 1417748SAli.Saidi@ARM.com dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); 1426759SAli.Saidi@ARM.com 1437748SAli.Saidi@ARM.com // setMiscReg "with effect" will set the misc register mapping correctly. 1447748SAli.Saidi@ARM.com // e.g. updateRegMap(val) 1457748SAli.Saidi@ARM.com dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR)); 1467748SAli.Saidi@ARM.com 1477749SAli.Saidi@ARM.com // Copy over the PC State 1487748SAli.Saidi@ARM.com dest->pcState(src->pcState()); 1497749SAli.Saidi@ARM.com 1507749SAli.Saidi@ARM.com // Invalidate the tlb misc register cache 1517749SAli.Saidi@ARM.com dest->getITBPtr()->invalidateMiscReg(); 1527749SAli.Saidi@ARM.com dest->getDTBPtr()->invalidateMiscReg(); 1536759SAli.Saidi@ARM.com} 1547752SWilliam.Wang@arm.com 1557752SWilliam.Wang@arm.comAddr 1567752SWilliam.Wang@arm.comtruncPage(Addr addr) 1577752SWilliam.Wang@arm.com{ 1587752SWilliam.Wang@arm.com return addr & ~(PageBytes - 1); 1597748SAli.Saidi@ARM.com} 1607752SWilliam.Wang@arm.com 1617752SWilliam.Wang@arm.comAddr 1627752SWilliam.Wang@arm.comroundPage(Addr addr) 1637752SWilliam.Wang@arm.com{ 1647752SWilliam.Wang@arm.com return (addr + PageBytes - 1) & ~(PageBytes - 1); 1657752SWilliam.Wang@arm.com} 1667752SWilliam.Wang@arm.com 1677752SWilliam.Wang@arm.com} // namespace ArmISA 168