utility.cc revision 12406
16757SAli.Saidi@ARM.com/* 211574SCurtis.Dunham@arm.com * Copyright (c) 2009-2014, 2016 ARM Limited 36757SAli.Saidi@ARM.com * All rights reserved. 46757SAli.Saidi@ARM.com * 57111Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67111Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77111Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87111Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97111Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107111Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117111Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127111Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137111Sgblack@eecs.umich.edu * 146757SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 156757SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 166757SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 176757SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 186757SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 196757SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 206757SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 216757SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 226757SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 236757SAli.Saidi@ARM.com * this software without specific prior written permission. 246757SAli.Saidi@ARM.com * 256757SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 266757SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 276757SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 286757SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 296757SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 306757SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 316757SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 326757SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 336757SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 346757SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 356757SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 366757SAli.Saidi@ARM.com * 376757SAli.Saidi@ARM.com * Authors: Ali Saidi 386757SAli.Saidi@ARM.com */ 396735Sgblack@eecs.umich.edu 4011793Sbrandon.potter@amd.com#include "arch/arm/utility.hh" 4111793Sbrandon.potter@amd.com 4210474Sandreas.hansson@arm.com#include <memory> 436757SAli.Saidi@ARM.com 446757SAli.Saidi@ARM.com#include "arch/arm/faults.hh" 457707Sgblack@eecs.umich.edu#include "arch/arm/isa_traits.hh" 4610037SARM gem5 Developers#include "arch/arm/system.hh" 478782Sgblack@eecs.umich.edu#include "arch/arm/tlb.hh" 488782Sgblack@eecs.umich.edu#include "arch/arm/vtophys.hh" 4911793Sbrandon.potter@amd.com#include "cpu/base.hh" 508887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 516757SAli.Saidi@ARM.com#include "cpu/thread_context.hh" 528706Sandreas.hansson@arm.com#include "mem/fs_translating_port_proxy.hh" 538782Sgblack@eecs.umich.edu#include "sim/full_system.hh" 547749SAli.Saidi@ARM.com 556735Sgblack@eecs.umich.edunamespace ArmISA { 566735Sgblack@eecs.umich.edu 576735Sgblack@eecs.umich.eduvoid 586735Sgblack@eecs.umich.eduinitCPU(ThreadContext *tc, int cpuId) 596735Sgblack@eecs.umich.edu{ 606735Sgblack@eecs.umich.edu // Reset CP15?? What does that mean -- ali 619058Satgutier@umich.edu 626735Sgblack@eecs.umich.edu // FPEXC.EN = 0 638886SAli.Saidi@ARM.com 6410474Sandreas.hansson@arm.com static Fault reset = std::make_shared<Reset>(); 658286SAli.Saidi@ARM.com reset->invoke(tc); 666735Sgblack@eecs.umich.edu} 676735Sgblack@eecs.umich.edu 687707Sgblack@eecs.umich.eduuint64_t 697707Sgblack@eecs.umich.edugetArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) 707707Sgblack@eecs.umich.edu{ 718806Sgblack@eecs.umich.edu if (!FullSystem) { 728806Sgblack@eecs.umich.edu panic("getArgument() only implemented for full system mode.\n"); 738806Sgblack@eecs.umich.edu M5_DUMMY_RETURN 748806Sgblack@eecs.umich.edu } 758706Sandreas.hansson@arm.com 767693SAli.Saidi@ARM.com if (fp) 777693SAli.Saidi@ARM.com panic("getArgument(): Floating point arguments not implemented\n"); 787693SAli.Saidi@ARM.com 7910037SARM gem5 Developers if (inAArch64(tc)) { 8010037SARM gem5 Developers if (size == (uint16_t)(-1)) 8110037SARM gem5 Developers size = sizeof(uint64_t); 8210037SARM gem5 Developers 8310037SARM gem5 Developers if (number < 8 /*NumArgumentRegs64*/) { 8410037SARM gem5 Developers return tc->readIntReg(number); 857693SAli.Saidi@ARM.com } else { 8610037SARM gem5 Developers panic("getArgument(): No support reading stack args for AArch64\n"); 877693SAli.Saidi@ARM.com } 887693SAli.Saidi@ARM.com } else { 8910037SARM gem5 Developers if (size == (uint16_t)(-1)) 9010318Sandreas.hansson@arm.com // todo: should this not be sizeof(uint32_t) rather? 9110037SARM gem5 Developers size = ArmISA::MachineBytes; 9210037SARM gem5 Developers 9310037SARM gem5 Developers if (number < NumArgumentRegs) { 9410037SARM gem5 Developers // If the argument is 64 bits, it must be in an even regiser 9510037SARM gem5 Developers // number. Increment the number here if it isn't even. 9610037SARM gem5 Developers if (size == sizeof(uint64_t)) { 9710037SARM gem5 Developers if ((number % 2) != 0) 9810037SARM gem5 Developers number++; 9910037SARM gem5 Developers // Read the two halves of the data. Number is inc here to 10010037SARM gem5 Developers // get the second half of the 64 bit reg. 10110037SARM gem5 Developers uint64_t tmp; 10210037SARM gem5 Developers tmp = tc->readIntReg(number++); 10310037SARM gem5 Developers tmp |= tc->readIntReg(number) << 32; 10410037SARM gem5 Developers return tmp; 10510037SARM gem5 Developers } else { 10610037SARM gem5 Developers return tc->readIntReg(number); 10710037SARM gem5 Developers } 10810037SARM gem5 Developers } else { 10910037SARM gem5 Developers Addr sp = tc->readIntReg(StackPointerReg); 11010037SARM gem5 Developers FSTranslatingPortProxy &vp = tc->getVirtProxy(); 11110037SARM gem5 Developers uint64_t arg; 11210037SARM gem5 Developers if (size == sizeof(uint64_t)) { 11310037SARM gem5 Developers // If the argument is even it must be aligned 11410037SARM gem5 Developers if ((number % 2) != 0) 11510037SARM gem5 Developers number++; 11610037SARM gem5 Developers arg = vp.read<uint64_t>(sp + 11710037SARM gem5 Developers (number-NumArgumentRegs) * sizeof(uint32_t)); 11810037SARM gem5 Developers // since two 32 bit args == 1 64 bit arg, increment number 1197693SAli.Saidi@ARM.com number++; 12010037SARM gem5 Developers } else { 12110037SARM gem5 Developers arg = vp.read<uint32_t>(sp + 12210037SARM gem5 Developers (number-NumArgumentRegs) * sizeof(uint32_t)); 12310037SARM gem5 Developers } 12410037SARM gem5 Developers return arg; 1257693SAli.Saidi@ARM.com } 1267650SAli.Saidi@ARM.com } 12710037SARM gem5 Developers panic("getArgument() should always return\n"); 1286757SAli.Saidi@ARM.com} 1296757SAli.Saidi@ARM.com 1307693SAli.Saidi@ARM.comvoid 1317693SAli.Saidi@ARM.comskipFunction(ThreadContext *tc) 1327693SAli.Saidi@ARM.com{ 1339920Syasuko.eckert@amd.com PCState newPC = tc->pcState(); 13410037SARM gem5 Developers if (inAArch64(tc)) { 13510037SARM gem5 Developers newPC.set(tc->readIntReg(INTREG_X30)); 13610037SARM gem5 Developers } else { 13710037SARM gem5 Developers newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1)); 13810037SARM gem5 Developers } 1398887Sgeoffrey.blake@arm.com 1408887Sgeoffrey.blake@arm.com CheckerCPU *checker = tc->getCheckerCpuPtr(); 1418887Sgeoffrey.blake@arm.com if (checker) { 1428887Sgeoffrey.blake@arm.com tc->pcStateNoRecord(newPC); 1438887Sgeoffrey.blake@arm.com } else { 1448887Sgeoffrey.blake@arm.com tc->pcState(newPC); 1458887Sgeoffrey.blake@arm.com } 1467693SAli.Saidi@ARM.com} 1477693SAli.Saidi@ARM.com 1487748SAli.Saidi@ARM.comvoid 1497748SAli.Saidi@ARM.comcopyRegs(ThreadContext *src, ThreadContext *dest) 1507748SAli.Saidi@ARM.com{ 1519920Syasuko.eckert@amd.com for (int i = 0; i < NumIntRegs; i++) 1529431SAndreas.Sandberg@ARM.com dest->setIntRegFlat(i, src->readIntRegFlat(i)); 1538208SAli.Saidi@ARM.com 1549920Syasuko.eckert@amd.com for (int i = 0; i < NumFloatRegs; i++) 1559431SAndreas.Sandberg@ARM.com dest->setFloatRegFlat(i, src->readFloatRegFlat(i)); 1568208SAli.Saidi@ARM.com 15712109SRekai.GonzalezAlberquilla@arm.com for (int i = 0; i < NumVecRegs; i++) 15812109SRekai.GonzalezAlberquilla@arm.com dest->setVecRegFlat(i, src->readVecRegFlat(i)); 15912109SRekai.GonzalezAlberquilla@arm.com 16010338SCurtis.Dunham@arm.com for (int i = 0; i < NumCCRegs; i++) 16110338SCurtis.Dunham@arm.com dest->setCCReg(i, src->readCCReg(i)); 1629920Syasuko.eckert@amd.com 1639920Syasuko.eckert@amd.com for (int i = 0; i < NumMiscRegs; i++) 1647748SAli.Saidi@ARM.com dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); 1656759SAli.Saidi@ARM.com 1667748SAli.Saidi@ARM.com // setMiscReg "with effect" will set the misc register mapping correctly. 1677748SAli.Saidi@ARM.com // e.g. updateRegMap(val) 1687748SAli.Saidi@ARM.com dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR)); 1697748SAli.Saidi@ARM.com 1707749SAli.Saidi@ARM.com // Copy over the PC State 1717748SAli.Saidi@ARM.com dest->pcState(src->pcState()); 1727749SAli.Saidi@ARM.com 1737749SAli.Saidi@ARM.com // Invalidate the tlb misc register cache 17412406Sgabeblack@google.com dynamic_cast<TLB *>(dest->getITBPtr())->invalidateMiscReg(); 17512406Sgabeblack@google.com dynamic_cast<TLB *>(dest->getDTBPtr())->invalidateMiscReg(); 1766759SAli.Saidi@ARM.com} 1777752SWilliam.Wang@arm.com 17810037SARM gem5 Developersbool 17910037SARM gem5 DevelopersinSecureState(ThreadContext *tc) 18010037SARM gem5 Developers{ 18110037SARM gem5 Developers SCR scr = inAArch64(tc) ? tc->readMiscReg(MISCREG_SCR_EL3) : 18210037SARM gem5 Developers tc->readMiscReg(MISCREG_SCR); 18310037SARM gem5 Developers return ArmSystem::haveSecurity(tc) && inSecureState( 18410037SARM gem5 Developers scr, tc->readMiscReg(MISCREG_CPSR)); 18510037SARM gem5 Developers} 18610037SARM gem5 Developers 18710037SARM gem5 Developersbool 18810037SARM gem5 DevelopersinAArch64(ThreadContext *tc) 18910037SARM gem5 Developers{ 19010037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 19110037SARM gem5 Developers return opModeIs64((OperatingMode) (uint8_t) cpsr.mode); 19210037SARM gem5 Developers} 19310037SARM gem5 Developers 19410037SARM gem5 Developersbool 19510037SARM gem5 DeveloperslongDescFormatInUse(ThreadContext *tc) 19610037SARM gem5 Developers{ 19710037SARM gem5 Developers TTBCR ttbcr = tc->readMiscReg(MISCREG_TTBCR); 19810037SARM gem5 Developers return ArmSystem::haveLPAE(tc) && ttbcr.eae; 19910037SARM gem5 Developers} 20010037SARM gem5 Developers 20110037SARM gem5 Developersuint32_t 20210037SARM gem5 DevelopersgetMPIDR(ArmSystem *arm_sys, ThreadContext *tc) 20310037SARM gem5 Developers{ 20410190Sakash.bagdia@arm.com // Multiprocessor Affinity Register MPIDR from Cortex(tm)-A15 Technical 20510190Sakash.bagdia@arm.com // Reference Manual 20610190Sakash.bagdia@arm.com // 20710190Sakash.bagdia@arm.com // bit 31 - Multi-processor extensions available 20810190Sakash.bagdia@arm.com // bit 30 - Uni-processor system 20910190Sakash.bagdia@arm.com // bit 24 - Multi-threaded cores 21010190Sakash.bagdia@arm.com // bit 11-8 - Cluster ID 21110190Sakash.bagdia@arm.com // bit 1-0 - CPU ID 21210190Sakash.bagdia@arm.com // 21310190Sakash.bagdia@arm.com // We deliberately extend both the Cluster ID and CPU ID fields to allow 21410190Sakash.bagdia@arm.com // for simulation of larger systems 21510190Sakash.bagdia@arm.com assert((0 <= tc->cpuId()) && (tc->cpuId() < 256)); 21611294Sandreas.hansson@arm.com assert(tc->socketId() < 65536); 21711149Smitch.hayenga@arm.com if (arm_sys->multiThread) { 21811149Smitch.hayenga@arm.com return 0x80000000 | // multiprocessor extensions available 21911149Smitch.hayenga@arm.com tc->contextId(); 22011149Smitch.hayenga@arm.com } else if (arm_sys->multiProc) { 22110037SARM gem5 Developers return 0x80000000 | // multiprocessor extensions available 22210190Sakash.bagdia@arm.com tc->cpuId() | tc->socketId() << 8; 22310037SARM gem5 Developers } else { 22410037SARM gem5 Developers return 0x80000000 | // multiprocessor extensions available 22510037SARM gem5 Developers 0x40000000 | // in up system 22610190Sakash.bagdia@arm.com tc->cpuId() | tc->socketId() << 8; 22710037SARM gem5 Developers } 22810037SARM gem5 Developers} 22910037SARM gem5 Developers 23010037SARM gem5 Developersbool 23110037SARM gem5 DevelopersELIs64(ThreadContext *tc, ExceptionLevel el) 23210037SARM gem5 Developers{ 23310037SARM gem5 Developers if (ArmSystem::highestEL(tc) == el) 23410037SARM gem5 Developers // Register width is hard-wired 23510037SARM gem5 Developers return ArmSystem::highestELIs64(tc); 23610037SARM gem5 Developers 23710037SARM gem5 Developers switch (el) { 23810037SARM gem5 Developers case EL0: 23910037SARM gem5 Developers return opModeIs64(currOpMode(tc)); 24010037SARM gem5 Developers case EL1: 24110037SARM gem5 Developers { 24211574SCurtis.Dunham@arm.com if (ArmSystem::haveVirtualization(tc)) { 24311574SCurtis.Dunham@arm.com HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); 24411574SCurtis.Dunham@arm.com return hcr.rw; 24511574SCurtis.Dunham@arm.com } else if (ArmSystem::haveSecurity(tc)) { 24611574SCurtis.Dunham@arm.com SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); 24711574SCurtis.Dunham@arm.com return scr.rw; 24811574SCurtis.Dunham@arm.com } 24911574SCurtis.Dunham@arm.com panic("must haveSecurity(tc)"); 25010037SARM gem5 Developers } 25110037SARM gem5 Developers case EL2: 25210037SARM gem5 Developers { 25310037SARM gem5 Developers assert(ArmSystem::haveSecurity(tc)); 25410037SARM gem5 Developers SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); 25510037SARM gem5 Developers return scr.rw; 25610037SARM gem5 Developers } 25710037SARM gem5 Developers default: 25810037SARM gem5 Developers panic("Invalid exception level"); 25910037SARM gem5 Developers break; 26010037SARM gem5 Developers } 26110037SARM gem5 Developers} 26210037SARM gem5 Developers 26310037SARM gem5 Developersbool 26410037SARM gem5 DevelopersisBigEndian64(ThreadContext *tc) 26510037SARM gem5 Developers{ 26610037SARM gem5 Developers switch (opModeToEL(currOpMode(tc))) { 26710037SARM gem5 Developers case EL3: 26810037SARM gem5 Developers return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).ee; 26910037SARM gem5 Developers case EL2: 27010037SARM gem5 Developers return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).ee; 27110037SARM gem5 Developers case EL1: 27210037SARM gem5 Developers return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).ee; 27310037SARM gem5 Developers case EL0: 27410037SARM gem5 Developers return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).e0e; 27510037SARM gem5 Developers default: 27610037SARM gem5 Developers panic("Invalid exception level"); 27710037SARM gem5 Developers break; 27810037SARM gem5 Developers } 27910037SARM gem5 Developers} 28010037SARM gem5 Developers 28110037SARM gem5 DevelopersAddr 28210854SNathanael.Premillieu@arm.compurifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el, 28310854SNathanael.Premillieu@arm.com TTBCR tcr) 28410854SNathanael.Premillieu@arm.com{ 28510854SNathanael.Premillieu@arm.com switch (el) { 28610854SNathanael.Premillieu@arm.com case EL0: 28710854SNathanael.Premillieu@arm.com case EL1: 28810854SNathanael.Premillieu@arm.com if (bits(addr, 55, 48) == 0xFF && tcr.tbi1) 28910854SNathanael.Premillieu@arm.com return addr | mask(63, 55); 29010854SNathanael.Premillieu@arm.com else if (!bits(addr, 55, 48) && tcr.tbi0) 29110854SNathanael.Premillieu@arm.com return bits(addr,55, 0); 29210854SNathanael.Premillieu@arm.com break; 29311574SCurtis.Dunham@arm.com case EL2: 29411574SCurtis.Dunham@arm.com assert(ArmSystem::haveVirtualization(tc)); 29511574SCurtis.Dunham@arm.com tcr = tc->readMiscReg(MISCREG_TCR_EL2); 29611574SCurtis.Dunham@arm.com if (tcr.tbi) 29711574SCurtis.Dunham@arm.com return addr & mask(56); 29811574SCurtis.Dunham@arm.com break; 29910854SNathanael.Premillieu@arm.com case EL3: 30010854SNathanael.Premillieu@arm.com assert(ArmSystem::haveSecurity(tc)); 30110854SNathanael.Premillieu@arm.com if (tcr.tbi) 30210854SNathanael.Premillieu@arm.com return addr & mask(56); 30310854SNathanael.Premillieu@arm.com break; 30410854SNathanael.Premillieu@arm.com default: 30510854SNathanael.Premillieu@arm.com panic("Invalid exception level"); 30610854SNathanael.Premillieu@arm.com break; 30710854SNathanael.Premillieu@arm.com } 30810854SNathanael.Premillieu@arm.com 30910854SNathanael.Premillieu@arm.com return addr; // Nothing to do if this is not a tagged address 31010854SNathanael.Premillieu@arm.com} 31110854SNathanael.Premillieu@arm.com 31210854SNathanael.Premillieu@arm.comAddr 31310037SARM gem5 DeveloperspurifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el) 31410037SARM gem5 Developers{ 31510037SARM gem5 Developers TTBCR tcr; 31610037SARM gem5 Developers 31710037SARM gem5 Developers switch (el) { 31810037SARM gem5 Developers case EL0: 31910037SARM gem5 Developers case EL1: 32010037SARM gem5 Developers tcr = tc->readMiscReg(MISCREG_TCR_EL1); 32110037SARM gem5 Developers if (bits(addr, 55, 48) == 0xFF && tcr.tbi1) 32210037SARM gem5 Developers return addr | mask(63, 55); 32310037SARM gem5 Developers else if (!bits(addr, 55, 48) && tcr.tbi0) 32410037SARM gem5 Developers return bits(addr,55, 0); 32510037SARM gem5 Developers break; 32611574SCurtis.Dunham@arm.com case EL2: 32711574SCurtis.Dunham@arm.com assert(ArmSystem::haveVirtualization(tc)); 32811574SCurtis.Dunham@arm.com tcr = tc->readMiscReg(MISCREG_TCR_EL2); 32911574SCurtis.Dunham@arm.com if (tcr.tbi) 33011574SCurtis.Dunham@arm.com return addr & mask(56); 33111574SCurtis.Dunham@arm.com break; 33210037SARM gem5 Developers case EL3: 33310037SARM gem5 Developers assert(ArmSystem::haveSecurity(tc)); 33410037SARM gem5 Developers tcr = tc->readMiscReg(MISCREG_TCR_EL3); 33510037SARM gem5 Developers if (tcr.tbi) 33610037SARM gem5 Developers return addr & mask(56); 33710037SARM gem5 Developers break; 33810037SARM gem5 Developers default: 33910037SARM gem5 Developers panic("Invalid exception level"); 34010037SARM gem5 Developers break; 34110037SARM gem5 Developers } 34210037SARM gem5 Developers 34310037SARM gem5 Developers return addr; // Nothing to do if this is not a tagged address 34410037SARM gem5 Developers} 34510037SARM gem5 Developers 3467752SWilliam.Wang@arm.comAddr 3477752SWilliam.Wang@arm.comtruncPage(Addr addr) 3487752SWilliam.Wang@arm.com{ 3497752SWilliam.Wang@arm.com return addr & ~(PageBytes - 1); 3507748SAli.Saidi@ARM.com} 3517752SWilliam.Wang@arm.com 3527752SWilliam.Wang@arm.comAddr 3537752SWilliam.Wang@arm.comroundPage(Addr addr) 3547752SWilliam.Wang@arm.com{ 3557752SWilliam.Wang@arm.com return (addr + PageBytes - 1) & ~(PageBytes - 1); 3567752SWilliam.Wang@arm.com} 3577752SWilliam.Wang@arm.com 35810037SARM gem5 Developersbool 35910037SARM gem5 DevelopersmcrMrc15TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, 36010037SARM gem5 Developers HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss) 36110037SARM gem5 Developers{ 36210037SARM gem5 Developers bool isRead; 36310037SARM gem5 Developers uint32_t crm; 36410037SARM gem5 Developers IntRegIndex rt; 36510037SARM gem5 Developers uint32_t crn; 36610037SARM gem5 Developers uint32_t opc1; 36710037SARM gem5 Developers uint32_t opc2; 36810037SARM gem5 Developers bool trapToHype = false; 36910037SARM gem5 Developers 37010037SARM gem5 Developers 37110037SARM gem5 Developers if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) { 37210037SARM gem5 Developers mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2); 37310037SARM gem5 Developers trapToHype = ((uint32_t) hstr) & (1 << crn); 37410037SARM gem5 Developers trapToHype |= hdcr.tpm && (crn == 9) && (crm >= 12); 37510037SARM gem5 Developers trapToHype |= hcr.tidcp && ( 37610037SARM gem5 Developers ((crn == 9) && ((crm <= 2) || ((crm >= 5) && (crm <= 8)))) || 37710037SARM gem5 Developers ((crn == 10) && ((crm <= 1) || (crm == 4) || (crm == 8))) || 37810037SARM gem5 Developers ((crn == 11) && ((crm <= 8) || (crm == 15))) ); 37910037SARM gem5 Developers 38010037SARM gem5 Developers if (!trapToHype) { 38110037SARM gem5 Developers switch (unflattenMiscReg(miscReg)) { 38210037SARM gem5 Developers case MISCREG_CPACR: 38310037SARM gem5 Developers trapToHype = hcptr.tcpac; 38410037SARM gem5 Developers break; 38510037SARM gem5 Developers case MISCREG_REVIDR: 38610037SARM gem5 Developers case MISCREG_TCMTR: 38710037SARM gem5 Developers case MISCREG_TLBTR: 38810037SARM gem5 Developers case MISCREG_AIDR: 38910037SARM gem5 Developers trapToHype = hcr.tid1; 39010037SARM gem5 Developers break; 39110037SARM gem5 Developers case MISCREG_CTR: 39210037SARM gem5 Developers case MISCREG_CCSIDR: 39310037SARM gem5 Developers case MISCREG_CLIDR: 39410037SARM gem5 Developers case MISCREG_CSSELR: 39510037SARM gem5 Developers trapToHype = hcr.tid2; 39610037SARM gem5 Developers break; 39710037SARM gem5 Developers case MISCREG_ID_PFR0: 39810037SARM gem5 Developers case MISCREG_ID_PFR1: 39910037SARM gem5 Developers case MISCREG_ID_DFR0: 40010037SARM gem5 Developers case MISCREG_ID_AFR0: 40110037SARM gem5 Developers case MISCREG_ID_MMFR0: 40210037SARM gem5 Developers case MISCREG_ID_MMFR1: 40310037SARM gem5 Developers case MISCREG_ID_MMFR2: 40410037SARM gem5 Developers case MISCREG_ID_MMFR3: 40510037SARM gem5 Developers case MISCREG_ID_ISAR0: 40610037SARM gem5 Developers case MISCREG_ID_ISAR1: 40710037SARM gem5 Developers case MISCREG_ID_ISAR2: 40810037SARM gem5 Developers case MISCREG_ID_ISAR3: 40910037SARM gem5 Developers case MISCREG_ID_ISAR4: 41010037SARM gem5 Developers case MISCREG_ID_ISAR5: 41110037SARM gem5 Developers trapToHype = hcr.tid3; 41210037SARM gem5 Developers break; 41310037SARM gem5 Developers case MISCREG_DCISW: 41410037SARM gem5 Developers case MISCREG_DCCSW: 41510037SARM gem5 Developers case MISCREG_DCCISW: 41610037SARM gem5 Developers trapToHype = hcr.tsw; 41710037SARM gem5 Developers break; 41810037SARM gem5 Developers case MISCREG_DCIMVAC: 41910037SARM gem5 Developers case MISCREG_DCCIMVAC: 42010037SARM gem5 Developers case MISCREG_DCCMVAC: 42110037SARM gem5 Developers trapToHype = hcr.tpc; 42210037SARM gem5 Developers break; 42310037SARM gem5 Developers case MISCREG_ICIMVAU: 42410037SARM gem5 Developers case MISCREG_ICIALLU: 42510037SARM gem5 Developers case MISCREG_ICIALLUIS: 42610037SARM gem5 Developers case MISCREG_DCCMVAU: 42710037SARM gem5 Developers trapToHype = hcr.tpu; 42810037SARM gem5 Developers break; 42910037SARM gem5 Developers case MISCREG_TLBIALLIS: 43010037SARM gem5 Developers case MISCREG_TLBIMVAIS: 43110037SARM gem5 Developers case MISCREG_TLBIASIDIS: 43210037SARM gem5 Developers case MISCREG_TLBIMVAAIS: 43310037SARM gem5 Developers case MISCREG_DTLBIALL: 43410037SARM gem5 Developers case MISCREG_ITLBIALL: 43510037SARM gem5 Developers case MISCREG_DTLBIMVA: 43610037SARM gem5 Developers case MISCREG_ITLBIMVA: 43710037SARM gem5 Developers case MISCREG_DTLBIASID: 43810037SARM gem5 Developers case MISCREG_ITLBIASID: 43910037SARM gem5 Developers case MISCREG_TLBIMVAA: 44010037SARM gem5 Developers case MISCREG_TLBIALL: 44110037SARM gem5 Developers case MISCREG_TLBIMVA: 44210037SARM gem5 Developers case MISCREG_TLBIASID: 44310037SARM gem5 Developers trapToHype = hcr.ttlb; 44410037SARM gem5 Developers break; 44510037SARM gem5 Developers case MISCREG_ACTLR: 44610037SARM gem5 Developers trapToHype = hcr.tac; 44710037SARM gem5 Developers break; 44810037SARM gem5 Developers case MISCREG_SCTLR: 44910037SARM gem5 Developers case MISCREG_TTBR0: 45010037SARM gem5 Developers case MISCREG_TTBR1: 45110037SARM gem5 Developers case MISCREG_TTBCR: 45210037SARM gem5 Developers case MISCREG_DACR: 45310037SARM gem5 Developers case MISCREG_DFSR: 45410037SARM gem5 Developers case MISCREG_IFSR: 45510037SARM gem5 Developers case MISCREG_DFAR: 45610037SARM gem5 Developers case MISCREG_IFAR: 45710037SARM gem5 Developers case MISCREG_ADFSR: 45810037SARM gem5 Developers case MISCREG_AIFSR: 45910037SARM gem5 Developers case MISCREG_PRRR: 46010037SARM gem5 Developers case MISCREG_NMRR: 46110037SARM gem5 Developers case MISCREG_MAIR0: 46210037SARM gem5 Developers case MISCREG_MAIR1: 46310037SARM gem5 Developers case MISCREG_CONTEXTIDR: 46410037SARM gem5 Developers trapToHype = hcr.tvm & !isRead; 46510037SARM gem5 Developers break; 46610037SARM gem5 Developers case MISCREG_PMCR: 46710037SARM gem5 Developers trapToHype = hdcr.tpmcr; 46810037SARM gem5 Developers break; 46910037SARM gem5 Developers // No default action needed 47010037SARM gem5 Developers default: 47110037SARM gem5 Developers break; 47210037SARM gem5 Developers } 47310037SARM gem5 Developers } 47410037SARM gem5 Developers } 47510037SARM gem5 Developers return trapToHype; 47610037SARM gem5 Developers} 47710037SARM gem5 Developers 47810037SARM gem5 Developers 47910037SARM gem5 Developersbool 48010037SARM gem5 DevelopersmcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, 48110037SARM gem5 Developers HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss) 48210037SARM gem5 Developers{ 48310037SARM gem5 Developers bool isRead; 48410037SARM gem5 Developers uint32_t crm; 48510037SARM gem5 Developers IntRegIndex rt; 48610037SARM gem5 Developers uint32_t crn; 48710037SARM gem5 Developers uint32_t opc1; 48810037SARM gem5 Developers uint32_t opc2; 48910037SARM gem5 Developers bool trapToHype = false; 49010037SARM gem5 Developers 49110037SARM gem5 Developers if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) { 49210037SARM gem5 Developers mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2); 49310037SARM gem5 Developers inform("trap check M:%x N:%x 1:%x 2:%x hdcr %x, hcptr %x, hstr %x\n", 49410037SARM gem5 Developers crm, crn, opc1, opc2, hdcr, hcptr, hstr); 49510037SARM gem5 Developers trapToHype = hdcr.tda && (opc1 == 0); 49610037SARM gem5 Developers trapToHype |= hcptr.tta && (opc1 == 1); 49710037SARM gem5 Developers if (!trapToHype) { 49810037SARM gem5 Developers switch (unflattenMiscReg(miscReg)) { 49910037SARM gem5 Developers case MISCREG_DBGOSLSR: 50010037SARM gem5 Developers case MISCREG_DBGOSLAR: 50110037SARM gem5 Developers case MISCREG_DBGOSDLR: 50210037SARM gem5 Developers case MISCREG_DBGPRCR: 50310037SARM gem5 Developers trapToHype = hdcr.tdosa; 50410037SARM gem5 Developers break; 50510037SARM gem5 Developers case MISCREG_DBGDRAR: 50610037SARM gem5 Developers case MISCREG_DBGDSAR: 50710037SARM gem5 Developers trapToHype = hdcr.tdra; 50810037SARM gem5 Developers break; 50910037SARM gem5 Developers case MISCREG_JIDR: 51010037SARM gem5 Developers trapToHype = hcr.tid0; 51110037SARM gem5 Developers break; 51210037SARM gem5 Developers case MISCREG_JOSCR: 51310037SARM gem5 Developers case MISCREG_JMCR: 51410037SARM gem5 Developers trapToHype = hstr.tjdbx; 51510037SARM gem5 Developers break; 51610037SARM gem5 Developers case MISCREG_TEECR: 51710037SARM gem5 Developers case MISCREG_TEEHBR: 51810037SARM gem5 Developers trapToHype = hstr.ttee; 51910037SARM gem5 Developers break; 52010037SARM gem5 Developers // No default action needed 52110037SARM gem5 Developers default: 52210037SARM gem5 Developers break; 52310037SARM gem5 Developers } 52410037SARM gem5 Developers } 52510037SARM gem5 Developers } 52610037SARM gem5 Developers return trapToHype; 52710037SARM gem5 Developers} 52810037SARM gem5 Developers 52910037SARM gem5 Developersbool 53010037SARM gem5 DevelopersmcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr, 53110037SARM gem5 Developers HCR hcr, uint32_t iss) 53210037SARM gem5 Developers{ 53310037SARM gem5 Developers uint32_t crm; 53410037SARM gem5 Developers IntRegIndex rt; 53510037SARM gem5 Developers uint32_t crn; 53610037SARM gem5 Developers uint32_t opc1; 53710037SARM gem5 Developers uint32_t opc2; 53810037SARM gem5 Developers bool isRead; 53910037SARM gem5 Developers bool trapToHype = false; 54010037SARM gem5 Developers 54110037SARM gem5 Developers if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) { 54210037SARM gem5 Developers // This is technically the wrong function, but we can re-use it for 54310037SARM gem5 Developers // the moment because we only need one field, which overlaps with the 54410037SARM gem5 Developers // mcrmrc layout 54510037SARM gem5 Developers mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2); 54610037SARM gem5 Developers trapToHype = ((uint32_t) hstr) & (1 << crm); 54710037SARM gem5 Developers 54810037SARM gem5 Developers if (!trapToHype) { 54910037SARM gem5 Developers switch (unflattenMiscReg(miscReg)) { 55010037SARM gem5 Developers case MISCREG_SCTLR: 55110037SARM gem5 Developers case MISCREG_TTBR0: 55210037SARM gem5 Developers case MISCREG_TTBR1: 55310037SARM gem5 Developers case MISCREG_TTBCR: 55410037SARM gem5 Developers case MISCREG_DACR: 55510037SARM gem5 Developers case MISCREG_DFSR: 55610037SARM gem5 Developers case MISCREG_IFSR: 55710037SARM gem5 Developers case MISCREG_DFAR: 55810037SARM gem5 Developers case MISCREG_IFAR: 55910037SARM gem5 Developers case MISCREG_ADFSR: 56010037SARM gem5 Developers case MISCREG_AIFSR: 56110037SARM gem5 Developers case MISCREG_PRRR: 56210037SARM gem5 Developers case MISCREG_NMRR: 56310037SARM gem5 Developers case MISCREG_MAIR0: 56410037SARM gem5 Developers case MISCREG_MAIR1: 56510037SARM gem5 Developers case MISCREG_CONTEXTIDR: 56610037SARM gem5 Developers trapToHype = hcr.tvm & !isRead; 56710037SARM gem5 Developers break; 56810037SARM gem5 Developers // No default action needed 56910037SARM gem5 Developers default: 57010037SARM gem5 Developers break; 57110037SARM gem5 Developers } 57210037SARM gem5 Developers } 57310037SARM gem5 Developers } 57410037SARM gem5 Developers return trapToHype; 57510037SARM gem5 Developers} 57610037SARM gem5 Developers 57710037SARM gem5 Developersbool 57810037SARM gem5 DevelopersmsrMrs64TrapToSup(const MiscRegIndex miscReg, ExceptionLevel el, 57910037SARM gem5 Developers CPACR cpacr /* CPACR_EL1 */) 58010037SARM gem5 Developers{ 58110037SARM gem5 Developers bool trapToSup = false; 58210037SARM gem5 Developers switch (miscReg) { 58310037SARM gem5 Developers case MISCREG_FPCR: 58410037SARM gem5 Developers case MISCREG_FPSR: 58510037SARM gem5 Developers case MISCREG_FPEXC32_EL2: 58610037SARM gem5 Developers if ((el == EL0 && cpacr.fpen != 0x3) || 58710037SARM gem5 Developers (el == EL1 && !(cpacr.fpen & 0x1))) 58810037SARM gem5 Developers trapToSup = true; 58910037SARM gem5 Developers break; 59010037SARM gem5 Developers default: 59110037SARM gem5 Developers break; 59210037SARM gem5 Developers } 59310037SARM gem5 Developers return trapToSup; 59410037SARM gem5 Developers} 59510037SARM gem5 Developers 59610037SARM gem5 Developersbool 59711582SDylan.Johnson@ARM.commsrMrs64TrapToHyp(const MiscRegIndex miscReg, 59811582SDylan.Johnson@ARM.com ExceptionLevel el, 59911582SDylan.Johnson@ARM.com bool isRead, 60010037SARM gem5 Developers CPTR cptr /* CPTR_EL2 */, 60110037SARM gem5 Developers HCR hcr /* HCR_EL2 */, 60210037SARM gem5 Developers bool * isVfpNeon) 60310037SARM gem5 Developers{ 60410037SARM gem5 Developers bool trapToHyp = false; 60510037SARM gem5 Developers *isVfpNeon = false; 60610037SARM gem5 Developers 60710037SARM gem5 Developers switch (miscReg) { 60810037SARM gem5 Developers // FP/SIMD regs 60910037SARM gem5 Developers case MISCREG_FPCR: 61010037SARM gem5 Developers case MISCREG_FPSR: 61110037SARM gem5 Developers case MISCREG_FPEXC32_EL2: 61210037SARM gem5 Developers trapToHyp = cptr.tfp; 61310037SARM gem5 Developers *isVfpNeon = true; 61410037SARM gem5 Developers break; 61510037SARM gem5 Developers // CPACR 61610037SARM gem5 Developers case MISCREG_CPACR_EL1: 61711582SDylan.Johnson@ARM.com trapToHyp = cptr.tcpac && el == EL1; 61810037SARM gem5 Developers break; 61910037SARM gem5 Developers // Virtual memory control regs 62010037SARM gem5 Developers case MISCREG_SCTLR_EL1: 62110037SARM gem5 Developers case MISCREG_TTBR0_EL1: 62210037SARM gem5 Developers case MISCREG_TTBR1_EL1: 62310037SARM gem5 Developers case MISCREG_TCR_EL1: 62410037SARM gem5 Developers case MISCREG_ESR_EL1: 62510037SARM gem5 Developers case MISCREG_FAR_EL1: 62610037SARM gem5 Developers case MISCREG_AFSR0_EL1: 62710037SARM gem5 Developers case MISCREG_AFSR1_EL1: 62810037SARM gem5 Developers case MISCREG_MAIR_EL1: 62910037SARM gem5 Developers case MISCREG_AMAIR_EL1: 63010037SARM gem5 Developers case MISCREG_CONTEXTIDR_EL1: 63111582SDylan.Johnson@ARM.com trapToHyp = ((hcr.trvm && isRead) || (hcr.tvm && !isRead)) 63211582SDylan.Johnson@ARM.com && el == EL1; 63310037SARM gem5 Developers break; 63410037SARM gem5 Developers // TLB maintenance instructions 63510037SARM gem5 Developers case MISCREG_TLBI_VMALLE1: 63610037SARM gem5 Developers case MISCREG_TLBI_VAE1_Xt: 63710037SARM gem5 Developers case MISCREG_TLBI_ASIDE1_Xt: 63810037SARM gem5 Developers case MISCREG_TLBI_VAAE1_Xt: 63910037SARM gem5 Developers case MISCREG_TLBI_VALE1_Xt: 64010037SARM gem5 Developers case MISCREG_TLBI_VAALE1_Xt: 64110037SARM gem5 Developers case MISCREG_TLBI_VMALLE1IS: 64210037SARM gem5 Developers case MISCREG_TLBI_VAE1IS_Xt: 64310037SARM gem5 Developers case MISCREG_TLBI_ASIDE1IS_Xt: 64410037SARM gem5 Developers case MISCREG_TLBI_VAAE1IS_Xt: 64510037SARM gem5 Developers case MISCREG_TLBI_VALE1IS_Xt: 64610037SARM gem5 Developers case MISCREG_TLBI_VAALE1IS_Xt: 64711582SDylan.Johnson@ARM.com trapToHyp = hcr.ttlb && el == EL1; 64810037SARM gem5 Developers break; 64910037SARM gem5 Developers // Cache maintenance instructions to the point of unification 65010037SARM gem5 Developers case MISCREG_IC_IVAU_Xt: 65110037SARM gem5 Developers case MISCREG_ICIALLU: 65210037SARM gem5 Developers case MISCREG_ICIALLUIS: 65310037SARM gem5 Developers case MISCREG_DC_CVAU_Xt: 65411582SDylan.Johnson@ARM.com trapToHyp = hcr.tpu && el <= EL1; 65510037SARM gem5 Developers break; 65610037SARM gem5 Developers // Data/Unified cache maintenance instructions to the point of coherency 65710037SARM gem5 Developers case MISCREG_DC_IVAC_Xt: 65810037SARM gem5 Developers case MISCREG_DC_CIVAC_Xt: 65910037SARM gem5 Developers case MISCREG_DC_CVAC_Xt: 66011582SDylan.Johnson@ARM.com trapToHyp = hcr.tpc && el <= EL1; 66110037SARM gem5 Developers break; 66210037SARM gem5 Developers // Data/Unified cache maintenance instructions by set/way 66310037SARM gem5 Developers case MISCREG_DC_ISW_Xt: 66410037SARM gem5 Developers case MISCREG_DC_CSW_Xt: 66510037SARM gem5 Developers case MISCREG_DC_CISW_Xt: 66611582SDylan.Johnson@ARM.com trapToHyp = hcr.tsw && el == EL1; 66710037SARM gem5 Developers break; 66810037SARM gem5 Developers // ACTLR 66910037SARM gem5 Developers case MISCREG_ACTLR_EL1: 67011582SDylan.Johnson@ARM.com trapToHyp = hcr.tacr && el == EL1; 67110037SARM gem5 Developers break; 67210037SARM gem5 Developers 67310037SARM gem5 Developers // @todo: Trap implementation-dependent functionality based on 67410037SARM gem5 Developers // hcr.tidcp 67510037SARM gem5 Developers 67610037SARM gem5 Developers // ID regs, group 3 67710037SARM gem5 Developers case MISCREG_ID_PFR0_EL1: 67810037SARM gem5 Developers case MISCREG_ID_PFR1_EL1: 67910037SARM gem5 Developers case MISCREG_ID_DFR0_EL1: 68010037SARM gem5 Developers case MISCREG_ID_AFR0_EL1: 68110037SARM gem5 Developers case MISCREG_ID_MMFR0_EL1: 68210037SARM gem5 Developers case MISCREG_ID_MMFR1_EL1: 68310037SARM gem5 Developers case MISCREG_ID_MMFR2_EL1: 68410037SARM gem5 Developers case MISCREG_ID_MMFR3_EL1: 68510037SARM gem5 Developers case MISCREG_ID_ISAR0_EL1: 68610037SARM gem5 Developers case MISCREG_ID_ISAR1_EL1: 68710037SARM gem5 Developers case MISCREG_ID_ISAR2_EL1: 68810037SARM gem5 Developers case MISCREG_ID_ISAR3_EL1: 68910037SARM gem5 Developers case MISCREG_ID_ISAR4_EL1: 69010037SARM gem5 Developers case MISCREG_ID_ISAR5_EL1: 69110037SARM gem5 Developers case MISCREG_MVFR0_EL1: 69210037SARM gem5 Developers case MISCREG_MVFR1_EL1: 69310037SARM gem5 Developers case MISCREG_MVFR2_EL1: 69410037SARM gem5 Developers case MISCREG_ID_AA64PFR0_EL1: 69510037SARM gem5 Developers case MISCREG_ID_AA64PFR1_EL1: 69610037SARM gem5 Developers case MISCREG_ID_AA64DFR0_EL1: 69710037SARM gem5 Developers case MISCREG_ID_AA64DFR1_EL1: 69810037SARM gem5 Developers case MISCREG_ID_AA64ISAR0_EL1: 69910037SARM gem5 Developers case MISCREG_ID_AA64ISAR1_EL1: 70010037SARM gem5 Developers case MISCREG_ID_AA64MMFR0_EL1: 70110037SARM gem5 Developers case MISCREG_ID_AA64MMFR1_EL1: 70210037SARM gem5 Developers case MISCREG_ID_AA64AFR0_EL1: 70310037SARM gem5 Developers case MISCREG_ID_AA64AFR1_EL1: 70410037SARM gem5 Developers assert(isRead); 70511582SDylan.Johnson@ARM.com trapToHyp = hcr.tid3 && el == EL1; 70610037SARM gem5 Developers break; 70710037SARM gem5 Developers // ID regs, group 2 70810037SARM gem5 Developers case MISCREG_CTR_EL0: 70910037SARM gem5 Developers case MISCREG_CCSIDR_EL1: 71010037SARM gem5 Developers case MISCREG_CLIDR_EL1: 71110037SARM gem5 Developers case MISCREG_CSSELR_EL1: 71211582SDylan.Johnson@ARM.com trapToHyp = hcr.tid2 && el <= EL1; 71310037SARM gem5 Developers break; 71410037SARM gem5 Developers // ID regs, group 1 71510037SARM gem5 Developers case MISCREG_AIDR_EL1: 71610037SARM gem5 Developers case MISCREG_REVIDR_EL1: 71710037SARM gem5 Developers assert(isRead); 71811582SDylan.Johnson@ARM.com trapToHyp = hcr.tid1 && el == EL1; 71910037SARM gem5 Developers break; 72010037SARM gem5 Developers default: 72110037SARM gem5 Developers break; 72210037SARM gem5 Developers } 72310037SARM gem5 Developers return trapToHyp; 72410037SARM gem5 Developers} 72510037SARM gem5 Developers 72610037SARM gem5 Developersbool 72710037SARM gem5 DevelopersmsrMrs64TrapToMon(const MiscRegIndex miscReg, CPTR cptr /* CPTR_EL3 */, 72810037SARM gem5 Developers ExceptionLevel el, bool * isVfpNeon) 72910037SARM gem5 Developers{ 73010037SARM gem5 Developers bool trapToMon = false; 73110037SARM gem5 Developers *isVfpNeon = false; 73210037SARM gem5 Developers 73310037SARM gem5 Developers switch (miscReg) { 73410037SARM gem5 Developers // FP/SIMD regs 73510037SARM gem5 Developers case MISCREG_FPCR: 73610037SARM gem5 Developers case MISCREG_FPSR: 73710037SARM gem5 Developers case MISCREG_FPEXC32_EL2: 73810037SARM gem5 Developers trapToMon = cptr.tfp; 73910037SARM gem5 Developers *isVfpNeon = true; 74010037SARM gem5 Developers break; 74110037SARM gem5 Developers // CPACR, CPTR 74210037SARM gem5 Developers case MISCREG_CPACR_EL1: 74310037SARM gem5 Developers if (el == EL1) { 74410037SARM gem5 Developers trapToMon = cptr.tcpac; 74510037SARM gem5 Developers } 74610037SARM gem5 Developers break; 74710037SARM gem5 Developers case MISCREG_CPTR_EL2: 74810037SARM gem5 Developers if (el == EL2) { 74910037SARM gem5 Developers trapToMon = cptr.tcpac; 75010037SARM gem5 Developers } 75110037SARM gem5 Developers break; 75210037SARM gem5 Developers default: 75310037SARM gem5 Developers break; 75410037SARM gem5 Developers } 75510037SARM gem5 Developers return trapToMon; 75610037SARM gem5 Developers} 75710037SARM gem5 Developers 75810037SARM gem5 Developersbool 75910037SARM gem5 DevelopersdecodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int ®Idx, 76010037SARM gem5 Developers CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity) 76110037SARM gem5 Developers{ 76210103Sstephan.diestelhorst@arm.com OperatingMode mode = MODE_UNDEFINED; 76310037SARM gem5 Developers bool ok = true; 76410037SARM gem5 Developers 76510037SARM gem5 Developers // R mostly indicates if its a int register or a misc reg, we override 76610037SARM gem5 Developers // below if the few corner cases 76710037SARM gem5 Developers isIntReg = !r; 76810037SARM gem5 Developers // Loosely based on ARM ARM issue C section B9.3.10 76910037SARM gem5 Developers if (r) { 77010037SARM gem5 Developers switch (sysM) 77110037SARM gem5 Developers { 77210037SARM gem5 Developers case 0xE: 77310037SARM gem5 Developers regIdx = MISCREG_SPSR_FIQ; 77410037SARM gem5 Developers mode = MODE_FIQ; 77510037SARM gem5 Developers break; 77610037SARM gem5 Developers case 0x10: 77710037SARM gem5 Developers regIdx = MISCREG_SPSR_IRQ; 77810037SARM gem5 Developers mode = MODE_IRQ; 77910037SARM gem5 Developers break; 78010037SARM gem5 Developers case 0x12: 78110037SARM gem5 Developers regIdx = MISCREG_SPSR_SVC; 78210037SARM gem5 Developers mode = MODE_SVC; 78310037SARM gem5 Developers break; 78410037SARM gem5 Developers case 0x14: 78510037SARM gem5 Developers regIdx = MISCREG_SPSR_ABT; 78610037SARM gem5 Developers mode = MODE_ABORT; 78710037SARM gem5 Developers break; 78810037SARM gem5 Developers case 0x16: 78910037SARM gem5 Developers regIdx = MISCREG_SPSR_UND; 79010037SARM gem5 Developers mode = MODE_UNDEFINED; 79110037SARM gem5 Developers break; 79210037SARM gem5 Developers case 0x1C: 79310037SARM gem5 Developers regIdx = MISCREG_SPSR_MON; 79410037SARM gem5 Developers mode = MODE_MON; 79510037SARM gem5 Developers break; 79610037SARM gem5 Developers case 0x1E: 79710037SARM gem5 Developers regIdx = MISCREG_SPSR_HYP; 79810037SARM gem5 Developers mode = MODE_HYP; 79910037SARM gem5 Developers break; 80010037SARM gem5 Developers default: 80110037SARM gem5 Developers ok = false; 80210037SARM gem5 Developers break; 80310037SARM gem5 Developers } 80410037SARM gem5 Developers } else { 80510037SARM gem5 Developers int sysM4To3 = bits(sysM, 4, 3); 80610037SARM gem5 Developers 80710037SARM gem5 Developers if (sysM4To3 == 0) { 80810037SARM gem5 Developers mode = MODE_USER; 80910037SARM gem5 Developers regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8); 81010037SARM gem5 Developers } else if (sysM4To3 == 1) { 81110037SARM gem5 Developers mode = MODE_FIQ; 81210037SARM gem5 Developers regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8); 81310037SARM gem5 Developers } else if (sysM4To3 == 3) { 81410037SARM gem5 Developers if (bits(sysM, 1) == 0) { 81510037SARM gem5 Developers mode = MODE_MON; 81610037SARM gem5 Developers regIdx = intRegInMode(mode, 14 - bits(sysM, 0)); 81710037SARM gem5 Developers } else { 81810037SARM gem5 Developers mode = MODE_HYP; 81910037SARM gem5 Developers if (bits(sysM, 0) == 1) { 82010037SARM gem5 Developers regIdx = intRegInMode(mode, 13); // R13 in HYP 82110037SARM gem5 Developers } else { 82210037SARM gem5 Developers isIntReg = false; 82310037SARM gem5 Developers regIdx = MISCREG_ELR_HYP; 82410037SARM gem5 Developers } 82510037SARM gem5 Developers } 82610037SARM gem5 Developers } else { // Other Banked registers 82710037SARM gem5 Developers int sysM2 = bits(sysM, 2); 82810037SARM gem5 Developers int sysM1 = bits(sysM, 1); 82910037SARM gem5 Developers 83010037SARM gem5 Developers mode = (OperatingMode) ( ((sysM2 || sysM1) << 0) | 83110037SARM gem5 Developers (1 << 1) | 83210037SARM gem5 Developers ((sysM2 && !sysM1) << 2) | 83310037SARM gem5 Developers ((sysM2 && sysM1) << 3) | 83410037SARM gem5 Developers (1 << 4) ); 83510037SARM gem5 Developers regIdx = intRegInMode(mode, 14 - bits(sysM, 0)); 83610037SARM gem5 Developers // Don't flatten the register here. This is going to go through 83710037SARM gem5 Developers // setIntReg() which will do the flattening 83810037SARM gem5 Developers ok &= mode != cpsr.mode; 83910037SARM gem5 Developers } 84010037SARM gem5 Developers } 84110037SARM gem5 Developers 84210037SARM gem5 Developers // Check that the requested register is accessable from the current mode 84310037SARM gem5 Developers if (ok && checkSecurity && mode != cpsr.mode) { 84410037SARM gem5 Developers switch (cpsr.mode) 84510037SARM gem5 Developers { 84610037SARM gem5 Developers case MODE_USER: 84710037SARM gem5 Developers ok = false; 84810037SARM gem5 Developers break; 84910037SARM gem5 Developers case MODE_FIQ: 85010037SARM gem5 Developers ok &= mode != MODE_HYP; 85110037SARM gem5 Developers ok &= (mode != MODE_MON) || !scr.ns; 85210037SARM gem5 Developers break; 85310037SARM gem5 Developers case MODE_HYP: 85410037SARM gem5 Developers ok &= mode != MODE_MON; 85510037SARM gem5 Developers ok &= (mode != MODE_FIQ) || !nsacr.rfr; 85610037SARM gem5 Developers break; 85710037SARM gem5 Developers case MODE_IRQ: 85810037SARM gem5 Developers case MODE_SVC: 85910037SARM gem5 Developers case MODE_ABORT: 86010037SARM gem5 Developers case MODE_UNDEFINED: 86110037SARM gem5 Developers case MODE_SYSTEM: 86210037SARM gem5 Developers ok &= mode != MODE_HYP; 86310037SARM gem5 Developers ok &= (mode != MODE_MON) || !scr.ns; 86410037SARM gem5 Developers ok &= (mode != MODE_FIQ) || !nsacr.rfr; 86510037SARM gem5 Developers break; 86610037SARM gem5 Developers // can access everything, no further checks required 86710037SARM gem5 Developers case MODE_MON: 86810037SARM gem5 Developers break; 86910037SARM gem5 Developers default: 87010037SARM gem5 Developers panic("unknown Mode 0x%x\n", cpsr.mode); 87110037SARM gem5 Developers break; 87210037SARM gem5 Developers } 87310037SARM gem5 Developers } 87410037SARM gem5 Developers return (ok); 87510037SARM gem5 Developers} 87610037SARM gem5 Developers 87710037SARM gem5 Developersbool 87810037SARM gem5 DevelopersSPAlignmentCheckEnabled(ThreadContext* tc) 87910037SARM gem5 Developers{ 88010037SARM gem5 Developers switch (opModeToEL(currOpMode(tc))) { 88110037SARM gem5 Developers case EL3: 88210037SARM gem5 Developers return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).sa; 88310037SARM gem5 Developers case EL2: 88410037SARM gem5 Developers return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).sa; 88510037SARM gem5 Developers case EL1: 88610037SARM gem5 Developers return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa; 88710037SARM gem5 Developers case EL0: 88810037SARM gem5 Developers return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa0; 88910037SARM gem5 Developers default: 89010037SARM gem5 Developers panic("Invalid exception level"); 89110037SARM gem5 Developers break; 89210037SARM gem5 Developers } 89310037SARM gem5 Developers} 89410037SARM gem5 Developers 89510037SARM gem5 Developersint 89610037SARM gem5 DevelopersdecodePhysAddrRange64(uint8_t pa_enc) 89710037SARM gem5 Developers{ 89810037SARM gem5 Developers switch (pa_enc) { 89910037SARM gem5 Developers case 0x0: 90010037SARM gem5 Developers return 32; 90110037SARM gem5 Developers case 0x1: 90210037SARM gem5 Developers return 36; 90310037SARM gem5 Developers case 0x2: 90410037SARM gem5 Developers return 40; 90510037SARM gem5 Developers case 0x3: 90610037SARM gem5 Developers return 42; 90710037SARM gem5 Developers case 0x4: 90810037SARM gem5 Developers return 44; 90910037SARM gem5 Developers case 0x5: 91010037SARM gem5 Developers case 0x6: 91110037SARM gem5 Developers case 0x7: 91210037SARM gem5 Developers return 48; 91310037SARM gem5 Developers default: 91410037SARM gem5 Developers panic("Invalid phys. address range encoding"); 91510037SARM gem5 Developers } 91610037SARM gem5 Developers} 91710037SARM gem5 Developers 91810037SARM gem5 Developersuint8_t 91910037SARM gem5 DevelopersencodePhysAddrRange64(int pa_size) 92010037SARM gem5 Developers{ 92110037SARM gem5 Developers switch (pa_size) { 92210037SARM gem5 Developers case 32: 92310037SARM gem5 Developers return 0x0; 92410037SARM gem5 Developers case 36: 92510037SARM gem5 Developers return 0x1; 92610037SARM gem5 Developers case 40: 92710037SARM gem5 Developers return 0x2; 92810037SARM gem5 Developers case 42: 92910037SARM gem5 Developers return 0x3; 93010037SARM gem5 Developers case 44: 93110037SARM gem5 Developers return 0x4; 93210037SARM gem5 Developers case 48: 93310037SARM gem5 Developers return 0x5; 93410037SARM gem5 Developers default: 93510037SARM gem5 Developers panic("Invalid phys. address range"); 93610037SARM gem5 Developers } 93710037SARM gem5 Developers} 93810037SARM gem5 Developers 9397752SWilliam.Wang@arm.com} // namespace ArmISA 940