types.hh revision 8181:f789b9aac5f4 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#ifndef __ARCH_ARM_TYPES_HH__
44#define __ARCH_ARM_TYPES_HH__
45
46#include "arch/generic/types.hh"
47#include "base/bitunion.hh"
48#include "base/hashmap.hh"
49#include "base/misc.hh"
50#include "base/types.hh"
51
52namespace ArmISA
53{
54    typedef uint32_t MachInst;
55
56    BitUnion64(ExtMachInst)
57        Bitfield<63, 56> newItstate;
58        // ITSTATE bits
59        Bitfield<55, 48> itstate;
60        Bitfield<55, 52> itstateCond;
61        Bitfield<51, 48> itstateMask;
62
63        // FPSCR fields
64        Bitfield<41, 40> fpscrStride;
65        Bitfield<39, 37> fpscrLen;
66
67        // Bitfields to select mode.
68        Bitfield<36>     thumb;
69        Bitfield<35>     bigThumb;
70
71        // Made up bitfields that make life easier.
72        Bitfield<33>     sevenAndFour;
73        Bitfield<32>     isMisc;
74
75        uint32_t         instBits;
76
77        // All the different types of opcode fields.
78        Bitfield<27, 25> encoding;
79        Bitfield<25>     useImm;
80        Bitfield<24, 21> opcode;
81        Bitfield<24, 20> mediaOpcode;
82        Bitfield<24>     opcode24;
83        Bitfield<24, 23> opcode24_23;
84        Bitfield<23, 20> opcode23_20;
85        Bitfield<23, 21> opcode23_21;
86        Bitfield<20>     opcode20;
87        Bitfield<22>     opcode22;
88        Bitfield<19, 16> opcode19_16;
89        Bitfield<19>     opcode19;
90        Bitfield<18>     opcode18;
91        Bitfield<15, 12> opcode15_12;
92        Bitfield<15>     opcode15;
93        Bitfield<7,  4>  miscOpcode;
94        Bitfield<7,5>    opc2;
95        Bitfield<7>      opcode7;
96        Bitfield<6>      opcode6;
97        Bitfield<4>      opcode4;
98
99        Bitfield<31, 28> condCode;
100        Bitfield<20>     sField;
101        Bitfield<19, 16> rn;
102        Bitfield<15, 12> rd;
103        Bitfield<15, 12> rt;
104        Bitfield<11, 7>  shiftSize;
105        Bitfield<6,  5>  shift;
106        Bitfield<3,  0>  rm;
107
108        Bitfield<11, 8>  rs;
109
110        SubBitUnion(puswl, 24, 20)
111            Bitfield<24> prepost;
112            Bitfield<23> up;
113            Bitfield<22> psruser;
114            Bitfield<21> writeback;
115            Bitfield<20> loadOp;
116        EndSubBitUnion(puswl)
117
118        Bitfield<24, 20> pubwl;
119
120        Bitfield<7, 0> imm;
121
122        Bitfield<11, 8>  rotate;
123
124        Bitfield<11, 0>  immed11_0;
125        Bitfield<7,  0>  immed7_0;
126
127        Bitfield<11, 8>  immedHi11_8;
128        Bitfield<3,  0>  immedLo3_0;
129
130        Bitfield<15, 0>  regList;
131
132        Bitfield<23, 0>  offset;
133
134        Bitfield<23, 0>  immed23_0;
135
136        Bitfield<11, 8>  cpNum;
137        Bitfield<18, 16> fn;
138        Bitfield<14, 12> fd;
139        Bitfield<3>      fpRegImm;
140        Bitfield<3,  0>  fm;
141        Bitfield<2,  0>  fpImm;
142        Bitfield<24, 20> punwl;
143
144        Bitfield<15,  8>  m5Func;
145
146        // 16 bit thumb bitfields
147        Bitfield<15, 13> topcode15_13;
148        Bitfield<13, 11> topcode13_11;
149        Bitfield<12, 11> topcode12_11;
150        Bitfield<12, 10> topcode12_10;
151        Bitfield<11, 9>  topcode11_9;
152        Bitfield<11, 8>  topcode11_8;
153        Bitfield<10, 9>  topcode10_9;
154        Bitfield<10, 8>  topcode10_8;
155        Bitfield<9,  6>  topcode9_6;
156        Bitfield<7>      topcode7;
157        Bitfield<7, 6>   topcode7_6;
158        Bitfield<7, 5>   topcode7_5;
159        Bitfield<7, 4>   topcode7_4;
160        Bitfield<3, 0>   topcode3_0;
161
162        // 32 bit thumb bitfields
163        Bitfield<28, 27> htopcode12_11;
164        Bitfield<26, 25> htopcode10_9;
165        Bitfield<25>     htopcode9;
166        Bitfield<25, 24> htopcode9_8;
167        Bitfield<25, 21> htopcode9_5;
168        Bitfield<25, 20> htopcode9_4;
169        Bitfield<24>     htopcode8;
170        Bitfield<24, 23> htopcode8_7;
171        Bitfield<24, 22> htopcode8_6;
172        Bitfield<24, 21> htopcode8_5;
173        Bitfield<23>     htopcode7;
174        Bitfield<23, 21> htopcode7_5;
175        Bitfield<22>     htopcode6;
176        Bitfield<22, 21> htopcode6_5;
177        Bitfield<21, 20> htopcode5_4;
178        Bitfield<20>     htopcode4;
179
180        Bitfield<19, 16> htrn;
181        Bitfield<20>     hts;
182
183        Bitfield<15>     ltopcode15;
184        Bitfield<11, 8>  ltopcode11_8;
185        Bitfield<7,  6>  ltopcode7_6;
186        Bitfield<7,  4>  ltopcode7_4;
187        Bitfield<4>      ltopcode4;
188
189        Bitfield<11, 8>  ltrd;
190        Bitfield<11, 8>  ltcoproc;
191    EndBitUnion(ExtMachInst)
192
193    class PCState : public GenericISA::UPCState<MachInst>
194    {
195      protected:
196
197        typedef GenericISA::UPCState<MachInst> Base;
198
199        enum FlagBits {
200            ThumbBit = (1 << 0),
201            JazelleBit = (1 << 1)
202        };
203        uint8_t flags;
204        uint8_t nextFlags;
205        uint8_t forcedItStateValue;
206        uint8_t _size;
207        bool forcedItStateValid;
208      public:
209        PCState() : flags(0), nextFlags(0), forcedItStateValue(0), forcedItStateValid(false)
210        {}
211
212        void
213        set(Addr val)
214        {
215            Base::set(val);
216            npc(val + (thumb() ? 2 : 4));
217        }
218
219        PCState(Addr val) : flags(0), nextFlags(0), forcedItStateValue(0), forcedItStateValid(false)
220        { set(val); }
221
222        bool
223        thumb() const
224        {
225            return flags & ThumbBit;
226        }
227
228        void
229        thumb(bool val)
230        {
231            if (val)
232                flags |= ThumbBit;
233            else
234                flags &= ~ThumbBit;
235        }
236
237        bool
238        nextThumb() const
239        {
240            return nextFlags & ThumbBit;
241        }
242
243        void
244        nextThumb(bool val)
245        {
246            if (val)
247                nextFlags |= ThumbBit;
248            else
249                nextFlags &= ~ThumbBit;
250        }
251
252        void size(uint8_t s) { _size = s; }
253        uint8_t size() const { return _size; }
254
255        bool
256        branching() const
257        {
258            return ((this->pc() + this->size()) != this->npc());
259        }
260
261
262        bool
263        jazelle() const
264        {
265            return flags & JazelleBit;
266        }
267
268        void
269        jazelle(bool val)
270        {
271            if (val)
272                flags |= JazelleBit;
273            else
274                flags &= ~JazelleBit;
275        }
276
277        bool
278        nextJazelle() const
279        {
280            return nextFlags & JazelleBit;
281        }
282
283        void
284        nextJazelle(bool val)
285        {
286            if (val)
287                nextFlags |= JazelleBit;
288            else
289                nextFlags &= ~JazelleBit;
290        }
291
292        uint8_t
293        forcedItState() const
294        {
295            return forcedItStateValue;
296        }
297
298        void
299        forcedItState(uint8_t value)
300        {
301            forcedItStateValue = value;
302            // Not valid unless the advance is called.
303            forcedItStateValid = false;
304        }
305
306        bool
307        forcedItStateIsValid() const
308        {
309            return forcedItStateValid;
310        }
311
312        void
313        advance()
314        {
315            Base::advance();
316            npc(pc() + (thumb() ? 2 : 4));
317            flags = nextFlags;
318
319            // Validate the itState
320            if (forcedItStateValue != 0 && !forcedItStateValid) {
321                forcedItStateValid = true;
322            } else {
323                forcedItStateValid = false;
324                forcedItStateValue = 0;
325            }
326        }
327
328        void
329        uEnd()
330        {
331            advance();
332            upc(0);
333            nupc(1);
334        }
335
336        Addr
337        instPC() const
338        {
339            return pc() + (thumb() ? 4 : 8);
340        }
341
342        void
343        instNPC(uint32_t val)
344        {
345            npc(val &~ mask(nextThumb() ? 1 : 2));
346        }
347
348        Addr
349        instNPC() const
350        {
351            return npc();
352        }
353
354        // Perform an interworking branch.
355        void
356        instIWNPC(uint32_t val)
357        {
358            bool thumbEE = (thumb() && jazelle());
359
360            Addr newPC = val;
361            if (thumbEE) {
362                if (bits(newPC, 0)) {
363                    newPC = newPC & ~mask(1);
364                }  // else we have a bad interworking address; do not call
365                   // panic() since the instruction could be executed
366                   // speculatively
367            } else {
368                if (bits(newPC, 0)) {
369                    nextThumb(true);
370                    newPC = newPC & ~mask(1);
371                } else if (!bits(newPC, 1)) {
372                    nextThumb(false);
373                } else {
374                    // This state is UNPREDICTABLE in the ARM architecture
375                    // The easy thing to do is just mask off the bit and
376                    // stay in the current mode, so we'll do that.
377                    newPC &= ~mask(2);
378                }
379            }
380            npc(newPC);
381        }
382
383        // Perform an interworking branch in ARM mode, a regular branch
384        // otherwise.
385        void
386        instAIWNPC(uint32_t val)
387        {
388            if (!thumb() && !jazelle())
389                instIWNPC(val);
390            else
391                instNPC(val);
392        }
393
394        bool
395        operator == (const PCState &opc) const
396        {
397            return Base::operator == (opc) &&
398                flags == opc.flags && nextFlags == opc.nextFlags;
399        }
400
401        void
402        serialize(std::ostream &os)
403        {
404            Base::serialize(os);
405            SERIALIZE_SCALAR(flags);
406            SERIALIZE_SCALAR(_size);
407            SERIALIZE_SCALAR(nextFlags);
408            SERIALIZE_SCALAR(forcedItStateValue);
409            SERIALIZE_SCALAR(forcedItStateValid);
410        }
411
412        void
413        unserialize(Checkpoint *cp, const std::string &section)
414        {
415            Base::unserialize(cp, section);
416            UNSERIALIZE_SCALAR(flags);
417            UNSERIALIZE_SCALAR(_size);
418            UNSERIALIZE_SCALAR(nextFlags);
419            UNSERIALIZE_SCALAR(forcedItStateValue);
420            UNSERIALIZE_SCALAR(forcedItStateValid);
421        }
422    };
423
424    // Shift types for ARM instructions
425    enum ArmShiftType {
426        LSL = 0,
427        LSR,
428        ASR,
429        ROR
430    };
431
432    typedef uint64_t LargestRead;
433    // Need to use 64 bits to make sure that read requests get handled properly
434
435    typedef int RegContextParam;
436    typedef int RegContextVal;
437
438    //used in FP convert & round function
439    enum ConvertType{
440        SINGLE_TO_DOUBLE,
441        SINGLE_TO_WORD,
442        SINGLE_TO_LONG,
443
444        DOUBLE_TO_SINGLE,
445        DOUBLE_TO_WORD,
446        DOUBLE_TO_LONG,
447
448        LONG_TO_SINGLE,
449        LONG_TO_DOUBLE,
450        LONG_TO_WORD,
451        LONG_TO_PS,
452
453        WORD_TO_SINGLE,
454        WORD_TO_DOUBLE,
455        WORD_TO_LONG,
456        WORD_TO_PS,
457
458        PL_TO_SINGLE,
459        PU_TO_SINGLE
460    };
461
462    //used in FP convert & round function
463    enum RoundMode{
464        RND_ZERO,
465        RND_DOWN,
466        RND_UP,
467        RND_NEAREST
468    };
469
470    enum OperatingMode {
471        MODE_USER = 16,
472        MODE_FIQ = 17,
473        MODE_IRQ = 18,
474        MODE_SVC = 19,
475        MODE_MON = 22,
476        MODE_ABORT = 23,
477        MODE_UNDEFINED = 27,
478        MODE_SYSTEM = 31,
479        MODE_MAXMODE = MODE_SYSTEM
480    };
481
482    static inline bool
483    badMode(OperatingMode mode)
484    {
485        switch (mode) {
486          case MODE_USER:
487          case MODE_FIQ:
488          case MODE_IRQ:
489          case MODE_SVC:
490          case MODE_MON:
491          case MODE_ABORT:
492          case MODE_UNDEFINED:
493          case MODE_SYSTEM:
494            return false;
495          default:
496            return true;
497        }
498    }
499
500} // namespace ArmISA
501
502namespace __hash_namespace {
503    template<>
504    struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> {
505        size_t operator()(const ArmISA::ExtMachInst &emi) const {
506            return hash<uint32_t>::operator()((uint32_t)emi);
507        };
508    };
509}
510
511#endif
512