types.hh revision 8075:dc266f3bcae4
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 */ 42 43#ifndef __ARCH_ARM_TYPES_HH__ 44#define __ARCH_ARM_TYPES_HH__ 45 46#include "arch/generic/types.hh" 47#include "base/bitunion.hh" 48#include "base/hashmap.hh" 49#include "base/misc.hh" 50#include "base/types.hh" 51 52namespace ArmISA 53{ 54 typedef uint32_t MachInst; 55 56 BitUnion64(ExtMachInst) 57 Bitfield<63, 56> newItstate; 58 // ITSTATE bits 59 Bitfield<55, 48> itstate; 60 Bitfield<55, 52> itstateCond; 61 Bitfield<51, 48> itstateMask; 62 63 // FPSCR fields 64 Bitfield<41, 40> fpscrStride; 65 Bitfield<39, 37> fpscrLen; 66 67 // Bitfields to select mode. 68 Bitfield<36> thumb; 69 Bitfield<35> bigThumb; 70 71 // Made up bitfields that make life easier. 72 Bitfield<33> sevenAndFour; 73 Bitfield<32> isMisc; 74 75 uint32_t instBits; 76 77 // All the different types of opcode fields. 78 Bitfield<27, 25> encoding; 79 Bitfield<25> useImm; 80 Bitfield<24, 21> opcode; 81 Bitfield<24, 20> mediaOpcode; 82 Bitfield<24> opcode24; 83 Bitfield<24, 23> opcode24_23; 84 Bitfield<23, 20> opcode23_20; 85 Bitfield<23, 21> opcode23_21; 86 Bitfield<20> opcode20; 87 Bitfield<22> opcode22; 88 Bitfield<19, 16> opcode19_16; 89 Bitfield<19> opcode19; 90 Bitfield<18> opcode18; 91 Bitfield<15, 12> opcode15_12; 92 Bitfield<15> opcode15; 93 Bitfield<7, 4> miscOpcode; 94 Bitfield<7,5> opc2; 95 Bitfield<7> opcode7; 96 Bitfield<6> opcode6; 97 Bitfield<4> opcode4; 98 99 Bitfield<31, 28> condCode; 100 Bitfield<20> sField; 101 Bitfield<19, 16> rn; 102 Bitfield<15, 12> rd; 103 Bitfield<15, 12> rt; 104 Bitfield<11, 7> shiftSize; 105 Bitfield<6, 5> shift; 106 Bitfield<3, 0> rm; 107 108 Bitfield<11, 8> rs; 109 110 SubBitUnion(puswl, 24, 20) 111 Bitfield<24> prepost; 112 Bitfield<23> up; 113 Bitfield<22> psruser; 114 Bitfield<21> writeback; 115 Bitfield<20> loadOp; 116 EndSubBitUnion(puswl) 117 118 Bitfield<24, 20> pubwl; 119 120 Bitfield<7, 0> imm; 121 122 Bitfield<11, 8> rotate; 123 124 Bitfield<11, 0> immed11_0; 125 Bitfield<7, 0> immed7_0; 126 127 Bitfield<11, 8> immedHi11_8; 128 Bitfield<3, 0> immedLo3_0; 129 130 Bitfield<15, 0> regList; 131 132 Bitfield<23, 0> offset; 133 134 Bitfield<23, 0> immed23_0; 135 136 Bitfield<11, 8> cpNum; 137 Bitfield<18, 16> fn; 138 Bitfield<14, 12> fd; 139 Bitfield<3> fpRegImm; 140 Bitfield<3, 0> fm; 141 Bitfield<2, 0> fpImm; 142 Bitfield<24, 20> punwl; 143 144 Bitfield<15, 8> m5Func; 145 146 // 16 bit thumb bitfields 147 Bitfield<15, 13> topcode15_13; 148 Bitfield<13, 11> topcode13_11; 149 Bitfield<12, 11> topcode12_11; 150 Bitfield<12, 10> topcode12_10; 151 Bitfield<11, 9> topcode11_9; 152 Bitfield<11, 8> topcode11_8; 153 Bitfield<10, 9> topcode10_9; 154 Bitfield<10, 8> topcode10_8; 155 Bitfield<9, 6> topcode9_6; 156 Bitfield<7> topcode7; 157 Bitfield<7, 6> topcode7_6; 158 Bitfield<7, 5> topcode7_5; 159 Bitfield<7, 4> topcode7_4; 160 Bitfield<3, 0> topcode3_0; 161 162 // 32 bit thumb bitfields 163 Bitfield<28, 27> htopcode12_11; 164 Bitfield<26, 25> htopcode10_9; 165 Bitfield<25> htopcode9; 166 Bitfield<25, 24> htopcode9_8; 167 Bitfield<25, 21> htopcode9_5; 168 Bitfield<25, 20> htopcode9_4; 169 Bitfield<24> htopcode8; 170 Bitfield<24, 23> htopcode8_7; 171 Bitfield<24, 22> htopcode8_6; 172 Bitfield<24, 21> htopcode8_5; 173 Bitfield<23> htopcode7; 174 Bitfield<23, 21> htopcode7_5; 175 Bitfield<22> htopcode6; 176 Bitfield<22, 21> htopcode6_5; 177 Bitfield<21, 20> htopcode5_4; 178 Bitfield<20> htopcode4; 179 180 Bitfield<19, 16> htrn; 181 Bitfield<20> hts; 182 183 Bitfield<15> ltopcode15; 184 Bitfield<11, 8> ltopcode11_8; 185 Bitfield<7, 6> ltopcode7_6; 186 Bitfield<7, 4> ltopcode7_4; 187 Bitfield<4> ltopcode4; 188 189 Bitfield<11, 8> ltrd; 190 Bitfield<11, 8> ltcoproc; 191 EndBitUnion(ExtMachInst) 192 193 class PCState : public GenericISA::UPCState<MachInst> 194 { 195 protected: 196 197 typedef GenericISA::UPCState<MachInst> Base; 198 199 enum FlagBits { 200 ThumbBit = (1 << 0), 201 JazelleBit = (1 << 1) 202 }; 203 uint8_t flags; 204 uint8_t nextFlags; 205 uint8_t forcedItStateValue; 206 bool forcedItStateValid; 207 public: 208 PCState() : flags(0), nextFlags(0), forcedItStateValue(0), forcedItStateValid(false) 209 {} 210 211 void 212 set(Addr val) 213 { 214 Base::set(val); 215 npc(val + (thumb() ? 2 : 4)); 216 } 217 218 PCState(Addr val) : flags(0), nextFlags(0), forcedItStateValue(0), forcedItStateValid(false) 219 { set(val); } 220 221 bool 222 thumb() const 223 { 224 return flags & ThumbBit; 225 } 226 227 void 228 thumb(bool val) 229 { 230 if (val) 231 flags |= ThumbBit; 232 else 233 flags &= ~ThumbBit; 234 } 235 236 bool 237 nextThumb() const 238 { 239 return nextFlags & ThumbBit; 240 } 241 242 void 243 nextThumb(bool val) 244 { 245 if (val) 246 nextFlags |= ThumbBit; 247 else 248 nextFlags &= ~ThumbBit; 249 } 250 251 bool 252 jazelle() const 253 { 254 return flags & JazelleBit; 255 } 256 257 void 258 jazelle(bool val) 259 { 260 if (val) 261 flags |= JazelleBit; 262 else 263 flags &= ~JazelleBit; 264 } 265 266 bool 267 nextJazelle() const 268 { 269 return nextFlags & JazelleBit; 270 } 271 272 void 273 nextJazelle(bool val) 274 { 275 if (val) 276 nextFlags |= JazelleBit; 277 else 278 nextFlags &= ~JazelleBit; 279 } 280 281 uint8_t 282 forcedItState() const 283 { 284 return forcedItStateValue; 285 } 286 287 void 288 forcedItState(uint8_t value) 289 { 290 forcedItStateValue = value; 291 // Not valid unless the advance is called. 292 forcedItStateValid = false; 293 } 294 295 bool 296 forcedItStateIsValid() const 297 { 298 return forcedItStateValid; 299 } 300 301 void 302 advance() 303 { 304 Base::advance(); 305 npc(pc() + (thumb() ? 2 : 4)); 306 flags = nextFlags; 307 308 // Validate the itState 309 if (forcedItStateValue != 0 && !forcedItStateValid) { 310 forcedItStateValid = true; 311 } else { 312 forcedItStateValid = false; 313 forcedItStateValue = 0; 314 } 315 } 316 317 void 318 uEnd() 319 { 320 advance(); 321 upc(0); 322 nupc(1); 323 } 324 325 Addr 326 instPC() const 327 { 328 return pc() + (thumb() ? 4 : 8); 329 } 330 331 void 332 instNPC(uint32_t val) 333 { 334 npc(val &~ mask(nextThumb() ? 1 : 2)); 335 } 336 337 Addr 338 instNPC() const 339 { 340 return npc(); 341 } 342 343 // Perform an interworking branch. 344 void 345 instIWNPC(uint32_t val) 346 { 347 bool thumbEE = (thumb() && jazelle()); 348 349 Addr newPC = val; 350 if (thumbEE) { 351 if (bits(newPC, 0)) { 352 newPC = newPC & ~mask(1); 353 } // else we have a bad interworking address; do not call 354 // panic() since the instruction could be executed 355 // speculatively 356 } else { 357 if (bits(newPC, 0)) { 358 nextThumb(true); 359 newPC = newPC & ~mask(1); 360 } else if (!bits(newPC, 1)) { 361 nextThumb(false); 362 } else { 363 // This state is UNPREDICTABLE in the ARM architecture 364 // The easy thing to do is just mask off the bit and 365 // stay in the current mode, so we'll do that. 366 newPC &= ~mask(2); 367 } 368 } 369 npc(newPC); 370 } 371 372 // Perform an interworking branch in ARM mode, a regular branch 373 // otherwise. 374 void 375 instAIWNPC(uint32_t val) 376 { 377 if (!thumb() && !jazelle()) 378 instIWNPC(val); 379 else 380 instNPC(val); 381 } 382 383 bool 384 operator == (const PCState &opc) const 385 { 386 return Base::operator == (opc) && 387 flags == opc.flags && nextFlags == opc.nextFlags; 388 } 389 390 void 391 serialize(std::ostream &os) 392 { 393 Base::serialize(os); 394 SERIALIZE_SCALAR(flags); 395 SERIALIZE_SCALAR(nextFlags); 396 SERIALIZE_SCALAR(forcedItStateValue); 397 SERIALIZE_SCALAR(forcedItStateValid); 398 } 399 400 void 401 unserialize(Checkpoint *cp, const std::string §ion) 402 { 403 Base::unserialize(cp, section); 404 UNSERIALIZE_SCALAR(flags); 405 UNSERIALIZE_SCALAR(nextFlags); 406 UNSERIALIZE_SCALAR(forcedItStateValue); 407 UNSERIALIZE_SCALAR(forcedItStateValid); 408 } 409 }; 410 411 // Shift types for ARM instructions 412 enum ArmShiftType { 413 LSL = 0, 414 LSR, 415 ASR, 416 ROR 417 }; 418 419 typedef uint64_t LargestRead; 420 // Need to use 64 bits to make sure that read requests get handled properly 421 422 typedef int RegContextParam; 423 typedef int RegContextVal; 424 425 //used in FP convert & round function 426 enum ConvertType{ 427 SINGLE_TO_DOUBLE, 428 SINGLE_TO_WORD, 429 SINGLE_TO_LONG, 430 431 DOUBLE_TO_SINGLE, 432 DOUBLE_TO_WORD, 433 DOUBLE_TO_LONG, 434 435 LONG_TO_SINGLE, 436 LONG_TO_DOUBLE, 437 LONG_TO_WORD, 438 LONG_TO_PS, 439 440 WORD_TO_SINGLE, 441 WORD_TO_DOUBLE, 442 WORD_TO_LONG, 443 WORD_TO_PS, 444 445 PL_TO_SINGLE, 446 PU_TO_SINGLE 447 }; 448 449 //used in FP convert & round function 450 enum RoundMode{ 451 RND_ZERO, 452 RND_DOWN, 453 RND_UP, 454 RND_NEAREST 455 }; 456 457 enum OperatingMode { 458 MODE_USER = 16, 459 MODE_FIQ = 17, 460 MODE_IRQ = 18, 461 MODE_SVC = 19, 462 MODE_MON = 22, 463 MODE_ABORT = 23, 464 MODE_UNDEFINED = 27, 465 MODE_SYSTEM = 31, 466 MODE_MAXMODE = MODE_SYSTEM 467 }; 468 469 static inline bool 470 badMode(OperatingMode mode) 471 { 472 switch (mode) { 473 case MODE_USER: 474 case MODE_FIQ: 475 case MODE_IRQ: 476 case MODE_SVC: 477 case MODE_MON: 478 case MODE_ABORT: 479 case MODE_UNDEFINED: 480 case MODE_SYSTEM: 481 return false; 482 default: 483 return true; 484 } 485 } 486 487 struct CoreSpecific { 488 // Empty for now on the ARM 489 }; 490 491} // namespace ArmISA 492 493namespace __hash_namespace { 494 template<> 495 struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> { 496 size_t operator()(const ArmISA::ExtMachInst &emi) const { 497 return hash<uint32_t>::operator()((uint32_t)emi); 498 }; 499 }; 500} 501 502#endif 503