types.hh revision 7680:f4eda002333b
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 */ 42 43#ifndef __ARCH_ARM_TYPES_HH__ 44#define __ARCH_ARM_TYPES_HH__ 45 46#include "base/bitunion.hh" 47#include "base/hashmap.hh" 48#include "base/types.hh" 49 50namespace ArmISA 51{ 52 typedef uint32_t MachInst; 53 54 BitUnion64(ExtMachInst) 55 Bitfield<63, 56> newItstate; 56 // ITSTATE bits 57 Bitfield<55, 48> itstate; 58 Bitfield<55, 52> itstateCond; 59 Bitfield<51, 48> itstateMask; 60 61 // FPSCR fields 62 Bitfield<41, 40> fpscrStride; 63 Bitfield<39, 37> fpscrLen; 64 65 // Bitfields to select mode. 66 Bitfield<36> thumb; 67 Bitfield<35> bigThumb; 68 69 // Made up bitfields that make life easier. 70 Bitfield<33> sevenAndFour; 71 Bitfield<32> isMisc; 72 73 uint32_t instBits; 74 75 // All the different types of opcode fields. 76 Bitfield<27, 25> encoding; 77 Bitfield<25> useImm; 78 Bitfield<24, 21> opcode; 79 Bitfield<24, 20> mediaOpcode; 80 Bitfield<24> opcode24; 81 Bitfield<24, 23> opcode24_23; 82 Bitfield<23, 20> opcode23_20; 83 Bitfield<23, 21> opcode23_21; 84 Bitfield<20> opcode20; 85 Bitfield<22> opcode22; 86 Bitfield<19, 16> opcode19_16; 87 Bitfield<19> opcode19; 88 Bitfield<18> opcode18; 89 Bitfield<15, 12> opcode15_12; 90 Bitfield<15> opcode15; 91 Bitfield<7, 4> miscOpcode; 92 Bitfield<7,5> opc2; 93 Bitfield<7> opcode7; 94 Bitfield<6> opcode6; 95 Bitfield<4> opcode4; 96 97 Bitfield<31, 28> condCode; 98 Bitfield<20> sField; 99 Bitfield<19, 16> rn; 100 Bitfield<15, 12> rd; 101 Bitfield<15, 12> rt; 102 Bitfield<11, 7> shiftSize; 103 Bitfield<6, 5> shift; 104 Bitfield<3, 0> rm; 105 106 Bitfield<11, 8> rs; 107 108 SubBitUnion(puswl, 24, 20) 109 Bitfield<24> prepost; 110 Bitfield<23> up; 111 Bitfield<22> psruser; 112 Bitfield<21> writeback; 113 Bitfield<20> loadOp; 114 EndSubBitUnion(puswl) 115 116 Bitfield<24, 20> pubwl; 117 118 Bitfield<7, 0> imm; 119 120 Bitfield<11, 8> rotate; 121 122 Bitfield<11, 0> immed11_0; 123 Bitfield<7, 0> immed7_0; 124 125 Bitfield<11, 8> immedHi11_8; 126 Bitfield<3, 0> immedLo3_0; 127 128 Bitfield<15, 0> regList; 129 130 Bitfield<23, 0> offset; 131 132 Bitfield<23, 0> immed23_0; 133 134 Bitfield<11, 8> cpNum; 135 Bitfield<18, 16> fn; 136 Bitfield<14, 12> fd; 137 Bitfield<3> fpRegImm; 138 Bitfield<3, 0> fm; 139 Bitfield<2, 0> fpImm; 140 Bitfield<24, 20> punwl; 141 142 Bitfield<7, 0> m5Func; 143 144 // 16 bit thumb bitfields 145 Bitfield<15, 13> topcode15_13; 146 Bitfield<13, 11> topcode13_11; 147 Bitfield<12, 11> topcode12_11; 148 Bitfield<12, 10> topcode12_10; 149 Bitfield<11, 9> topcode11_9; 150 Bitfield<11, 8> topcode11_8; 151 Bitfield<10, 9> topcode10_9; 152 Bitfield<10, 8> topcode10_8; 153 Bitfield<9, 6> topcode9_6; 154 Bitfield<7> topcode7; 155 Bitfield<7, 6> topcode7_6; 156 Bitfield<7, 5> topcode7_5; 157 Bitfield<7, 4> topcode7_4; 158 Bitfield<3, 0> topcode3_0; 159 160 // 32 bit thumb bitfields 161 Bitfield<28, 27> htopcode12_11; 162 Bitfield<26, 25> htopcode10_9; 163 Bitfield<25> htopcode9; 164 Bitfield<25, 24> htopcode9_8; 165 Bitfield<25, 21> htopcode9_5; 166 Bitfield<25, 20> htopcode9_4; 167 Bitfield<24> htopcode8; 168 Bitfield<24, 23> htopcode8_7; 169 Bitfield<24, 22> htopcode8_6; 170 Bitfield<24, 21> htopcode8_5; 171 Bitfield<23> htopcode7; 172 Bitfield<23, 21> htopcode7_5; 173 Bitfield<22> htopcode6; 174 Bitfield<22, 21> htopcode6_5; 175 Bitfield<21, 20> htopcode5_4; 176 Bitfield<20> htopcode4; 177 178 Bitfield<19, 16> htrn; 179 Bitfield<20> hts; 180 181 Bitfield<15> ltopcode15; 182 Bitfield<11, 8> ltopcode11_8; 183 Bitfield<7, 6> ltopcode7_6; 184 Bitfield<7, 4> ltopcode7_4; 185 Bitfield<4> ltopcode4; 186 187 Bitfield<11, 8> ltrd; 188 Bitfield<11, 8> ltcoproc; 189 EndBitUnion(ExtMachInst) 190 191 // Shift types for ARM instructions 192 enum ArmShiftType { 193 LSL = 0, 194 LSR, 195 ASR, 196 ROR 197 }; 198 199 typedef uint64_t LargestRead; 200 // Need to use 64 bits to make sure that read requests get handled properly 201 202 typedef int RegContextParam; 203 typedef int RegContextVal; 204 205 //used in FP convert & round function 206 enum ConvertType{ 207 SINGLE_TO_DOUBLE, 208 SINGLE_TO_WORD, 209 SINGLE_TO_LONG, 210 211 DOUBLE_TO_SINGLE, 212 DOUBLE_TO_WORD, 213 DOUBLE_TO_LONG, 214 215 LONG_TO_SINGLE, 216 LONG_TO_DOUBLE, 217 LONG_TO_WORD, 218 LONG_TO_PS, 219 220 WORD_TO_SINGLE, 221 WORD_TO_DOUBLE, 222 WORD_TO_LONG, 223 WORD_TO_PS, 224 225 PL_TO_SINGLE, 226 PU_TO_SINGLE 227 }; 228 229 //used in FP convert & round function 230 enum RoundMode{ 231 RND_ZERO, 232 RND_DOWN, 233 RND_UP, 234 RND_NEAREST 235 }; 236 237 enum OperatingMode { 238 MODE_USER = 16, 239 MODE_FIQ = 17, 240 MODE_IRQ = 18, 241 MODE_SVC = 19, 242 MODE_MON = 22, 243 MODE_ABORT = 23, 244 MODE_UNDEFINED = 27, 245 MODE_SYSTEM = 31, 246 MODE_MAXMODE = MODE_SYSTEM 247 }; 248 249 static inline bool 250 badMode(OperatingMode mode) 251 { 252 switch (mode) { 253 case MODE_USER: 254 case MODE_FIQ: 255 case MODE_IRQ: 256 case MODE_SVC: 257 case MODE_MON: 258 case MODE_ABORT: 259 case MODE_UNDEFINED: 260 case MODE_SYSTEM: 261 return false; 262 default: 263 return true; 264 } 265 } 266 267 struct CoreSpecific { 268 // Empty for now on the ARM 269 }; 270 271} // namespace ArmISA 272 273namespace __hash_namespace { 274 template<> 275 struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> { 276 size_t operator()(const ArmISA::ExtMachInst &emi) const { 277 return hash<uint32_t>::operator()((uint32_t)emi); 278 }; 279 }; 280} 281 282#endif 283