types.hh revision 7408:ee6949c5bb5b
15217Ssaidi@eecs.umich.edu/* 213610Sgiacomo.gabrielli@arm.com * Copyright (c) 2010 ARM Limited 39920Syasuko.eckert@amd.com * All rights reserved 49428SAndreas.Sandberg@ARM.com * 59428SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 69428SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 79428SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 89428SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 99428SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 109428SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 119428SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 129428SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 139428SAndreas.Sandberg@ARM.com * 149428SAndreas.Sandberg@ARM.com * Copyright (c) 2007-2008 The Florida State University 155217Ssaidi@eecs.umich.edu * All rights reserved. 165217Ssaidi@eecs.umich.edu * 175217Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 185217Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 195217Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 205217Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 215217Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 225217Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 235217Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 245217Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 255217Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 265217Ssaidi@eecs.umich.edu * this software without specific prior written permission. 275217Ssaidi@eecs.umich.edu * 285217Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 295217Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 305217Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 315217Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 325217Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 335217Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 345217Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 355217Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 365217Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 375217Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 385217Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 395217Ssaidi@eecs.umich.edu * 405217Ssaidi@eecs.umich.edu * Authors: Stephen Hines 415217Ssaidi@eecs.umich.edu */ 425217Ssaidi@eecs.umich.edu 435217Ssaidi@eecs.umich.edu#ifndef __ARCH_ARM_TYPES_HH__ 4411793Sbrandon.potter@amd.com#define __ARCH_ARM_TYPES_HH__ 4511793Sbrandon.potter@amd.com 4613610Sgiacomo.gabrielli@arm.com#include "base/bitunion.hh" 4711627Smichael.lebeane@amd.com#include "base/types.hh" 4812334Sgabeblack@google.com 495217Ssaidi@eecs.umich.edunamespace ArmISA 506658Snate@binkert.org{ 519441SAndreas.Sandberg@ARM.com typedef uint32_t MachInst; 529441SAndreas.Sandberg@ARM.com 538232Snate@binkert.org BitUnion64(ExtMachInst) 5411627Smichael.lebeane@amd.com Bitfield<63, 56> newItstate; 5511627Smichael.lebeane@amd.com // ITSTATE bits 569441SAndreas.Sandberg@ARM.com Bitfield<55, 48> itstate; 575217Ssaidi@eecs.umich.edu Bitfield<55, 52> itstateCond; 585217Ssaidi@eecs.umich.edu Bitfield<51, 48> itstateMask; 595217Ssaidi@eecs.umich.edu 605217Ssaidi@eecs.umich.edu // FPSCR fields 615217Ssaidi@eecs.umich.edu Bitfield<41, 40> fpscrStride; 625217Ssaidi@eecs.umich.edu Bitfield<39, 37> fpscrLen; 635217Ssaidi@eecs.umich.edu 645217Ssaidi@eecs.umich.edu // Bitfields to select mode. 6513557Sgabeblack@google.com Bitfield<36> thumb; 6613557Sgabeblack@google.com Bitfield<35> bigThumb; 675217Ssaidi@eecs.umich.edu 685217Ssaidi@eecs.umich.edu // Made up bitfields that make life easier. 695217Ssaidi@eecs.umich.edu Bitfield<33> sevenAndFour; 705217Ssaidi@eecs.umich.edu Bitfield<32> isMisc; 715217Ssaidi@eecs.umich.edu 725217Ssaidi@eecs.umich.edu uint32_t instBits; 735217Ssaidi@eecs.umich.edu 7413611Sgabeblack@google.com // All the different types of opcode fields. 7513611Sgabeblack@google.com Bitfield<27, 25> encoding; 765217Ssaidi@eecs.umich.edu Bitfield<25> useImm; 775217Ssaidi@eecs.umich.edu Bitfield<24, 21> opcode; 785217Ssaidi@eecs.umich.edu Bitfield<24, 20> mediaOpcode; 795217Ssaidi@eecs.umich.edu Bitfield<24> opcode24; 8012109SRekai.GonzalezAlberquilla@arm.com Bitfield<24, 23> opcode24_23; 8112109SRekai.GonzalezAlberquilla@arm.com Bitfield<23, 20> opcode23_20; 8212109SRekai.GonzalezAlberquilla@arm.com Bitfield<23, 21> opcode23_21; 8312109SRekai.GonzalezAlberquilla@arm.com Bitfield<20> opcode20; 8412109SRekai.GonzalezAlberquilla@arm.com Bitfield<22> opcode22; 8512109SRekai.GonzalezAlberquilla@arm.com Bitfield<19, 16> opcode19_16; 8612109SRekai.GonzalezAlberquilla@arm.com Bitfield<19> opcode19; 8712109SRekai.GonzalezAlberquilla@arm.com Bitfield<18> opcode18; 8812109SRekai.GonzalezAlberquilla@arm.com Bitfield<15, 12> opcode15_12; 8912109SRekai.GonzalezAlberquilla@arm.com Bitfield<15> opcode15; 9013610Sgiacomo.gabrielli@arm.com Bitfield<7, 4> miscOpcode; 9113610Sgiacomo.gabrielli@arm.com Bitfield<7,5> opc2; 9213610Sgiacomo.gabrielli@arm.com Bitfield<7> opcode7; 9313610Sgiacomo.gabrielli@arm.com Bitfield<6> opcode6; 9413610Sgiacomo.gabrielli@arm.com Bitfield<4> opcode4; 9513610Sgiacomo.gabrielli@arm.com 9613610Sgiacomo.gabrielli@arm.com Bitfield<31, 28> condCode; 9713610Sgiacomo.gabrielli@arm.com Bitfield<20> sField; 9813610Sgiacomo.gabrielli@arm.com Bitfield<19, 16> rn; 9913610Sgiacomo.gabrielli@arm.com Bitfield<15, 12> rd; 10013610Sgiacomo.gabrielli@arm.com Bitfield<15, 12> rt; 1015217Ssaidi@eecs.umich.edu Bitfield<11, 7> shiftSize; 10213557Sgabeblack@google.com Bitfield<6, 5> shift; 10313557Sgabeblack@google.com Bitfield<3, 0> rm; 1045217Ssaidi@eecs.umich.edu 1055217Ssaidi@eecs.umich.edu Bitfield<11, 8> rs; 1065217Ssaidi@eecs.umich.edu 1075217Ssaidi@eecs.umich.edu SubBitUnion(puswl, 24, 20) 1085217Ssaidi@eecs.umich.edu Bitfield<24> prepost; 1099920Syasuko.eckert@amd.com Bitfield<23> up; 1109920Syasuko.eckert@amd.com Bitfield<22> psruser; 1119920Syasuko.eckert@amd.com Bitfield<21> writeback; 1129920Syasuko.eckert@amd.com Bitfield<20> loadOp; 1139920Syasuko.eckert@amd.com EndSubBitUnion(puswl) 1149920Syasuko.eckert@amd.com 1159920Syasuko.eckert@amd.com Bitfield<24, 20> pubwl; 1169920Syasuko.eckert@amd.com 1177720Sgblack@eecs.umich.edu Bitfield<7, 0> imm; 1187720Sgblack@eecs.umich.edu 1195712Shsul@eecs.umich.edu Bitfield<11, 8> rotate; 1205712Shsul@eecs.umich.edu 1215217Ssaidi@eecs.umich.edu Bitfield<11, 0> immed11_0; 1225217Ssaidi@eecs.umich.edu Bitfield<7, 0> immed7_0; 1235714Shsul@eecs.umich.edu 12411005Sandreas.sandberg@arm.com Bitfield<11, 8> immedHi11_8; 12511005Sandreas.sandberg@arm.com Bitfield<3, 0> immedLo3_0; 12611005Sandreas.sandberg@arm.com 1275714Shsul@eecs.umich.edu Bitfield<15, 0> regList; 1285714Shsul@eecs.umich.edu 1295714Shsul@eecs.umich.edu Bitfield<23, 0> offset; 1305217Ssaidi@eecs.umich.edu 1319428SAndreas.Sandberg@ARM.com Bitfield<23, 0> immed23_0; 1329428SAndreas.Sandberg@ARM.com 13311627Smichael.lebeane@amd.com Bitfield<11, 8> cpNum; 13411627Smichael.lebeane@amd.com Bitfield<18, 16> fn; 13511627Smichael.lebeane@amd.com Bitfield<14, 12> fd; 13611627Smichael.lebeane@amd.com Bitfield<3> fpRegImm; 13711627Smichael.lebeane@amd.com Bitfield<3, 0> fm; 13811627Smichael.lebeane@amd.com Bitfield<2, 0> fpImm; 13911627Smichael.lebeane@amd.com Bitfield<24, 20> punwl; 14011627Smichael.lebeane@amd.com 14111627Smichael.lebeane@amd.com Bitfield<7, 0> m5Func; 14211627Smichael.lebeane@amd.com 14311627Smichael.lebeane@amd.com // 16 bit thumb bitfields 14411627Smichael.lebeane@amd.com Bitfield<15, 13> topcode15_13; 14511627Smichael.lebeane@amd.com Bitfield<13, 11> topcode13_11; 14611627Smichael.lebeane@amd.com Bitfield<12, 11> topcode12_11; 14711627Smichael.lebeane@amd.com Bitfield<12, 10> topcode12_10; 14811627Smichael.lebeane@amd.com Bitfield<11, 9> topcode11_9; 14911627Smichael.lebeane@amd.com Bitfield<11, 8> topcode11_8; 15011627Smichael.lebeane@amd.com Bitfield<10, 9> topcode10_9; 15111627Smichael.lebeane@amd.com Bitfield<10, 8> topcode10_8; 15211627Smichael.lebeane@amd.com Bitfield<9, 6> topcode9_6; 15311627Smichael.lebeane@amd.com Bitfield<7> topcode7; 15411627Smichael.lebeane@amd.com Bitfield<7, 6> topcode7_6; 15511627Smichael.lebeane@amd.com Bitfield<7, 5> topcode7_5; 15611627Smichael.lebeane@amd.com Bitfield<7, 4> topcode7_4; 15711627Smichael.lebeane@amd.com Bitfield<3, 0> topcode3_0; 15811627Smichael.lebeane@amd.com 15911627Smichael.lebeane@amd.com // 32 bit thumb bitfields 16011627Smichael.lebeane@amd.com Bitfield<28, 27> htopcode12_11; 16111627Smichael.lebeane@amd.com Bitfield<26, 25> htopcode10_9; 16211627Smichael.lebeane@amd.com Bitfield<25> htopcode9; 16311627Smichael.lebeane@amd.com Bitfield<25, 24> htopcode9_8; 16411627Smichael.lebeane@amd.com Bitfield<25, 21> htopcode9_5; 16511627Smichael.lebeane@amd.com Bitfield<25, 20> htopcode9_4; 16610905Sandreas.sandberg@arm.com Bitfield<24> htopcode8; 1679428SAndreas.Sandberg@ARM.com Bitfield<24, 23> htopcode8_7; 1689428SAndreas.Sandberg@ARM.com Bitfield<24, 22> htopcode8_6; 1699428SAndreas.Sandberg@ARM.com Bitfield<24, 21> htopcode8_5; 17013557Sgabeblack@google.com Bitfield<23> htopcode7; 1719428SAndreas.Sandberg@ARM.com Bitfield<23, 21> htopcode7_5; 17213611Sgabeblack@google.com Bitfield<22> htopcode6; 1739428SAndreas.Sandberg@ARM.com Bitfield<22, 21> htopcode6_5; 1749428SAndreas.Sandberg@ARM.com Bitfield<21, 20> htopcode5_4; 17510905Sandreas.sandberg@arm.com Bitfield<20> htopcode4; 1769428SAndreas.Sandberg@ARM.com 17712109SRekai.GonzalezAlberquilla@arm.com Bitfield<19, 16> htrn; 17812109SRekai.GonzalezAlberquilla@arm.com Bitfield<20> hts; 17912109SRekai.GonzalezAlberquilla@arm.com 18012109SRekai.GonzalezAlberquilla@arm.com Bitfield<15> ltopcode15; 18112109SRekai.GonzalezAlberquilla@arm.com Bitfield<11, 8> ltopcode11_8; 18212109SRekai.GonzalezAlberquilla@arm.com Bitfield<7, 6> ltopcode7_6; 18313610Sgiacomo.gabrielli@arm.com Bitfield<7, 4> ltopcode7_4; 18413610Sgiacomo.gabrielli@arm.com Bitfield<4> ltopcode4; 18513610Sgiacomo.gabrielli@arm.com 18613610Sgiacomo.gabrielli@arm.com Bitfield<11, 8> ltrd; 18713610Sgiacomo.gabrielli@arm.com Bitfield<11, 8> ltcoproc; 18813610Sgiacomo.gabrielli@arm.com EndBitUnion(ExtMachInst) 18913557Sgabeblack@google.com 1909428SAndreas.Sandberg@ARM.com // Shift types for ARM instructions 1919428SAndreas.Sandberg@ARM.com enum ArmShiftType { 1929428SAndreas.Sandberg@ARM.com LSL = 0, 1939428SAndreas.Sandberg@ARM.com LSR, 1949920Syasuko.eckert@amd.com ASR, 1959920Syasuko.eckert@amd.com ROR 1969920Syasuko.eckert@amd.com }; 1979920Syasuko.eckert@amd.com 1989920Syasuko.eckert@amd.com typedef uint64_t LargestRead; 1999920Syasuko.eckert@amd.com // Need to use 64 bits to make sure that read requests get handled properly 2009920Syasuko.eckert@amd.com 20110905Sandreas.sandberg@arm.com typedef int RegContextParam; 2029428SAndreas.Sandberg@ARM.com typedef int RegContextVal; 2039428SAndreas.Sandberg@ARM.com 2049428SAndreas.Sandberg@ARM.com //used in FP convert & round function 2059428SAndreas.Sandberg@ARM.com enum ConvertType{ 2069428SAndreas.Sandberg@ARM.com SINGLE_TO_DOUBLE, 20710905Sandreas.sandberg@arm.com SINGLE_TO_WORD, 2089428SAndreas.Sandberg@ARM.com SINGLE_TO_LONG, 2099428SAndreas.Sandberg@ARM.com 2109428SAndreas.Sandberg@ARM.com DOUBLE_TO_SINGLE, 21113557Sgabeblack@google.com DOUBLE_TO_WORD, 2129428SAndreas.Sandberg@ARM.com DOUBLE_TO_LONG, 2139428SAndreas.Sandberg@ARM.com 21410905Sandreas.sandberg@arm.com LONG_TO_SINGLE, 2159428SAndreas.Sandberg@ARM.com LONG_TO_DOUBLE, 21613611Sgabeblack@google.com LONG_TO_WORD, 2179428SAndreas.Sandberg@ARM.com LONG_TO_PS, 21812109SRekai.GonzalezAlberquilla@arm.com 21912109SRekai.GonzalezAlberquilla@arm.com WORD_TO_SINGLE, 22012109SRekai.GonzalezAlberquilla@arm.com WORD_TO_DOUBLE, 22112109SRekai.GonzalezAlberquilla@arm.com WORD_TO_LONG, 22212109SRekai.GonzalezAlberquilla@arm.com WORD_TO_PS, 22312109SRekai.GonzalezAlberquilla@arm.com 22413610Sgiacomo.gabrielli@arm.com PL_TO_SINGLE, 22513610Sgiacomo.gabrielli@arm.com PU_TO_SINGLE 22613610Sgiacomo.gabrielli@arm.com }; 22713610Sgiacomo.gabrielli@arm.com 22813610Sgiacomo.gabrielli@arm.com //used in FP convert & round function 22913610Sgiacomo.gabrielli@arm.com enum RoundMode{ 23013557Sgabeblack@google.com RND_ZERO, 2319428SAndreas.Sandberg@ARM.com RND_DOWN, 2329428SAndreas.Sandberg@ARM.com RND_UP, 2339428SAndreas.Sandberg@ARM.com RND_NEAREST 2349428SAndreas.Sandberg@ARM.com }; 2359920Syasuko.eckert@amd.com 2369920Syasuko.eckert@amd.com enum OperatingMode { 2379920Syasuko.eckert@amd.com MODE_USER = 16, 2389920Syasuko.eckert@amd.com MODE_FIQ = 17, 2399920Syasuko.eckert@amd.com MODE_IRQ = 18, 2409920Syasuko.eckert@amd.com MODE_SVC = 19, 2419920Syasuko.eckert@amd.com MODE_MON = 22, 2429428SAndreas.Sandberg@ARM.com MODE_ABORT = 23, 24310905Sandreas.sandberg@arm.com MODE_UNDEFINED = 27, 2449428SAndreas.Sandberg@ARM.com MODE_SYSTEM = 31 2459428SAndreas.Sandberg@ARM.com }; 2469428SAndreas.Sandberg@ARM.com 2479428SAndreas.Sandberg@ARM.com static inline bool 2489441SAndreas.Sandberg@ARM.com badMode(OperatingMode mode) 2499441SAndreas.Sandberg@ARM.com { 2509441SAndreas.Sandberg@ARM.com switch (mode) { 2519441SAndreas.Sandberg@ARM.com case MODE_USER: 2529441SAndreas.Sandberg@ARM.com case MODE_FIQ: 2539441SAndreas.Sandberg@ARM.com case MODE_IRQ: 2549441SAndreas.Sandberg@ARM.com case MODE_SVC: 2559441SAndreas.Sandberg@ARM.com case MODE_MON: 2569441SAndreas.Sandberg@ARM.com case MODE_ABORT: 2579441SAndreas.Sandberg@ARM.com case MODE_UNDEFINED: 2589441SAndreas.Sandberg@ARM.com case MODE_SYSTEM: 2599441SAndreas.Sandberg@ARM.com return false; 2609441SAndreas.Sandberg@ARM.com default: 2619441SAndreas.Sandberg@ARM.com return true; 2629441SAndreas.Sandberg@ARM.com } 2639441SAndreas.Sandberg@ARM.com } 2649441SAndreas.Sandberg@ARM.com 2659441SAndreas.Sandberg@ARM.com struct CoreSpecific { 2669441SAndreas.Sandberg@ARM.com // Empty for now on the ARM 2679441SAndreas.Sandberg@ARM.com }; 2689441SAndreas.Sandberg@ARM.com 2699441SAndreas.Sandberg@ARM.com} // namespace ArmISA 2709441SAndreas.Sandberg@ARM.com 2719441SAndreas.Sandberg@ARM.com#endif 2729441SAndreas.Sandberg@ARM.com