types.hh revision 7376:3b781776b2d9
16407SN/A/* 27414SN/A * Copyright (c) 2010 ARM Limited 37414SN/A * All rights reserved 47414SN/A * 57414SN/A * The license below extends only to copyright in the software and shall 67414SN/A * not be construed as granting a license to any other intellectual 77414SN/A * property including but not limited to intellectual property relating 87414SN/A * to a hardware implementation of the functionality of the software 97414SN/A * licensed hereunder. You may use the software subject to the license 107414SN/A * terms below provided that you ensure that this notice is replicated 117414SN/A * unmodified and in its entirety in all distributions of the software, 127414SN/A * modified or unmodified, in source code or in binary form. 137414SN/A * 146407SN/A * Copyright (c) 2007-2008 The Florida State University 156407SN/A * All rights reserved. 166407SN/A * 176407SN/A * Redistribution and use in source and binary forms, with or without 186407SN/A * modification, are permitted provided that the following conditions are 196407SN/A * met: redistributions of source code must retain the above copyright 206407SN/A * notice, this list of conditions and the following disclaimer; 216407SN/A * redistributions in binary form must reproduce the above copyright 226407SN/A * notice, this list of conditions and the following disclaimer in the 236407SN/A * documentation and/or other materials provided with the distribution; 246407SN/A * neither the name of the copyright holders nor the names of its 256407SN/A * contributors may be used to endorse or promote products derived from 266407SN/A * this software without specific prior written permission. 276407SN/A * 286407SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296407SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306407SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316407SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326407SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336407SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346407SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356407SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366407SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376407SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386407SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396407SN/A * 406407SN/A * Authors: Stephen Hines 416407SN/A */ 426407SN/A 436407SN/A#ifndef __ARCH_ARM_TYPES_HH__ 446407SN/A#define __ARCH_ARM_TYPES_HH__ 456407SN/A 466407SN/A#include "base/bitunion.hh" 476407SN/A#include "base/types.hh" 486407SN/A 496407SN/Anamespace ArmISA 506407SN/A{ 518113Sgblack@eecs.umich.edu typedef uint32_t MachInst; 526407SN/A 536407SN/A BitUnion64(ExtMachInst) 546407SN/A // FPSCR fields 556407SN/A Bitfield<41, 40> fpscrStride; 566407SN/A Bitfield<39, 37> fpscrLen; 576407SN/A 586407SN/A // Bitfields to select mode. 596407SN/A Bitfield<36> thumb; 606407SN/A Bitfield<35> bigThumb; 616407SN/A 626407SN/A // Made up bitfields that make life easier. 636407SN/A Bitfield<33> sevenAndFour; 646407SN/A Bitfield<32> isMisc; 656407SN/A 666407SN/A uint32_t instBits; 676407SN/A 686407SN/A // All the different types of opcode fields. 696407SN/A Bitfield<27, 25> encoding; 706407SN/A Bitfield<25> useImm; 716407SN/A Bitfield<24, 21> opcode; 726407SN/A Bitfield<24, 20> mediaOpcode; 736407SN/A Bitfield<24> opcode24; 746407SN/A Bitfield<24, 23> opcode24_23; 756407SN/A Bitfield<23, 20> opcode23_20; 767414SN/A Bitfield<23, 21> opcode23_21; 777414SN/A Bitfield<20> opcode20; 786407SN/A Bitfield<22> opcode22; 796407SN/A Bitfield<19, 16> opcode19_16; 807414SN/A Bitfield<19> opcode19; 816407SN/A Bitfield<18> opcode18; 826407SN/A Bitfield<15, 12> opcode15_12; 836407SN/A Bitfield<15> opcode15; 846407SN/A Bitfield<7, 4> miscOpcode; 856407SN/A Bitfield<7,5> opc2; 866407SN/A Bitfield<7> opcode7; 877414SN/A Bitfield<6> opcode6; 886407SN/A Bitfield<4> opcode4; 896407SN/A 908108SN/A Bitfield<31, 28> condCode; 918108SN/A Bitfield<20> sField; 926407SN/A Bitfield<19, 16> rn; 938108SN/A Bitfield<15, 12> rd; 946407SN/A Bitfield<15, 12> rt; 956407SN/A Bitfield<11, 7> shiftSize; 968108SN/A Bitfield<6, 5> shift; 978108SN/A Bitfield<3, 0> rm; 986407SN/A 998108SN/A Bitfield<11, 8> rs; 1006407SN/A 1016407SN/A SubBitUnion(puswl, 24, 20) 1026407SN/A Bitfield<24> prepost; 1036407SN/A Bitfield<23> up; 1046407SN/A Bitfield<22> psruser; 1056407SN/A Bitfield<21> writeback; 1066407SN/A Bitfield<20> loadOp; 1076407SN/A EndSubBitUnion(puswl) 108 109 Bitfield<24, 20> pubwl; 110 111 Bitfield<7, 0> imm; 112 113 Bitfield<11, 8> rotate; 114 115 Bitfield<11, 0> immed11_0; 116 Bitfield<7, 0> immed7_0; 117 118 Bitfield<11, 8> immedHi11_8; 119 Bitfield<3, 0> immedLo3_0; 120 121 Bitfield<15, 0> regList; 122 123 Bitfield<23, 0> offset; 124 125 Bitfield<23, 0> immed23_0; 126 127 Bitfield<11, 8> cpNum; 128 Bitfield<18, 16> fn; 129 Bitfield<14, 12> fd; 130 Bitfield<3> fpRegImm; 131 Bitfield<3, 0> fm; 132 Bitfield<2, 0> fpImm; 133 Bitfield<24, 20> punwl; 134 135 Bitfield<7, 0> m5Func; 136 137 // 16 bit thumb bitfields 138 Bitfield<15, 13> topcode15_13; 139 Bitfield<13, 11> topcode13_11; 140 Bitfield<12, 11> topcode12_11; 141 Bitfield<12, 10> topcode12_10; 142 Bitfield<11, 9> topcode11_9; 143 Bitfield<11, 8> topcode11_8; 144 Bitfield<10, 9> topcode10_9; 145 Bitfield<10, 8> topcode10_8; 146 Bitfield<9, 6> topcode9_6; 147 Bitfield<7> topcode7; 148 Bitfield<7, 6> topcode7_6; 149 Bitfield<7, 5> topcode7_5; 150 Bitfield<7, 4> topcode7_4; 151 Bitfield<3, 0> topcode3_0; 152 153 // 32 bit thumb bitfields 154 Bitfield<28, 27> htopcode12_11; 155 Bitfield<26, 25> htopcode10_9; 156 Bitfield<25> htopcode9; 157 Bitfield<25, 24> htopcode9_8; 158 Bitfield<25, 21> htopcode9_5; 159 Bitfield<25, 20> htopcode9_4; 160 Bitfield<24> htopcode8; 161 Bitfield<24, 23> htopcode8_7; 162 Bitfield<24, 22> htopcode8_6; 163 Bitfield<24, 21> htopcode8_5; 164 Bitfield<23> htopcode7; 165 Bitfield<23, 21> htopcode7_5; 166 Bitfield<22> htopcode6; 167 Bitfield<22, 21> htopcode6_5; 168 Bitfield<21, 20> htopcode5_4; 169 Bitfield<20> htopcode4; 170 171 Bitfield<19, 16> htrn; 172 Bitfield<20> hts; 173 174 Bitfield<15> ltopcode15; 175 Bitfield<11, 8> ltopcode11_8; 176 Bitfield<7, 6> ltopcode7_6; 177 Bitfield<7, 4> ltopcode7_4; 178 Bitfield<4> ltopcode4; 179 180 Bitfield<11, 8> ltrd; 181 Bitfield<11, 8> ltcoproc; 182 EndBitUnion(ExtMachInst) 183 184 // Shift types for ARM instructions 185 enum ArmShiftType { 186 LSL = 0, 187 LSR, 188 ASR, 189 ROR 190 }; 191 192 typedef uint64_t LargestRead; 193 // Need to use 64 bits to make sure that read requests get handled properly 194 195 typedef int RegContextParam; 196 typedef int RegContextVal; 197 198 //used in FP convert & round function 199 enum ConvertType{ 200 SINGLE_TO_DOUBLE, 201 SINGLE_TO_WORD, 202 SINGLE_TO_LONG, 203 204 DOUBLE_TO_SINGLE, 205 DOUBLE_TO_WORD, 206 DOUBLE_TO_LONG, 207 208 LONG_TO_SINGLE, 209 LONG_TO_DOUBLE, 210 LONG_TO_WORD, 211 LONG_TO_PS, 212 213 WORD_TO_SINGLE, 214 WORD_TO_DOUBLE, 215 WORD_TO_LONG, 216 WORD_TO_PS, 217 218 PL_TO_SINGLE, 219 PU_TO_SINGLE 220 }; 221 222 //used in FP convert & round function 223 enum RoundMode{ 224 RND_ZERO, 225 RND_DOWN, 226 RND_UP, 227 RND_NEAREST 228 }; 229 230 enum OperatingMode { 231 MODE_USER = 16, 232 MODE_FIQ = 17, 233 MODE_IRQ = 18, 234 MODE_SVC = 19, 235 MODE_MON = 22, 236 MODE_ABORT = 23, 237 MODE_UNDEFINED = 27, 238 MODE_SYSTEM = 31 239 }; 240 241 static inline bool 242 badMode(OperatingMode mode) 243 { 244 switch (mode) { 245 case MODE_USER: 246 case MODE_FIQ: 247 case MODE_IRQ: 248 case MODE_SVC: 249 case MODE_MON: 250 case MODE_ABORT: 251 case MODE_UNDEFINED: 252 case MODE_SYSTEM: 253 return false; 254 default: 255 return true; 256 } 257 } 258 259 struct CoreSpecific { 260 // Empty for now on the ARM 261 }; 262 263} // namespace ArmISA 264 265#endif 266