types.hh revision 7103:844dbc22e3cb
12810SN/A/* 22810SN/A * Copyright (c) 2010 ARM Limited 32810SN/A * All rights reserved 42810SN/A * 52810SN/A * The license below extends only to copyright in the software and shall 62810SN/A * not be construed as granting a license to any other intellectual 72810SN/A * property including but not limited to intellectual property relating 82810SN/A * to a hardware implementation of the functionality of the software 92810SN/A * licensed hereunder. You may use the software subject to the license 102810SN/A * terms below provided that you ensure that this notice is replicated 112810SN/A * unmodified and in its entirety in all distributions of the software, 122810SN/A * modified or unmodified, in source code or in binary form. 132810SN/A * 142810SN/A * Copyright (c) 2007-2008 The Florida State University 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 363348SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 373348SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 388232Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 395338Sstever@gmail.com * 405338Sstever@gmail.com * Authors: Stephen Hines 418786Sgblack@eecs.umich.edu */ 422810SN/A 432810SN/A#ifndef __ARCH_ARM_TYPES_HH__ 442810SN/A#define __ARCH_ARM_TYPES_HH__ 454965SN/A 466122SSteve.Reinhardt@amd.com#include "base/bitunion.hh" 475314SN/A#include "base/types.hh" 488736Sandreas.hansson@arm.com 492810SN/Anamespace ArmISA 504475SN/A{ 514475SN/A typedef uint32_t MachInst; 524475SN/A 535034SN/A BitUnion64(ExtMachInst) 545034SN/A // Bitfields to select mode. 555314SN/A Bitfield<36> thumb; 565314SN/A Bitfield<35> bigThumb; 574628SN/A 585034SN/A // Made up bitfields that make life easier. 595034SN/A Bitfield<33> sevenAndFour; 605034SN/A Bitfield<32> isMisc; 616122SSteve.Reinhardt@amd.com 628134SAli.Saidi@ARM.com uint32_t instBits; 634626SN/A 644626SN/A // All the different types of opcode fields. 655034SN/A Bitfield<27, 25> encoding; 666122SSteve.Reinhardt@amd.com Bitfield<25> useImm; 676978SLisa.Hsu@amd.com Bitfield<24, 21> opcode; 688833Sdam.sunwoo@arm.com Bitfield<24, 20> mediaOpcode; 694458SN/A Bitfield<24> opcode24; 702810SN/A Bitfield<23, 20> opcode23_20; 712810SN/A Bitfield<23, 21> opcode23_21; 725314SN/A Bitfield<20> opcode20; 735314SN/A Bitfield<22> opcode22; 745314SN/A Bitfield<19> opcode19; 755314SN/A Bitfield<18> opcode18; 765314SN/A Bitfield<15, 12> opcode15_12; 775314SN/A Bitfield<15> opcode15; 785314SN/A Bitfield<7, 4> miscOpcode; 795314SN/A Bitfield<7,5> opc2; 805314SN/A Bitfield<7> opcode7; 815314SN/A Bitfield<4> opcode4; 825314SN/A 836227Snate@binkert.org Bitfield<31, 28> condCode; 846227Snate@binkert.org Bitfield<20> sField; 852810SN/A Bitfield<19, 16> rn; 862810SN/A Bitfield<15, 12> rd; 872810SN/A Bitfield<11, 7> shiftSize; 882810SN/A Bitfield<6, 5> shift; 893606SN/A Bitfield<3, 0> rm; 904458SN/A 914458SN/A Bitfield<11, 8> rs; 923013SN/A 933236SN/A SubBitUnion(puswl, 24, 20) 944458SN/A Bitfield<24> prepost; 954458SN/A Bitfield<23> up; 964458SN/A Bitfield<22> psruser; 973246SN/A Bitfield<21> writeback; 983309SN/A Bitfield<20> loadOp; 993013SN/A EndSubBitUnion(puswl) 1002810SN/A 1012810SN/A Bitfield<24, 20> pubwl; 1023013SN/A 1033013SN/A Bitfield<7, 0> imm; 1042810SN/A 1053013SN/A Bitfield<11, 8> rotate; 1063013SN/A 1072810SN/A Bitfield<11, 0> immed11_0; 1082810SN/A Bitfield<7, 0> immed7_0; 1092810SN/A 1102810SN/A Bitfield<11, 8> immedHi11_8; 1112810SN/A Bitfield<3, 0> immedLo3_0; 1123013SN/A 1133013SN/A Bitfield<15, 0> regList; 1143013SN/A 1152897SN/A Bitfield<23, 0> offset; 1162897SN/A 1173013SN/A Bitfield<23, 0> immed23_0; 1182897SN/A 1194666SN/A Bitfield<11, 8> cpNum; 1204666SN/A Bitfield<18, 16> fn; 1218708Sandreas.hansson@arm.com Bitfield<14, 12> fd; 1222897SN/A Bitfield<3> fpRegImm; 1232810SN/A Bitfield<3, 0> fm; 1242810SN/A Bitfield<2, 0> fpImm; 1252844SN/A Bitfield<24, 20> punwl; 1262810SN/A 1272858SN/A Bitfield<7, 0> m5Func; 1282858SN/A 1292858SN/A // 16 bit thumb bitfields 1302858SN/A Bitfield<15, 13> topcode15_13; 1318711Sandreas.hansson@arm.com Bitfield<13, 11> topcode13_11; 1322858SN/A Bitfield<12, 11> topcode12_11; 1332858SN/A Bitfield<12, 10> topcode12_10; 1344628SN/A Bitfield<11, 9> topcode11_9; 1352858SN/A Bitfield<11, 8> topcode11_8; 1362810SN/A Bitfield<10, 9> topcode10_9; 1372810SN/A Bitfield<10, 8> topcode10_8; 1382810SN/A Bitfield<9, 6> topcode9_6; 1392810SN/A Bitfield<7> topcode7; 1402810SN/A Bitfield<7, 6> topcode7_6; 1414022SN/A Bitfield<7, 5> topcode7_5; 1424022SN/A Bitfield<7, 4> topcode7_4; 1434022SN/A Bitfield<3, 0> topcode3_0; 1442810SN/A EndBitUnion(ExtMachInst) 1452810SN/A 1468833Sdam.sunwoo@arm.com // Shift types for ARM instructions 1472810SN/A enum ArmShiftType { 1482810SN/A LSL = 0, 1492810SN/A LSR, 1502810SN/A ASR, 1518833Sdam.sunwoo@arm.com ROR 1528833Sdam.sunwoo@arm.com }; 1538833Sdam.sunwoo@arm.com 1542810SN/A typedef uint64_t LargestRead; 1552810SN/A // Need to use 64 bits to make sure that read requests get handled properly 1564871SN/A 1574871SN/A typedef int RegContextParam; 1584871SN/A typedef int RegContextVal; 1594871SN/A 1604871SN/A //used in FP convert & round function 1614871SN/A enum ConvertType{ 1624871SN/A SINGLE_TO_DOUBLE, 1634871SN/A SINGLE_TO_WORD, 1644871SN/A SINGLE_TO_LONG, 1654871SN/A 1662810SN/A DOUBLE_TO_SINGLE, 1672810SN/A DOUBLE_TO_WORD, 1682810SN/A DOUBLE_TO_LONG, 1698833Sdam.sunwoo@arm.com 1702810SN/A LONG_TO_SINGLE, 1714871SN/A LONG_TO_DOUBLE, 1728833Sdam.sunwoo@arm.com LONG_TO_WORD, 1738833Sdam.sunwoo@arm.com LONG_TO_PS, 1748833Sdam.sunwoo@arm.com 1752810SN/A WORD_TO_SINGLE, 1762810SN/A WORD_TO_DOUBLE, 1772810SN/A WORD_TO_LONG, 1782810SN/A WORD_TO_PS, 1798833Sdam.sunwoo@arm.com 1802810SN/A PL_TO_SINGLE, 1814871SN/A PU_TO_SINGLE 1828833Sdam.sunwoo@arm.com }; 1838833Sdam.sunwoo@arm.com 1848833Sdam.sunwoo@arm.com //used in FP convert & round function 1852810SN/A enum RoundMode{ 1862810SN/A RND_ZERO, 1874022SN/A RND_DOWN, 1884022SN/A RND_UP, 1894022SN/A RND_NEAREST 1902810SN/A }; 1912810SN/A 1928833Sdam.sunwoo@arm.com enum OperatingMode { 1932810SN/A MODE_USER = 16, 1942810SN/A MODE_FIQ = 17, 1952810SN/A MODE_IRQ = 18, 1962810SN/A MODE_SVC = 19, 1978833Sdam.sunwoo@arm.com MODE_MON = 22, 1988833Sdam.sunwoo@arm.com MODE_ABORT = 23, 1998833Sdam.sunwoo@arm.com MODE_UNDEFINED = 27, 2002810SN/A MODE_SYSTEM = 31 2012810SN/A }; 2022810SN/A 2032810SN/A struct CoreSpecific { 2042810SN/A // Empty for now on the ARM 2058833Sdam.sunwoo@arm.com }; 2062810SN/A 2074871SN/A} // namespace ArmISA 2088833Sdam.sunwoo@arm.com 2098833Sdam.sunwoo@arm.com#endif 2108833Sdam.sunwoo@arm.com