types.hh revision 7098 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#ifndef __ARCH_ARM_TYPES_HH__
44#define __ARCH_ARM_TYPES_HH__
45
46#include "base/bitunion.hh"
47#include "base/types.hh"
48
49namespace ArmISA
50{
51    typedef uint32_t MachInst;
52
53    BitUnion64(ExtMachInst)
54        // Bitfields to select mode.
55        Bitfield<36>     thumb;
56        Bitfield<35>     bigThumb;
57
58        // Made up bitfields that make life easier.
59        Bitfield<33>     sevenAndFour;
60        Bitfield<32>     isMisc;
61
62        uint32_t         instBits;
63
64        // All the different types of opcode fields.
65        Bitfield<27, 25> encoding;
66        Bitfield<25>     useImm;
67        Bitfield<24, 21> opcode;
68        Bitfield<24, 20> mediaOpcode;
69        Bitfield<24>     opcode24;
70        Bitfield<23, 20> opcode23_20;
71        Bitfield<23, 21> opcode23_21;
72        Bitfield<20>     opcode20;
73        Bitfield<22>     opcode22;
74        Bitfield<19>     opcode19;
75        Bitfield<18>     opcode18;
76        Bitfield<15, 12> opcode15_12;
77        Bitfield<15>     opcode15;
78        Bitfield<7,  4>  miscOpcode;
79        Bitfield<7,5>    opc2;
80        Bitfield<7>      opcode7;
81        Bitfield<4>      opcode4;
82
83        Bitfield<31, 28> condCode;
84        Bitfield<20>     sField;
85        Bitfield<19, 16> rn;
86        Bitfield<15, 12> rd;
87        Bitfield<11, 7>  shiftSize;
88        Bitfield<6,  5>  shift;
89        Bitfield<3,  0>  rm;
90
91        Bitfield<11, 8>  rs;
92
93        SubBitUnion(puswl, 24, 20)
94            Bitfield<24> prepost;
95            Bitfield<23> up;
96            Bitfield<22> psruser;
97            Bitfield<21> writeback;
98            Bitfield<20> loadOp;
99        EndSubBitUnion(puswl)
100
101        Bitfield<24, 20> pubwl;
102
103        Bitfield<7, 0> imm;
104
105        Bitfield<11, 8>  rotate;
106
107        Bitfield<11, 0>  immed11_0;
108        Bitfield<7,  0>  immed7_0;
109
110        Bitfield<11, 8>  immedHi11_8;
111        Bitfield<3,  0>  immedLo3_0;
112
113        Bitfield<15, 0>  regList;
114
115        Bitfield<23, 0>  offset;
116
117        Bitfield<23, 0>  immed23_0;
118
119        Bitfield<11, 8>  cpNum;
120        Bitfield<18, 16> fn;
121        Bitfield<14, 12> fd;
122        Bitfield<3>      fpRegImm;
123        Bitfield<3,  0>  fm;
124        Bitfield<2,  0>  fpImm;
125        Bitfield<24, 20> punwl;
126
127        Bitfield<7,  0>  m5Func;
128    EndBitUnion(ExtMachInst)
129
130    // Shift types for ARM instructions
131    enum ArmShiftType {
132        LSL = 0,
133        LSR,
134        ASR,
135        ROR
136    };
137
138    typedef uint64_t LargestRead;
139    // Need to use 64 bits to make sure that read requests get handled properly
140
141    typedef int RegContextParam;
142    typedef int RegContextVal;
143
144    //used in FP convert & round function
145    enum ConvertType{
146        SINGLE_TO_DOUBLE,
147        SINGLE_TO_WORD,
148        SINGLE_TO_LONG,
149
150        DOUBLE_TO_SINGLE,
151        DOUBLE_TO_WORD,
152        DOUBLE_TO_LONG,
153
154        LONG_TO_SINGLE,
155        LONG_TO_DOUBLE,
156        LONG_TO_WORD,
157        LONG_TO_PS,
158
159        WORD_TO_SINGLE,
160        WORD_TO_DOUBLE,
161        WORD_TO_LONG,
162        WORD_TO_PS,
163
164        PL_TO_SINGLE,
165        PU_TO_SINGLE
166    };
167
168    //used in FP convert & round function
169    enum RoundMode{
170        RND_ZERO,
171        RND_DOWN,
172        RND_UP,
173        RND_NEAREST
174    };
175
176    enum OperatingMode {
177        MODE_USER = 16,
178        MODE_FIQ = 17,
179        MODE_IRQ = 18,
180        MODE_SVC = 19,
181        MODE_MON = 22,
182        MODE_ABORT = 23,
183        MODE_UNDEFINED = 27,
184        MODE_SYSTEM = 31
185    };
186
187    struct CoreSpecific {
188        // Empty for now on the ARM
189    };
190
191} // namespace ArmISA
192
193#endif
194