types.hh revision 7097
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 */ 42 43#ifndef __ARCH_ARM_TYPES_HH__ 44#define __ARCH_ARM_TYPES_HH__ 45 46#include "base/bitunion.hh" 47#include "base/types.hh" 48 49namespace ArmISA 50{ 51 typedef uint32_t MachInst; 52 53 BitUnion64(ExtMachInst) 54 // Bitfields to select mode. 55 Bitfield<36> thumb; 56 Bitfield<35> bigThumb; 57 58 // Made up bitfields that make life easier. 59 Bitfield<33> sevenAndFour; 60 Bitfield<32> isMisc; 61 62 // All the different types of opcode fields. 63 Bitfield<27, 25> encoding; 64 Bitfield<25> useImm; 65 Bitfield<24, 21> opcode; 66 Bitfield<24, 20> mediaOpcode; 67 Bitfield<24> opcode24; 68 Bitfield<23, 20> opcode23_20; 69 Bitfield<23, 21> opcode23_21; 70 Bitfield<20> opcode20; 71 Bitfield<22> opcode22; 72 Bitfield<19> opcode19; 73 Bitfield<18> opcode18; 74 Bitfield<15, 12> opcode15_12; 75 Bitfield<15> opcode15; 76 Bitfield<7, 4> miscOpcode; 77 Bitfield<7,5> opc2; 78 Bitfield<7> opcode7; 79 Bitfield<4> opcode4; 80 81 Bitfield<31, 28> condCode; 82 Bitfield<20> sField; 83 Bitfield<19, 16> rn; 84 Bitfield<15, 12> rd; 85 Bitfield<11, 7> shiftSize; 86 Bitfield<6, 5> shift; 87 Bitfield<3, 0> rm; 88 89 Bitfield<11, 8> rs; 90 91 SubBitUnion(puswl, 24, 20) 92 Bitfield<24> prepost; 93 Bitfield<23> up; 94 Bitfield<22> psruser; 95 Bitfield<21> writeback; 96 Bitfield<20> loadOp; 97 EndSubBitUnion(puswl) 98 99 Bitfield<24, 20> pubwl; 100 101 Bitfield<7, 0> imm; 102 103 Bitfield<11, 8> rotate; 104 105 Bitfield<11, 0> immed11_0; 106 Bitfield<7, 0> immed7_0; 107 108 Bitfield<11, 8> immedHi11_8; 109 Bitfield<3, 0> immedLo3_0; 110 111 Bitfield<15, 0> regList; 112 113 Bitfield<23, 0> offset; 114 115 Bitfield<23, 0> immed23_0; 116 117 Bitfield<11, 8> cpNum; 118 Bitfield<18, 16> fn; 119 Bitfield<14, 12> fd; 120 Bitfield<3> fpRegImm; 121 Bitfield<3, 0> fm; 122 Bitfield<2, 0> fpImm; 123 Bitfield<24, 20> punwl; 124 125 Bitfield<7, 0> m5Func; 126 EndBitUnion(ExtMachInst) 127 128 // Shift types for ARM instructions 129 enum ArmShiftType { 130 LSL = 0, 131 LSR, 132 ASR, 133 ROR 134 }; 135 136 typedef uint64_t LargestRead; 137 // Need to use 64 bits to make sure that read requests get handled properly 138 139 typedef int RegContextParam; 140 typedef int RegContextVal; 141 142 //used in FP convert & round function 143 enum ConvertType{ 144 SINGLE_TO_DOUBLE, 145 SINGLE_TO_WORD, 146 SINGLE_TO_LONG, 147 148 DOUBLE_TO_SINGLE, 149 DOUBLE_TO_WORD, 150 DOUBLE_TO_LONG, 151 152 LONG_TO_SINGLE, 153 LONG_TO_DOUBLE, 154 LONG_TO_WORD, 155 LONG_TO_PS, 156 157 WORD_TO_SINGLE, 158 WORD_TO_DOUBLE, 159 WORD_TO_LONG, 160 WORD_TO_PS, 161 162 PL_TO_SINGLE, 163 PU_TO_SINGLE 164 }; 165 166 //used in FP convert & round function 167 enum RoundMode{ 168 RND_ZERO, 169 RND_DOWN, 170 RND_UP, 171 RND_NEAREST 172 }; 173 174 enum OperatingMode { 175 MODE_USER = 16, 176 MODE_FIQ = 17, 177 MODE_IRQ = 18, 178 MODE_SVC = 19, 179 MODE_MON = 22, 180 MODE_ABORT = 23, 181 MODE_UNDEFINED = 27, 182 MODE_SYSTEM = 31 183 }; 184 185 struct CoreSpecific { 186 // Empty for now on the ARM 187 }; 188 189} // namespace ArmISA 190 191#endif 192