types.hh revision 6741:73d89772f409 
1/*
2 * Copyright (c) 2007-2008 The Florida State University
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Stephen Hines
29 */
30
31#ifndef __ARCH_ARM_TYPES_HH__
32#define __ARCH_ARM_TYPES_HH__
33
34#include "base/bitunion.hh"
35#include "base/types.hh"
36
37namespace ArmISA
38{
39    typedef uint32_t MachInst;
40
41    BitUnion64(ExtMachInst)
42        // Made up bitfields that make life easier.
43        Bitfield<33>     sevenAndFour;
44        Bitfield<32>     isMisc;
45
46        // All the different types of opcode fields.
47        Bitfield<27, 25> encoding;
48        Bitfield<24, 21> opcode;
49        Bitfield<24, 20> mediaOpcode;
50        Bitfield<24>     opcode24;
51        Bitfield<23, 20> opcode23_20;
52        Bitfield<23, 21> opcode23_21;
53        Bitfield<22>     opcode22;
54        Bitfield<19>     opcode19;
55        Bitfield<18>     opcode18;
56        Bitfield<15, 12> opcode15_12;
57        Bitfield<15>     opcode15;
58        Bitfield<7,  4>  miscOpcode;
59        Bitfield<7>      opcode7;
60        Bitfield<4>      opcode4;
61
62        Bitfield<31, 28> condCode;
63        Bitfield<20>     sField;
64        Bitfield<19, 16> rn;
65        Bitfield<15, 12> rd;
66        Bitfield<11, 7>  shiftSize;
67        Bitfield<6,  5>  shift;
68        Bitfield<3,  0>  rm;
69
70        Bitfield<11, 8>  rs;
71
72        SubBitUnion(puswl, 24, 20)
73            Bitfield<24> prepost;
74            Bitfield<23> up;
75            Bitfield<22> psruser;
76            Bitfield<21> writeback;
77            Bitfield<20> loadOp;
78        EndSubBitUnion(puswl)
79
80        Bitfield<24, 20> pubwl;
81
82        Bitfield<7, 0> imm;
83
84        Bitfield<11, 8>  rotate;
85
86        Bitfield<11, 0>  immed11_0;
87        Bitfield<7,  0>  immed7_0;
88
89        Bitfield<11, 8>  immedHi11_8;
90        Bitfield<3,  0>  immedLo3_0;
91
92        Bitfield<15, 0>  regList;
93
94        Bitfield<23, 0>  offset;
95
96        Bitfield<23, 0>  immed23_0;
97
98        Bitfield<11, 8>  cpNum;
99        Bitfield<18, 16> fn;
100        Bitfield<14, 12> fd;
101        Bitfield<3>      fpRegImm;
102        Bitfield<3,  0>  fm;
103        Bitfield<2,  0>  fpImm;
104        Bitfield<24, 20> punwl;
105
106        Bitfield<7,  0>  m5Func;
107    EndBitUnion(ExtMachInst)
108
109    // Shift types for ARM instructions
110    enum ArmShiftType {
111        LSL = 0,
112        LSR,
113        ASR,
114        ROR
115    };
116
117    typedef uint64_t LargestRead;
118    // Need to use 64 bits to make sure that read requests get handled properly
119
120    typedef int RegContextParam;
121    typedef int RegContextVal;
122
123    //used in FP convert & round function
124    enum ConvertType{
125        SINGLE_TO_DOUBLE,
126        SINGLE_TO_WORD,
127        SINGLE_TO_LONG,
128
129        DOUBLE_TO_SINGLE,
130        DOUBLE_TO_WORD,
131        DOUBLE_TO_LONG,
132
133        LONG_TO_SINGLE,
134        LONG_TO_DOUBLE,
135        LONG_TO_WORD,
136        LONG_TO_PS,
137
138        WORD_TO_SINGLE,
139        WORD_TO_DOUBLE,
140        WORD_TO_LONG,
141        WORD_TO_PS,
142
143        PL_TO_SINGLE,
144        PU_TO_SINGLE
145    };
146
147    //used in FP convert & round function
148    enum RoundMode{
149        RND_ZERO,
150        RND_DOWN,
151        RND_UP,
152        RND_NEAREST
153    };
154
155    enum OperatingMode {
156        MODE_USER = 16,
157        MODE_FIQ = 17,
158        MODE_IRQ = 18,
159        MODE_SVC = 19,
160        MODE_MON = 22,
161        MODE_ABORT = 23,
162        MODE_UNDEFINED = 27,
163        MODE_SYSTEM = 31
164    };
165
166    struct CoreSpecific {
167        // Empty for now on the ARM
168    };
169
170} // namespace ArmISA
171
172#endif
173