types.hh revision 6314:781969fbeca9 
1/*
2 * Copyright (c) 2007-2008 The Florida State University
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Stephen Hines
29 */
30
31#ifndef __ARCH_ARM_TYPES_HH__
32#define __ARCH_ARM_TYPES_HH__
33
34#include "base/bitunion.hh"
35#include "base/types.hh"
36
37namespace ArmISA
38{
39    typedef uint32_t MachInst;
40
41    BitUnion64(ExtMachInst)
42        // Made up bitfields that make life easier.
43        Bitfield<33>     sevenAndFour;
44        Bitfield<32>     isMisc;
45
46        // All the different types of opcode fields.
47        Bitfield<27, 25> encoding;
48        Bitfield<24, 21> opcode;
49        Bitfield<24, 20> mediaOpcode;
50        Bitfield<24>     opcode24;
51        Bitfield<23, 20> opcode23_20;
52        Bitfield<23, 21> opcode23_21;
53        Bitfield<22>     opcode22;
54        Bitfield<19>     opcode19;
55        Bitfield<15, 12> opcode15_12;
56        Bitfield<15>     opcode15;
57        Bitfield<7,  4>  miscOpcode;
58        Bitfield<7>      opcode7;
59        Bitfield<4>      opcode4;
60
61        Bitfield<31, 28> condCode;
62        Bitfield<20>     sField;
63        Bitfield<19, 16> rn;
64        Bitfield<15, 12> rd;
65        Bitfield<11, 7>  shiftSize;
66        Bitfield<6,  5>  shift;
67        Bitfield<3,  0>  rm;
68
69        Bitfield<11, 8>  rs;
70
71        SubBitUnion(puswl, 24, 20)
72            Bitfield<24> prepost;
73            Bitfield<23> up;
74            Bitfield<22> psruser;
75            Bitfield<21> writeback;
76            Bitfield<20> loadOp;
77        EndSubBitUnion(puswl)
78
79        Bitfield<24, 20> pubwl;
80
81        Bitfield<7, 0> imm;
82
83        Bitfield<11, 8>  rotate;
84
85        Bitfield<11, 0>  immed11_0;
86        Bitfield<7,  0>  immed7_0;
87
88        Bitfield<11, 8>  immedHi11_8;
89        Bitfield<3,  0>  immedLo3_0;
90
91        Bitfield<15, 0>  regList;
92
93        Bitfield<23, 0>  offset;
94
95        Bitfield<23, 0>  immed23_0;
96
97        Bitfield<11, 8>  cpNum;
98        Bitfield<18, 16> fn;
99        Bitfield<14, 12> fd;
100        Bitfield<3>      fpRegImm;
101        Bitfield<3,  0>  fm;
102        Bitfield<2,  0>  fpImm;
103        Bitfield<24, 20> punwl;
104
105        Bitfield<7,  0>  m5Func;
106    EndBitUnion(ExtMachInst)
107
108    // Shift types for ARM instructions
109    enum ArmShiftType {
110        LSL = 0,
111        LSR,
112        ASR,
113        ROR
114    };
115
116    typedef uint8_t  RegIndex;
117
118    typedef uint64_t IntReg;
119    typedef uint64_t LargestRead;
120    // Need to use 64 bits to make sure that read requests get handled properly
121
122    // floating point register file entry type
123    typedef uint32_t FloatRegBits;
124    typedef float FloatReg;
125
126    // cop-0/cop-1 system control register
127    typedef uint64_t MiscReg;
128
129    typedef union {
130        IntReg   intreg;
131        FloatReg fpreg;
132        MiscReg  ctrlreg;
133    } AnyReg;
134
135    typedef int RegContextParam;
136    typedef int RegContextVal;
137
138    //used in FP convert & round function
139    enum ConvertType{
140        SINGLE_TO_DOUBLE,
141        SINGLE_TO_WORD,
142        SINGLE_TO_LONG,
143
144        DOUBLE_TO_SINGLE,
145        DOUBLE_TO_WORD,
146        DOUBLE_TO_LONG,
147
148        LONG_TO_SINGLE,
149        LONG_TO_DOUBLE,
150        LONG_TO_WORD,
151        LONG_TO_PS,
152
153        WORD_TO_SINGLE,
154        WORD_TO_DOUBLE,
155        WORD_TO_LONG,
156        WORD_TO_PS,
157
158        PL_TO_SINGLE,
159        PU_TO_SINGLE
160    };
161
162    //used in FP convert & round function
163    enum RoundMode{
164        RND_ZERO,
165        RND_DOWN,
166        RND_UP,
167        RND_NEAREST
168    };
169
170    enum OperatingMode {
171        MODE_USER = 16,
172        MODE_FIQ = 17,
173        MODE_IRQ = 18,
174        MODE_SVC = 19,
175        MODE_ABORT = 23,
176        MODE_UNDEFINED = 27,
177        MODE_SYSTEM = 31
178    };
179
180    struct CoreSpecific {
181        // Empty for now on the ARM
182    };
183
184} // namespace ArmISA
185
186#endif
187