types.hh revision 6254:8abc40611938 
1/*
2 * Copyright (c) 2007-2008 The Florida State University
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Stephen Hines
29 */
30
31#ifndef __ARCH_ARM_TYPES_HH__
32#define __ARCH_ARM_TYPES_HH__
33
34#include "base/bitunion.hh"
35#include "base/types.hh"
36
37namespace ArmISA
38{
39    typedef uint32_t MachInst;
40
41    BitUnion32(ExtMachInst)
42        // All the different types of opcode fields.
43        Bitfield<27, 25> opcode;
44        Bitfield<27, 25> opcode27_25;
45        Bitfield<24, 21> opcode24_21;
46        Bitfield<24, 23> opcode24_23;
47        Bitfield<24>     opcode24;
48        Bitfield<23, 20> opcode23_20;
49        Bitfield<23, 21> opcode23_21;
50        Bitfield<23>     opcode23;
51        Bitfield<22, 8>  opcode22_8;
52        Bitfield<22, 21> opcode22_21;
53        Bitfield<22>     opcode22;
54        Bitfield<21, 20> opcode21_20;
55        Bitfield<20>     opcode20;
56        Bitfield<19, 18> opcode19_18;
57        Bitfield<19>     opcode19;
58        Bitfield<15, 12> opcode15_12;
59        Bitfield<15>     opcode15;
60        Bitfield<9>      opcode9;
61        Bitfield<7,  4>  opcode7_4;
62        Bitfield<7,  5>  opcode7_5;
63        Bitfield<7,  6>  opcode7_6;
64        Bitfield<7>      opcode7;
65        Bitfield<6,  5>  opcode6_5;
66        Bitfield<6>      opcode6;
67        Bitfield<5>      opcode5;
68        Bitfield<4>      opcode4;
69
70        Bitfield<31, 28> condCode;
71        Bitfield<20>     sField;
72        Bitfield<19, 16> rn;
73        Bitfield<15, 12> rd;
74        Bitfield<11, 7>  shiftSize;
75        Bitfield<6,  5>  shift;
76        Bitfield<3,  0>  rm;
77
78        Bitfield<11, 8>  rs;
79
80        Bitfield<19, 16> rdup;
81        Bitfield<15, 12> rddn;
82
83        Bitfield<15, 12> rdhi;
84        Bitfield<11, 8>  rdlo;
85
86        Bitfield<23>     uField;
87
88        SubBitUnion(puswl, 24, 20)
89            Bitfield<24> prepost;
90            Bitfield<23> up;
91            Bitfield<22> psruser;
92            Bitfield<21> writeback;
93            Bitfield<20> loadOp;
94        EndSubBitUnion(puswl)
95
96        Bitfield<24, 20> pubwl;
97        Bitfield<24, 20> puiwl;
98        Bitfield<22>     byteAccess;
99
100        Bitfield<23, 20> luas;
101
102        SubBitUnion(imm, 7, 0)
103            Bitfield<7, 4> imm7_4;
104            Bitfield<3, 0> imm3_0;
105        EndSubBitUnion(imm)
106
107        SubBitUnion(msr, 19, 16)
108            Bitfield<19> f;
109            Bitfield<18> s;
110            Bitfield<17> x;
111            Bitfield<16> c;
112        EndSubBitUnion(msr)
113
114        Bitfield<6>      y;
115        Bitfield<5>      x;
116
117        Bitfield<15, 4>  immed15_4;
118
119        Bitfield<21>     wField;
120
121        Bitfield<11, 8>  rotate;
122        Bitfield<7,  0>  immed7_0;
123
124        Bitfield<21>     tField;
125        Bitfield<11, 0>  immed11_0;
126
127        Bitfield<20, 16> immed20_16;
128        Bitfield<19, 16> immed19_16;
129
130        Bitfield<11, 8>  immedHi11_8;
131        Bitfield<3,  0>  immedLo3_0;
132
133        Bitfield<11, 10> rot;
134
135        Bitfield<5>      rField;
136
137        Bitfield<22>     caret;
138        Bitfield<15, 0>  regList;
139
140        Bitfield<23, 0>  offset;
141        Bitfield<11, 8>  copro;
142        Bitfield<7,  4>  op1_7_4;
143        Bitfield<3,  0>  cm;
144
145        Bitfield<22>     lField;
146        Bitfield<15, 12> cd;
147        Bitfield<7,  0>  option;
148
149        Bitfield<23, 20> op1_23_20;
150        Bitfield<19, 16> cn;
151        Bitfield<7,  5>  op2_7_5;
152
153        Bitfield<23, 21> op1_23_21;
154
155        Bitfield<23, 0>  immed23_0;
156        Bitfield<17>     mField;
157        Bitfield<8>      aField;
158        Bitfield<7>      iField;
159        Bitfield<6>      fField;
160        Bitfield<4,  0>  mode;
161
162        Bitfield<24>     aBlx;
163
164        Bitfield<11, 8>  cpNum;
165        Bitfield<18, 16> fn;
166        Bitfield<14, 12> fd;
167        Bitfield<3>      fpRegImm;
168        Bitfield<3,  0>  fm;
169        Bitfield<2,  0>  fpImm;
170        Bitfield<24, 20> punwl;
171
172        Bitfield<7,  0>  m5Func;
173    EndBitUnion(ExtMachInst)
174
175    // Shift types for ARM instructions
176    enum ArmShiftType {
177        LSL = 0,
178        LSR,
179        ASR,
180        ROR
181    };
182
183    typedef uint8_t  RegIndex;
184
185    typedef uint64_t IntReg;
186    typedef uint64_t LargestRead;
187    // Need to use 64 bits to make sure that read requests get handled properly
188
189    // floating point register file entry type
190    typedef uint32_t FloatReg32;
191    typedef uint64_t FloatReg64;
192    typedef uint64_t FloatRegBits;
193
194    typedef double FloatRegVal;
195    typedef double FloatReg;
196
197    // cop-0/cop-1 system control register
198    typedef uint64_t MiscReg;
199
200    typedef union {
201        IntReg   intreg;
202        FloatReg fpreg;
203        MiscReg  ctrlreg;
204    } AnyReg;
205
206    typedef int RegContextParam;
207    typedef int RegContextVal;
208
209    //used in FP convert & round function
210    enum ConvertType{
211        SINGLE_TO_DOUBLE,
212        SINGLE_TO_WORD,
213        SINGLE_TO_LONG,
214
215        DOUBLE_TO_SINGLE,
216        DOUBLE_TO_WORD,
217        DOUBLE_TO_LONG,
218
219        LONG_TO_SINGLE,
220        LONG_TO_DOUBLE,
221        LONG_TO_WORD,
222        LONG_TO_PS,
223
224        WORD_TO_SINGLE,
225        WORD_TO_DOUBLE,
226        WORD_TO_LONG,
227        WORD_TO_PS,
228
229        PL_TO_SINGLE,
230        PU_TO_SINGLE
231    };
232
233    //used in FP convert & round function
234    enum RoundMode{
235        RND_ZERO,
236        RND_DOWN,
237        RND_UP,
238        RND_NEAREST
239    };
240
241    enum OperatingMode {
242        MODE_USER = 16,
243        MODE_FIQ = 17,
244        MODE_IRQ = 18,
245        MODE_SVC = 19,
246        MODE_ABORT = 23,
247        MODE_UNDEFINED = 27,
248        MODE_SYSTEM = 31
249    };
250
251    struct CoreSpecific {
252        // Empty for now on the ARM
253    };
254
255} // namespace ArmISA
256
257#endif
258