types.hh revision 12763
17375Sgblack@eecs.umich.edu/* 210037SARM gem5 Developers * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited 37375Sgblack@eecs.umich.edu * All rights reserved 47375Sgblack@eecs.umich.edu * 57375Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67375Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77375Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87375Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97375Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107375Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117375Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127375Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137375Sgblack@eecs.umich.edu * 147375Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Florida State University 157375Sgblack@eecs.umich.edu * All rights reserved. 167375Sgblack@eecs.umich.edu * 177375Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 187375Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 197375Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 207375Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 217375Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 227375Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 237375Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 247375Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 257375Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 267375Sgblack@eecs.umich.edu * this software without specific prior written permission. 277375Sgblack@eecs.umich.edu * 287375Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 297375Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 307375Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 317375Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 327375Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 337375Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 347375Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 357375Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 367375Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 377375Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 387375Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 397375Sgblack@eecs.umich.edu * 407375Sgblack@eecs.umich.edu * Authors: Stephen Hines 417375Sgblack@eecs.umich.edu */ 427375Sgblack@eecs.umich.edu 438229Snate@binkert.org#ifndef __ARCH_ARM_TYPES_HH__ 448229Snate@binkert.org#define __ARCH_ARM_TYPES_HH__ 458229Snate@binkert.org 468229Snate@binkert.org#include "arch/generic/types.hh" 477375Sgblack@eecs.umich.edu#include "base/bitunion.hh" 487378Sgblack@eecs.umich.edu#include "base/logging.hh" 497375Sgblack@eecs.umich.edu#include "base/types.hh" 507384Sgblack@eecs.umich.edu#include "debug/Decoder.hh" 517384Sgblack@eecs.umich.edu 527384Sgblack@eecs.umich.edunamespace ArmISA 537375Sgblack@eecs.umich.edu{ 547375Sgblack@eecs.umich.edu typedef uint32_t MachInst; 557375Sgblack@eecs.umich.edu 567375Sgblack@eecs.umich.edu BitUnion8(ITSTATE) 577375Sgblack@eecs.umich.edu /* Note that the split (cond, mask) below is not as in ARM ARM. 587375Sgblack@eecs.umich.edu * But it is more convenient for simulation. The condition 597375Sgblack@eecs.umich.edu * is always the concatenation of the top 3 bits and the next bit, 607375Sgblack@eecs.umich.edu * which applies when one of the bottom 4 bits is set. 617375Sgblack@eecs.umich.edu * Refer to predecoder.cc for the use case. 627375Sgblack@eecs.umich.edu */ 637375Sgblack@eecs.umich.edu Bitfield<7, 4> cond; 647375Sgblack@eecs.umich.edu Bitfield<3, 0> mask; 657375Sgblack@eecs.umich.edu // Bitfields for moving to/from CPSR 667375Sgblack@eecs.umich.edu Bitfield<7, 2> top6; 677375Sgblack@eecs.umich.edu Bitfield<1, 0> bottom2; 687375Sgblack@eecs.umich.edu EndBitUnion(ITSTATE) 697375Sgblack@eecs.umich.edu 707375Sgblack@eecs.umich.edu BitUnion64(ExtMachInst) 717375Sgblack@eecs.umich.edu // Decoder state 727375Sgblack@eecs.umich.edu Bitfield<63, 62> decoderFault; // See DecoderFault 737375Sgblack@eecs.umich.edu Bitfield<61> illegalExecution; 747375Sgblack@eecs.umich.edu 757375Sgblack@eecs.umich.edu // ITSTATE bits 767375Sgblack@eecs.umich.edu Bitfield<55, 48> itstate; 777375Sgblack@eecs.umich.edu Bitfield<55, 52> itstateCond; 787375Sgblack@eecs.umich.edu Bitfield<51, 48> itstateMask; 797376Sgblack@eecs.umich.edu 807376Sgblack@eecs.umich.edu // FPSCR fields 817376Sgblack@eecs.umich.edu Bitfield<41, 40> fpscrStride; 827375Sgblack@eecs.umich.edu Bitfield<39, 37> fpscrLen; 837375Sgblack@eecs.umich.edu 847378Sgblack@eecs.umich.edu // Bitfields to select mode. 857378Sgblack@eecs.umich.edu Bitfield<36> thumb; 867378Sgblack@eecs.umich.edu Bitfield<35> bigThumb; 877378Sgblack@eecs.umich.edu Bitfield<34> aarch64; 887378Sgblack@eecs.umich.edu 897378Sgblack@eecs.umich.edu // Made up bitfields that make life easier. 907378Sgblack@eecs.umich.edu Bitfield<33> sevenAndFour; 917378Sgblack@eecs.umich.edu Bitfield<32> isMisc; 927378Sgblack@eecs.umich.edu 937378Sgblack@eecs.umich.edu uint32_t instBits; 947378Sgblack@eecs.umich.edu 957378Sgblack@eecs.umich.edu // All the different types of opcode fields. 967378Sgblack@eecs.umich.edu Bitfield<27, 25> encoding; 977378Sgblack@eecs.umich.edu Bitfield<25> useImm; 987378Sgblack@eecs.umich.edu Bitfield<24, 21> opcode; 997378Sgblack@eecs.umich.edu Bitfield<24, 20> mediaOpcode; 1007378Sgblack@eecs.umich.edu Bitfield<24> opcode24; 1017378Sgblack@eecs.umich.edu Bitfield<24, 23> opcode24_23; 1027378Sgblack@eecs.umich.edu Bitfield<23, 20> opcode23_20; 1037378Sgblack@eecs.umich.edu Bitfield<23, 21> opcode23_21; 1047378Sgblack@eecs.umich.edu Bitfield<20> opcode20; 1057378Sgblack@eecs.umich.edu Bitfield<22> opcode22; 1067378Sgblack@eecs.umich.edu Bitfield<19, 16> opcode19_16; 10710037SARM gem5 Developers Bitfield<19> opcode19; 10810037SARM gem5 Developers Bitfield<18> opcode18; 1097378Sgblack@eecs.umich.edu Bitfield<15, 12> opcode15_12; 1107378Sgblack@eecs.umich.edu Bitfield<15> opcode15; 1118737Skoansin.tan@gmail.com Bitfield<7, 4> miscOpcode; 1128865SGiacomo.Gabrielli@arm.com Bitfield<7,5> opc2; 1138737Skoansin.tan@gmail.com Bitfield<7> opcode7; 1148865SGiacomo.Gabrielli@arm.com Bitfield<6> opcode6; 1158737Skoansin.tan@gmail.com Bitfield<4> opcode4; 1167382Sgblack@eecs.umich.edu 1177396Sgblack@eecs.umich.edu Bitfield<31, 28> condCode; 1187396Sgblack@eecs.umich.edu Bitfield<20> sField; 1197396Sgblack@eecs.umich.edu Bitfield<19, 16> rn; 1207396Sgblack@eecs.umich.edu Bitfield<15, 12> rd; 1217396Sgblack@eecs.umich.edu Bitfield<15, 12> rt; 1227396Sgblack@eecs.umich.edu Bitfield<11, 7> shiftSize; 1237396Sgblack@eecs.umich.edu Bitfield<6, 5> shift; 1247396Sgblack@eecs.umich.edu Bitfield<3, 0> rm; 1257396Sgblack@eecs.umich.edu 1267396Sgblack@eecs.umich.edu Bitfield<11, 8> rs; 1277396Sgblack@eecs.umich.edu 1287396Sgblack@eecs.umich.edu SubBitUnion(puswl, 24, 20) 1297396Sgblack@eecs.umich.edu Bitfield<24> prepost; 1307396Sgblack@eecs.umich.edu Bitfield<23> up; 1317396Sgblack@eecs.umich.edu Bitfield<22> psruser; 1327396Sgblack@eecs.umich.edu Bitfield<21> writeback; 1337396Sgblack@eecs.umich.edu Bitfield<20> loadOp; 1347396Sgblack@eecs.umich.edu EndSubBitUnion(puswl) 1357396Sgblack@eecs.umich.edu 1367396Sgblack@eecs.umich.edu Bitfield<24, 20> pubwl; 1377396Sgblack@eecs.umich.edu 1387397Sgblack@eecs.umich.edu Bitfield<7, 0> imm; 1397397Sgblack@eecs.umich.edu 1407397Sgblack@eecs.umich.edu Bitfield<11, 8> rotate; 1417397Sgblack@eecs.umich.edu 1427397Sgblack@eecs.umich.edu Bitfield<11, 0> immed11_0; 1437397Sgblack@eecs.umich.edu Bitfield<7, 0> immed7_0; 1447397Sgblack@eecs.umich.edu 1457397Sgblack@eecs.umich.edu Bitfield<11, 8> immedHi11_8; 1467397Sgblack@eecs.umich.edu Bitfield<3, 0> immedLo3_0; 1477397Sgblack@eecs.umich.edu 1487397Sgblack@eecs.umich.edu Bitfield<15, 0> regList; 1497397Sgblack@eecs.umich.edu 1507397Sgblack@eecs.umich.edu Bitfield<23, 0> offset; 1517397Sgblack@eecs.umich.edu 1527397Sgblack@eecs.umich.edu Bitfield<23, 0> immed23_0; 1537397Sgblack@eecs.umich.edu 1547397Sgblack@eecs.umich.edu Bitfield<11, 8> cpNum; 1557384Sgblack@eecs.umich.edu Bitfield<18, 16> fn; 1567384Sgblack@eecs.umich.edu Bitfield<14, 12> fd; 1577384Sgblack@eecs.umich.edu Bitfield<3> fpRegImm; 1587384Sgblack@eecs.umich.edu Bitfield<3, 0> fm; 1597384Sgblack@eecs.umich.edu Bitfield<2, 0> fpImm; 1607384Sgblack@eecs.umich.edu Bitfield<24, 20> punwl; 1617384Sgblack@eecs.umich.edu 1627384Sgblack@eecs.umich.edu Bitfield<15, 8> m5Func; 1637384Sgblack@eecs.umich.edu 1647384Sgblack@eecs.umich.edu // 16 bit thumb bitfields 1657384Sgblack@eecs.umich.edu Bitfield<15, 13> topcode15_13; 1667384Sgblack@eecs.umich.edu Bitfield<13, 11> topcode13_11; 1677384Sgblack@eecs.umich.edu Bitfield<12, 11> topcode12_11; 1687384Sgblack@eecs.umich.edu Bitfield<12, 10> topcode12_10; 1697384Sgblack@eecs.umich.edu Bitfield<11, 9> topcode11_9; 1707384Sgblack@eecs.umich.edu Bitfield<11, 8> topcode11_8; 1717384Sgblack@eecs.umich.edu Bitfield<10, 9> topcode10_9; 1727384Sgblack@eecs.umich.edu Bitfield<10, 8> topcode10_8; 1737384Sgblack@eecs.umich.edu Bitfield<9, 6> topcode9_6; 1747384Sgblack@eecs.umich.edu Bitfield<7> topcode7; 1757384Sgblack@eecs.umich.edu Bitfield<7, 6> topcode7_6; 1767384Sgblack@eecs.umich.edu Bitfield<7, 5> topcode7_5; 1777384Sgblack@eecs.umich.edu Bitfield<7, 4> topcode7_4; 1787384Sgblack@eecs.umich.edu Bitfield<3, 0> topcode3_0; 1797384Sgblack@eecs.umich.edu 1807384Sgblack@eecs.umich.edu // 32 bit thumb bitfields 1817384Sgblack@eecs.umich.edu Bitfield<28, 27> htopcode12_11; 1827384Sgblack@eecs.umich.edu Bitfield<26, 25> htopcode10_9; 1837384Sgblack@eecs.umich.edu Bitfield<25> htopcode9; 1847384Sgblack@eecs.umich.edu Bitfield<25, 24> htopcode9_8; 1857384Sgblack@eecs.umich.edu Bitfield<25, 21> htopcode9_5; 1867384Sgblack@eecs.umich.edu Bitfield<25, 20> htopcode9_4; 1877384Sgblack@eecs.umich.edu Bitfield<24> htopcode8; 1887384Sgblack@eecs.umich.edu Bitfield<24, 23> htopcode8_7; 1897384Sgblack@eecs.umich.edu Bitfield<24, 22> htopcode8_6; 1907384Sgblack@eecs.umich.edu Bitfield<24, 21> htopcode8_5; 1917384Sgblack@eecs.umich.edu Bitfield<23> htopcode7; 1927384Sgblack@eecs.umich.edu Bitfield<23, 21> htopcode7_5; 1937384Sgblack@eecs.umich.edu Bitfield<22> htopcode6; 1947384Sgblack@eecs.umich.edu Bitfield<22, 21> htopcode6_5; 1957384Sgblack@eecs.umich.edu Bitfield<21, 20> htopcode5_4; 1967384Sgblack@eecs.umich.edu Bitfield<20> htopcode4; 1977384Sgblack@eecs.umich.edu 1987384Sgblack@eecs.umich.edu Bitfield<19, 16> htrn; 1997384Sgblack@eecs.umich.edu Bitfield<20> hts; 2007384Sgblack@eecs.umich.edu 2017384Sgblack@eecs.umich.edu Bitfield<15> ltopcode15; 2027384Sgblack@eecs.umich.edu Bitfield<11, 8> ltopcode11_8; 2037639Sgblack@eecs.umich.edu Bitfield<7, 6> ltopcode7_6; 20412032Sandreas.sandberg@arm.com Bitfield<7, 4> ltopcode7_4; 2057639Sgblack@eecs.umich.edu Bitfield<4> ltopcode4; 2067639Sgblack@eecs.umich.edu 2077639Sgblack@eecs.umich.edu Bitfield<11, 8> ltrd; 2087639Sgblack@eecs.umich.edu Bitfield<11, 8> ltcoproc; 2097639Sgblack@eecs.umich.edu EndBitUnion(ExtMachInst) 2107639Sgblack@eecs.umich.edu 2117639Sgblack@eecs.umich.edu class PCState : public GenericISA::UPCState<MachInst> 2127639Sgblack@eecs.umich.edu { 2137396Sgblack@eecs.umich.edu protected: 2147396Sgblack@eecs.umich.edu 2157430Sgblack@eecs.umich.edu typedef GenericISA::UPCState<MachInst> Base; 21610037SARM gem5 Developers 2177396Sgblack@eecs.umich.edu enum FlagBits { 2187384Sgblack@eecs.umich.edu ThumbBit = (1 << 0), 2197430Sgblack@eecs.umich.edu JazelleBit = (1 << 1), 2207386Sgblack@eecs.umich.edu AArch64Bit = (1 << 2) 2217386Sgblack@eecs.umich.edu }; 2227430Sgblack@eecs.umich.edu 2237384Sgblack@eecs.umich.edu uint8_t flags; 2247386Sgblack@eecs.umich.edu uint8_t nextFlags; 2257430Sgblack@eecs.umich.edu uint8_t _itstate; 2267386Sgblack@eecs.umich.edu uint8_t _nextItstate; 2277430Sgblack@eecs.umich.edu uint8_t _size; 2287430Sgblack@eecs.umich.edu bool _illegalExec; 2297386Sgblack@eecs.umich.edu public: 2307639Sgblack@eecs.umich.edu PCState() : flags(0), nextFlags(0), _itstate(0), _nextItstate(0), 2317639Sgblack@eecs.umich.edu _size(0), _illegalExec(false) 23210037SARM gem5 Developers {} 23310037SARM gem5 Developers 23410037SARM gem5 Developers void 23510037SARM gem5 Developers set(Addr val) 23610037SARM gem5 Developers { 2377398Sgblack@eecs.umich.edu Base::set(val); 2387396Sgblack@eecs.umich.edu npc(val + (thumb() ? 2 : 4)); 2397396Sgblack@eecs.umich.edu } 2407396Sgblack@eecs.umich.edu 2417396Sgblack@eecs.umich.edu PCState(Addr val) : flags(0), nextFlags(0), _itstate(0), 2427396Sgblack@eecs.umich.edu _nextItstate(0), _size(0), _illegalExec(false) 2437396Sgblack@eecs.umich.edu { set(val); } 2447396Sgblack@eecs.umich.edu 2457396Sgblack@eecs.umich.edu bool 2467396Sgblack@eecs.umich.edu illegalExec() const 2477396Sgblack@eecs.umich.edu { 2487396Sgblack@eecs.umich.edu return _illegalExec; 2497396Sgblack@eecs.umich.edu } 2507396Sgblack@eecs.umich.edu 2517396Sgblack@eecs.umich.edu void 2527396Sgblack@eecs.umich.edu illegalExec(bool val) 2537396Sgblack@eecs.umich.edu { 2547396Sgblack@eecs.umich.edu _illegalExec = val; 2557396Sgblack@eecs.umich.edu } 2567396Sgblack@eecs.umich.edu 25710037SARM gem5 Developers bool 25810037SARM gem5 Developers thumb() const 25910037SARM gem5 Developers { 26010037SARM gem5 Developers return flags & ThumbBit; 26110037SARM gem5 Developers } 26210037SARM gem5 Developers 26310037SARM gem5 Developers void 26410037SARM gem5 Developers thumb(bool val) 26510037SARM gem5 Developers { 26610037SARM gem5 Developers if (val) 26710037SARM gem5 Developers flags |= ThumbBit; 26810037SARM gem5 Developers else 26910037SARM gem5 Developers flags &= ~ThumbBit; 27010037SARM gem5 Developers } 27110037SARM gem5 Developers 27210037SARM gem5 Developers bool 27310037SARM gem5 Developers nextThumb() const 27410037SARM gem5 Developers { 27510037SARM gem5 Developers return nextFlags & ThumbBit; 27610037SARM gem5 Developers } 27710037SARM gem5 Developers 27810037SARM gem5 Developers void 27910037SARM gem5 Developers nextThumb(bool val) 28010037SARM gem5 Developers { 28110037SARM gem5 Developers if (val) 28210037SARM gem5 Developers nextFlags |= ThumbBit; 28310037SARM gem5 Developers else 28410037SARM gem5 Developers nextFlags &= ~ThumbBit; 28510037SARM gem5 Developers } 28610037SARM gem5 Developers 28710037SARM gem5 Developers void size(uint8_t s) { _size = s; } 28810037SARM gem5 Developers uint8_t size() const { return _size; } 28910037SARM gem5 Developers 29010037SARM gem5 Developers bool 29110037SARM gem5 Developers branching() const 29210037SARM gem5 Developers { 29310037SARM gem5 Developers return ((this->pc() + this->size()) != this->npc()); 29410037SARM gem5 Developers } 29510037SARM gem5 Developers 29610037SARM gem5 Developers 29710037SARM gem5 Developers bool 29810037SARM gem5 Developers jazelle() const 29910037SARM gem5 Developers { 30010037SARM gem5 Developers return flags & JazelleBit; 30110037SARM gem5 Developers } 30210037SARM gem5 Developers 30310037SARM gem5 Developers void 30410037SARM gem5 Developers jazelle(bool val) 30510037SARM gem5 Developers { 30610037SARM gem5 Developers if (val) 30710037SARM gem5 Developers flags |= JazelleBit; 30810037SARM gem5 Developers else 30910037SARM gem5 Developers flags &= ~JazelleBit; 31010037SARM gem5 Developers } 31110037SARM gem5 Developers 31210037SARM gem5 Developers bool 31310037SARM gem5 Developers nextJazelle() const 31410037SARM gem5 Developers { 31510037SARM gem5 Developers return nextFlags & JazelleBit; 31610037SARM gem5 Developers } 31710037SARM gem5 Developers 31810037SARM gem5 Developers void 31910037SARM gem5 Developers nextJazelle(bool val) 32010037SARM gem5 Developers { 32110037SARM gem5 Developers if (val) 32210037SARM gem5 Developers nextFlags |= JazelleBit; 32310037SARM gem5 Developers else 32410037SARM gem5 Developers nextFlags &= ~JazelleBit; 32510037SARM gem5 Developers } 32610037SARM gem5 Developers 32710037SARM gem5 Developers bool 32810037SARM gem5 Developers aarch64() const 32910037SARM gem5 Developers { 33010037SARM gem5 Developers return flags & AArch64Bit; 33110037SARM gem5 Developers } 33210037SARM gem5 Developers 33310037SARM gem5 Developers void 33410037SARM gem5 Developers aarch64(bool val) 33510037SARM gem5 Developers { 33610037SARM gem5 Developers if (val) 33710037SARM gem5 Developers flags |= AArch64Bit; 33810037SARM gem5 Developers else 33910037SARM gem5 Developers flags &= ~AArch64Bit; 34010037SARM gem5 Developers } 34110037SARM gem5 Developers 34210037SARM gem5 Developers bool 34310037SARM gem5 Developers nextAArch64() const 34410037SARM gem5 Developers { 34510037SARM gem5 Developers return nextFlags & AArch64Bit; 34610037SARM gem5 Developers } 34710037SARM gem5 Developers 34810037SARM gem5 Developers void 34910037SARM gem5 Developers nextAArch64(bool val) 35010037SARM gem5 Developers { 35110037SARM gem5 Developers if (val) 35210037SARM gem5 Developers nextFlags |= AArch64Bit; 35310037SARM gem5 Developers else 35410037SARM gem5 Developers nextFlags &= ~AArch64Bit; 35510037SARM gem5 Developers } 35610037SARM gem5 Developers 35710037SARM gem5 Developers 35810037SARM gem5 Developers uint8_t 35910037SARM gem5 Developers itstate() const 36010037SARM gem5 Developers { 36110037SARM gem5 Developers return _itstate; 36210037SARM gem5 Developers } 36310037SARM gem5 Developers 36410037SARM gem5 Developers void 36510037SARM gem5 Developers itstate(uint8_t value) 36610037SARM gem5 Developers { 36710037SARM gem5 Developers _itstate = value; 36810037SARM gem5 Developers } 36910037SARM gem5 Developers 37010037SARM gem5 Developers uint8_t 37110037SARM gem5 Developers nextItstate() const 37210037SARM gem5 Developers { 37310037SARM gem5 Developers return _nextItstate; 37410037SARM gem5 Developers } 37510037SARM gem5 Developers 37610037SARM gem5 Developers void 37710037SARM gem5 Developers nextItstate(uint8_t value) 37810037SARM gem5 Developers { 37910037SARM gem5 Developers _nextItstate = value; 38010037SARM gem5 Developers } 38110037SARM gem5 Developers 38210037SARM gem5 Developers void 38310037SARM gem5 Developers advance() 38410037SARM gem5 Developers { 38510037SARM gem5 Developers Base::advance(); 38610037SARM gem5 Developers flags = nextFlags; 38710037SARM gem5 Developers npc(pc() + (thumb() ? 2 : 4)); 38810037SARM gem5 Developers 38910037SARM gem5 Developers if (_nextItstate) { 39010037SARM gem5 Developers _itstate = _nextItstate; 39110037SARM gem5 Developers _nextItstate = 0; 39210037SARM gem5 Developers } else if (_itstate) { 39310037SARM gem5 Developers ITSTATE it = _itstate; 39410037SARM gem5 Developers uint8_t cond_mask = it.mask; 39510037SARM gem5 Developers uint8_t thumb_cond = it.cond; 39610037SARM gem5 Developers DPRINTF(Decoder, "Advancing ITSTATE from %#x,%#x.\n", 39710037SARM gem5 Developers thumb_cond, cond_mask); 39810037SARM gem5 Developers cond_mask <<= 1; 39910037SARM gem5 Developers uint8_t new_bit = bits(cond_mask, 4); 40010037SARM gem5 Developers cond_mask &= mask(4); 40110037SARM gem5 Developers if (cond_mask == 0) 40210037SARM gem5 Developers thumb_cond = 0; 40310037SARM gem5 Developers else 40410037SARM gem5 Developers replaceBits(thumb_cond, 0, new_bit); 40510037SARM gem5 Developers DPRINTF(Decoder, "Advancing ITSTATE to %#x,%#x.\n", 40610037SARM gem5 Developers thumb_cond, cond_mask); 40710037SARM gem5 Developers it.mask = cond_mask; 40810037SARM gem5 Developers it.cond = thumb_cond; 40910037SARM gem5 Developers _itstate = it; 41010037SARM gem5 Developers } 41110037SARM gem5 Developers } 41210037SARM gem5 Developers 41310037SARM gem5 Developers void 41410037SARM gem5 Developers uEnd() 41510037SARM gem5 Developers { 41610037SARM gem5 Developers advance(); 41710037SARM gem5 Developers upc(0); 41810037SARM gem5 Developers nupc(1); 41910037SARM gem5 Developers } 42010037SARM gem5 Developers 42110037SARM gem5 Developers Addr 42210037SARM gem5 Developers instPC() const 42310037SARM gem5 Developers { 42410037SARM gem5 Developers return pc() + (thumb() ? 4 : 8); 42510037SARM gem5 Developers } 42610037SARM gem5 Developers 42710037SARM gem5 Developers void 42810037SARM gem5 Developers instNPC(Addr val) 42910037SARM gem5 Developers { 43010037SARM gem5 Developers // @todo: review this when AArch32/64 interprocessing is 43110037SARM gem5 Developers // supported 43210037SARM gem5 Developers if (aarch64()) 43310037SARM gem5 Developers npc(val); // AArch64 doesn't force PC alignment, a PC 4347639Sgblack@eecs.umich.edu // Alignment Fault can be raised instead 43510037SARM gem5 Developers else 4367639Sgblack@eecs.umich.edu npc(val &~ mask(nextThumb() ? 1 : 2)); 43710037SARM gem5 Developers } 4387382Sgblack@eecs.umich.edu 4397639Sgblack@eecs.umich.edu Addr 44010037SARM gem5 Developers instNPC() const 4417639Sgblack@eecs.umich.edu { 44210037SARM gem5 Developers return npc(); 4437639Sgblack@eecs.umich.edu } 4447639Sgblack@eecs.umich.edu 4457639Sgblack@eecs.umich.edu // Perform an interworking branch. 4467639Sgblack@eecs.umich.edu void 4477639Sgblack@eecs.umich.edu instIWNPC(Addr val) 4487639Sgblack@eecs.umich.edu { 4497379Sgblack@eecs.umich.edu bool thumbEE = (thumb() && jazelle()); 4507376Sgblack@eecs.umich.edu 4517376Sgblack@eecs.umich.edu Addr newPC = val; 4527376Sgblack@eecs.umich.edu if (thumbEE) { 4537376Sgblack@eecs.umich.edu if (bits(newPC, 0)) { 4547376Sgblack@eecs.umich.edu newPC = newPC & ~mask(1); 4557376Sgblack@eecs.umich.edu } // else we have a bad interworking address; do not call 4567376Sgblack@eecs.umich.edu // panic() since the instruction could be executed 4577376Sgblack@eecs.umich.edu // speculatively 4587376Sgblack@eecs.umich.edu } else { 4597376Sgblack@eecs.umich.edu if (bits(newPC, 0)) { 4607376Sgblack@eecs.umich.edu nextThumb(true); 4617376Sgblack@eecs.umich.edu newPC = newPC & ~mask(1); 4627376Sgblack@eecs.umich.edu } else if (!bits(newPC, 1)) { 4637376Sgblack@eecs.umich.edu nextThumb(false); 4647376Sgblack@eecs.umich.edu } else { 4657376Sgblack@eecs.umich.edu // This state is UNPREDICTABLE in the ARM architecture 4667376Sgblack@eecs.umich.edu // The easy thing to do is just mask off the bit and 4677430Sgblack@eecs.umich.edu // stay in the current mode, so we'll do that. 4687430Sgblack@eecs.umich.edu newPC &= ~mask(2); 4697430Sgblack@eecs.umich.edu } 4707430Sgblack@eecs.umich.edu } 4717376Sgblack@eecs.umich.edu npc(newPC); 4727376Sgblack@eecs.umich.edu } 47310037SARM gem5 Developers 47410037SARM gem5 Developers // Perform an interworking branch in ARM mode, a regular branch 47510037SARM gem5 Developers // otherwise. 47610037SARM gem5 Developers void 47710037SARM gem5 Developers instAIWNPC(Addr val) 47810037SARM gem5 Developers { 47910037SARM gem5 Developers if (!thumb() && !jazelle()) 48010037SARM gem5 Developers instIWNPC(val); 48110037SARM gem5 Developers else 48210037SARM gem5 Developers instNPC(val); 48310037SARM gem5 Developers } 48410037SARM gem5 Developers 48510037SARM gem5 Developers bool 48610037SARM gem5 Developers operator == (const PCState &opc) const 4877396Sgblack@eecs.umich.edu { 4887396Sgblack@eecs.umich.edu return Base::operator == (opc) && 4897396Sgblack@eecs.umich.edu flags == opc.flags && nextFlags == opc.nextFlags && 4907396Sgblack@eecs.umich.edu _itstate == opc._itstate && 4917396Sgblack@eecs.umich.edu _nextItstate == opc._nextItstate && 4927396Sgblack@eecs.umich.edu _illegalExec == opc._illegalExec; 4937396Sgblack@eecs.umich.edu } 4947396Sgblack@eecs.umich.edu 4957396Sgblack@eecs.umich.edu bool 4967396Sgblack@eecs.umich.edu operator != (const PCState &opc) const 4977396Sgblack@eecs.umich.edu { 4987396Sgblack@eecs.umich.edu return !(*this == opc); 4997396Sgblack@eecs.umich.edu } 5007396Sgblack@eecs.umich.edu 5017396Sgblack@eecs.umich.edu void 5027396Sgblack@eecs.umich.edu serialize(CheckpointOut &cp) const override 5037396Sgblack@eecs.umich.edu { 5047396Sgblack@eecs.umich.edu Base::serialize(cp); 5057396Sgblack@eecs.umich.edu SERIALIZE_SCALAR(flags); 5067396Sgblack@eecs.umich.edu SERIALIZE_SCALAR(_size); 5077396Sgblack@eecs.umich.edu SERIALIZE_SCALAR(nextFlags); 5087396Sgblack@eecs.umich.edu SERIALIZE_SCALAR(_itstate); 5097396Sgblack@eecs.umich.edu SERIALIZE_SCALAR(_nextItstate); 5107396Sgblack@eecs.umich.edu SERIALIZE_SCALAR(_illegalExec); 5117396Sgblack@eecs.umich.edu } 5127396Sgblack@eecs.umich.edu 5137396Sgblack@eecs.umich.edu void 5147396Sgblack@eecs.umich.edu unserialize(CheckpointIn &cp) override 5157396Sgblack@eecs.umich.edu { 5167396Sgblack@eecs.umich.edu Base::unserialize(cp); 5177396Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(flags); 5187396Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(_size); 5197396Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(nextFlags); 5207396Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(_itstate); 5217396Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(_nextItstate); 5227396Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(_illegalExec); 52310037SARM gem5 Developers } 52410037SARM gem5 Developers }; 52510037SARM gem5 Developers 52610037SARM gem5 Developers // Shift types for ARM instructions 52710037SARM gem5 Developers enum ArmShiftType { 52810037SARM gem5 Developers LSL = 0, 52910037SARM gem5 Developers LSR, 53010037SARM gem5 Developers ASR, 53110037SARM gem5 Developers ROR 53210037SARM gem5 Developers }; 53310037SARM gem5 Developers 53410037SARM gem5 Developers // Extension types for ARM instructions 53510037SARM gem5 Developers enum ArmExtendType { 53610037SARM gem5 Developers UXTB = 0, 53710037SARM gem5 Developers UXTH = 1, 53810037SARM gem5 Developers UXTW = 2, 53910037SARM gem5 Developers UXTX = 3, 54010037SARM gem5 Developers SXTB = 4, 54110037SARM gem5 Developers SXTH = 5, 54210037SARM gem5 Developers SXTW = 6, 54310037SARM gem5 Developers SXTX = 7 54410037SARM gem5 Developers }; 54510037SARM gem5 Developers 54610037SARM gem5 Developers typedef int RegContextParam; 54710037SARM gem5 Developers typedef int RegContextVal; 54810037SARM gem5 Developers 54910037SARM gem5 Developers //used in FP convert & round function 55010037SARM gem5 Developers enum ConvertType{ 55110037SARM gem5 Developers SINGLE_TO_DOUBLE, 55210037SARM gem5 Developers SINGLE_TO_WORD, 55310037SARM gem5 Developers SINGLE_TO_LONG, 55411321Ssteve.reinhardt@amd.com 55510037SARM gem5 Developers DOUBLE_TO_SINGLE, 55610037SARM gem5 Developers DOUBLE_TO_WORD, 55710037SARM gem5 Developers DOUBLE_TO_LONG, 55810037SARM gem5 Developers 55910037SARM gem5 Developers LONG_TO_SINGLE, 56010037SARM gem5 Developers LONG_TO_DOUBLE, 56110037SARM gem5 Developers LONG_TO_WORD, 56210037SARM gem5 Developers LONG_TO_PS, 56310037SARM gem5 Developers 56410037SARM gem5 Developers WORD_TO_SINGLE, 56510037SARM gem5 Developers WORD_TO_DOUBLE, 56610037SARM gem5 Developers WORD_TO_LONG, 56710037SARM gem5 Developers WORD_TO_PS, 56810037SARM gem5 Developers 56910037SARM gem5 Developers PL_TO_SINGLE, 57010037SARM gem5 Developers PU_TO_SINGLE 5717396Sgblack@eecs.umich.edu }; 5727396Sgblack@eecs.umich.edu 5737396Sgblack@eecs.umich.edu //used in FP convert & round function 5747396Sgblack@eecs.umich.edu enum RoundMode{ 5757396Sgblack@eecs.umich.edu RND_ZERO, 5767396Sgblack@eecs.umich.edu RND_DOWN, 5777396Sgblack@eecs.umich.edu RND_UP, 5787396Sgblack@eecs.umich.edu RND_NEAREST 5797396Sgblack@eecs.umich.edu }; 5807396Sgblack@eecs.umich.edu 5817396Sgblack@eecs.umich.edu enum ExceptionLevel { 5827396Sgblack@eecs.umich.edu EL0 = 0, 58310037SARM gem5 Developers EL1, 58410037SARM gem5 Developers EL2, 58510037SARM gem5 Developers EL3 58610037SARM gem5 Developers }; 5877639Sgblack@eecs.umich.edu 58810037SARM gem5 Developers enum OperatingMode { 58910037SARM gem5 Developers MODE_EL0T = 0x0, 59010037SARM gem5 Developers MODE_EL1T = 0x4, 59110037SARM gem5 Developers MODE_EL1H = 0x5, 59210037SARM gem5 Developers MODE_EL2T = 0x8, 59310037SARM gem5 Developers MODE_EL2H = 0x9, 59410037SARM gem5 Developers MODE_EL3T = 0xC, 59510037SARM gem5 Developers MODE_EL3H = 0xD, 59610037SARM gem5 Developers MODE_USER = 16, 59710037SARM gem5 Developers MODE_FIQ = 17, 59810037SARM gem5 Developers MODE_IRQ = 18, 59910037SARM gem5 Developers MODE_SVC = 19, 60010037SARM gem5 Developers MODE_MON = 22, 60110037SARM gem5 Developers MODE_ABORT = 23, 60210037SARM gem5 Developers MODE_HYP = 26, 60310037SARM gem5 Developers MODE_UNDEFINED = 27, 60410037SARM gem5 Developers MODE_SYSTEM = 31, 60510037SARM gem5 Developers MODE_MAXMODE = MODE_SYSTEM 60610037SARM gem5 Developers }; 60710037SARM gem5 Developers 60810037SARM gem5 Developers enum ExceptionClass { 60910037SARM gem5 Developers EC_INVALID = -1, 61010037SARM gem5 Developers EC_UNKNOWN = 0x0, 61110037SARM gem5 Developers EC_TRAPPED_WFI_WFE = 0x1, 61210037SARM gem5 Developers EC_TRAPPED_CP15_MCR_MRC = 0x3, 61310037SARM gem5 Developers EC_TRAPPED_CP15_MCRR_MRRC = 0x4, 61410037SARM gem5 Developers EC_TRAPPED_CP14_MCR_MRC = 0x5, 61510037SARM gem5 Developers EC_TRAPPED_CP14_LDC_STC = 0x6, 61610037SARM gem5 Developers EC_TRAPPED_HCPTR = 0x7, 61710037SARM gem5 Developers EC_TRAPPED_SIMD_FP = 0x7, // AArch64 alias 61810037SARM gem5 Developers EC_TRAPPED_CP10_MRC_VMRS = 0x8, 61910037SARM gem5 Developers EC_TRAPPED_BXJ = 0xA, 62010037SARM gem5 Developers EC_TRAPPED_CP14_MCRR_MRRC = 0xC, 62110037SARM gem5 Developers EC_ILLEGAL_INST = 0xE, 62210037SARM gem5 Developers EC_SVC_TO_HYP = 0x11, 62310037SARM gem5 Developers EC_SVC = 0x11, // AArch64 alias 62410037SARM gem5 Developers EC_HVC = 0x12, 62510037SARM gem5 Developers EC_SMC_TO_HYP = 0x13, 62610037SARM gem5 Developers EC_SMC = 0x13, // AArch64 alias 62710037SARM gem5 Developers EC_SVC_64 = 0x15, 6287639Sgblack@eecs.umich.edu EC_HVC_64 = 0x16, 6297639Sgblack@eecs.umich.edu EC_SMC_64 = 0x17, 6307639Sgblack@eecs.umich.edu EC_TRAPPED_MSR_MRS_64 = 0x18, 63110037SARM gem5 Developers EC_PREFETCH_ABORT_TO_HYP = 0x20, 63210037SARM gem5 Developers EC_PREFETCH_ABORT_LOWER_EL = 0x20, // AArch64 alias 6337639Sgblack@eecs.umich.edu EC_PREFETCH_ABORT_FROM_HYP = 0x21, 63410037SARM gem5 Developers EC_PREFETCH_ABORT_CURR_EL = 0x21, // AArch64 alias 63510037SARM gem5 Developers EC_PC_ALIGNMENT = 0x22, 63610037SARM gem5 Developers EC_DATA_ABORT_TO_HYP = 0x24, 6377639Sgblack@eecs.umich.edu EC_DATA_ABORT_LOWER_EL = 0x24, // AArch64 alias 63810037SARM gem5 Developers EC_DATA_ABORT_FROM_HYP = 0x25, 63910037SARM gem5 Developers EC_DATA_ABORT_CURR_EL = 0x25, // AArch64 alias 64010037SARM gem5 Developers EC_STACK_PTR_ALIGNMENT = 0x26, 64110037SARM gem5 Developers EC_FP_EXCEPTION = 0x28, 64210037SARM gem5 Developers EC_FP_EXCEPTION_64 = 0x2C, 64310037SARM gem5 Developers EC_SERROR = 0x2F, 64410037SARM gem5 Developers EC_SOFTWARE_BREAKPOINT = 0x38, 64510037SARM gem5 Developers EC_SOFTWARE_BREAKPOINT_64 = 0x3C, 64610037SARM gem5 Developers }; 64710037SARM gem5 Developers 64810037SARM gem5 Developers /** 64910037SARM gem5 Developers * Instruction decoder fault codes in ExtMachInst. 65010037SARM gem5 Developers */ 65110037SARM gem5 Developers enum DecoderFault : std::uint8_t { 65210037SARM gem5 Developers OK = 0x0, ///< No fault 65310037SARM gem5 Developers UNALIGNED = 0x1, ///< Unaligned instruction fault 65410037SARM gem5 Developers 65510037SARM gem5 Developers PANIC = 0x3, ///< Internal gem5 error 6567639Sgblack@eecs.umich.edu }; 6577639Sgblack@eecs.umich.edu 6587639Sgblack@eecs.umich.edu BitUnion8(OperatingMode64) 65910037SARM gem5 Developers Bitfield<0> spX; 66010037SARM gem5 Developers Bitfield<3, 2> el; 66110037SARM gem5 Developers Bitfield<4> width; 66210037SARM gem5 Developers EndBitUnion(OperatingMode64) 66310037SARM gem5 Developers 66410037SARM gem5 Developers static bool inline 66510037SARM gem5 Developers opModeIs64(OperatingMode mode) 66610037SARM gem5 Developers { 66710037SARM gem5 Developers return ((OperatingMode64)(uint8_t)mode).width == 0; 66810037SARM gem5 Developers } 66910037SARM gem5 Developers 67010037SARM gem5 Developers static bool inline 67110037SARM gem5 Developers opModeIsH(OperatingMode mode) 67210037SARM gem5 Developers { 67310037SARM gem5 Developers return (mode == MODE_EL1H || mode == MODE_EL2H || mode == MODE_EL3H); 67410037SARM gem5 Developers } 67510037SARM gem5 Developers 67610037SARM gem5 Developers static bool inline 67710037SARM gem5 Developers opModeIsT(OperatingMode mode) 67810037SARM gem5 Developers { 67910037SARM gem5 Developers return (mode == MODE_EL0T || mode == MODE_EL1T || mode == MODE_EL2T || 68010037SARM gem5 Developers mode == MODE_EL3T); 68110037SARM gem5 Developers } 68210037SARM gem5 Developers 68310037SARM gem5 Developers static ExceptionLevel inline 68410037SARM gem5 Developers opModeToEL(OperatingMode mode) 68510037SARM gem5 Developers { 68610037SARM gem5 Developers bool aarch32 = ((mode >> 4) & 1) ? true : false; 68710037SARM gem5 Developers if (aarch32) { 68811321Ssteve.reinhardt@amd.com switch (mode) { 68910037SARM gem5 Developers case MODE_USER: 69010037SARM gem5 Developers return EL0; 69110037SARM gem5 Developers case MODE_FIQ: 69210037SARM gem5 Developers case MODE_IRQ: 69310037SARM gem5 Developers case MODE_SVC: 69410037SARM gem5 Developers case MODE_ABORT: 69510037SARM gem5 Developers case MODE_UNDEFINED: 69610037SARM gem5 Developers case MODE_SYSTEM: 69710037SARM gem5 Developers return EL1; 69810037SARM gem5 Developers case MODE_HYP: 69910037SARM gem5 Developers return EL2; 70010037SARM gem5 Developers case MODE_MON: 70110037SARM gem5 Developers return EL3; 70210037SARM gem5 Developers default: 70310037SARM gem5 Developers panic("Invalid operating mode: %d", mode); 70410037SARM gem5 Developers break; 70510037SARM gem5 Developers } 70610037SARM gem5 Developers } else { 70710037SARM gem5 Developers // aarch64 70810037SARM gem5 Developers return (ExceptionLevel) ((mode >> 2) & 3); 70910037SARM gem5 Developers } 71011321Ssteve.reinhardt@amd.com } 71110037SARM gem5 Developers 71210037SARM gem5 Developers static inline bool 71310037SARM gem5 Developers badMode(OperatingMode mode) 71410037SARM gem5 Developers { 71510037SARM gem5 Developers switch (mode) { 71610037SARM gem5 Developers case MODE_EL0T: 7177639Sgblack@eecs.umich.edu case MODE_EL1T: 7187639Sgblack@eecs.umich.edu case MODE_EL1H: 7197639Sgblack@eecs.umich.edu case MODE_EL2T: 7207639Sgblack@eecs.umich.edu case MODE_EL2H: 7217639Sgblack@eecs.umich.edu case MODE_EL3T: 7227639Sgblack@eecs.umich.edu case MODE_EL3H: 7237639Sgblack@eecs.umich.edu case MODE_USER: 7247639Sgblack@eecs.umich.edu case MODE_FIQ: 7257639Sgblack@eecs.umich.edu case MODE_IRQ: 7267639Sgblack@eecs.umich.edu case MODE_SVC: 7277639Sgblack@eecs.umich.edu case MODE_MON: 7287639Sgblack@eecs.umich.edu case MODE_ABORT: 7297639Sgblack@eecs.umich.edu case MODE_HYP: 7307639Sgblack@eecs.umich.edu case MODE_UNDEFINED: 7317639Sgblack@eecs.umich.edu case MODE_SYSTEM: 73211321Ssteve.reinhardt@amd.com return false; 7337639Sgblack@eecs.umich.edu default: 7347639Sgblack@eecs.umich.edu return true; 7357639Sgblack@eecs.umich.edu } 7367639Sgblack@eecs.umich.edu } 7377639Sgblack@eecs.umich.edu 7387639Sgblack@eecs.umich.edu 7397639Sgblack@eecs.umich.edu static inline bool 7407639Sgblack@eecs.umich.edu badMode32(OperatingMode mode) 7417639Sgblack@eecs.umich.edu { 7427639Sgblack@eecs.umich.edu switch (mode) { 7437639Sgblack@eecs.umich.edu case MODE_USER: 7447639Sgblack@eecs.umich.edu case MODE_FIQ: 7457639Sgblack@eecs.umich.edu case MODE_IRQ: 7467639Sgblack@eecs.umich.edu case MODE_SVC: 7477639Sgblack@eecs.umich.edu case MODE_MON: 7487639Sgblack@eecs.umich.edu case MODE_ABORT: 7497639Sgblack@eecs.umich.edu case MODE_HYP: 7507639Sgblack@eecs.umich.edu case MODE_UNDEFINED: 7517639Sgblack@eecs.umich.edu case MODE_SYSTEM: 7527639Sgblack@eecs.umich.edu return false; 75311321Ssteve.reinhardt@amd.com default: 7547639Sgblack@eecs.umich.edu return true; 7557639Sgblack@eecs.umich.edu } 7567639Sgblack@eecs.umich.edu } 7577639Sgblack@eecs.umich.edu 7587639Sgblack@eecs.umich.edu} // namespace ArmISA 7597639Sgblack@eecs.umich.edu 76010037SARM gem5 Developers#endif 76110037SARM gem5 Developers