types.hh revision 9074
16019Shines@cs.fsu.edu/* 27097Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37097Sgblack@eecs.umich.edu * All rights reserved 47097Sgblack@eecs.umich.edu * 57097Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67097Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77097Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87097Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97097Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107097Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117097Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127097Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137097Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 156019Shines@cs.fsu.edu * All rights reserved. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 266019Shines@cs.fsu.edu * this software without specific prior written permission. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019Shines@cs.fsu.edu * 406019Shines@cs.fsu.edu * Authors: Stephen Hines 416019Shines@cs.fsu.edu */ 426019Shines@cs.fsu.edu 436019Shines@cs.fsu.edu#ifndef __ARCH_ARM_TYPES_HH__ 446019Shines@cs.fsu.edu#define __ARCH_ARM_TYPES_HH__ 456019Shines@cs.fsu.edu 467720Sgblack@eecs.umich.edu#include "arch/generic/types.hh" 476251Sgblack@eecs.umich.edu#include "base/bitunion.hh" 487680Sgblack@eecs.umich.edu#include "base/hashmap.hh" 497720Sgblack@eecs.umich.edu#include "base/misc.hh" 506214Snate@binkert.org#include "base/types.hh" 519023Sgblack@eecs.umich.edu#include "debug/Decoder.hh" 526019Shines@cs.fsu.edu 536019Shines@cs.fsu.edunamespace ArmISA 546019Shines@cs.fsu.edu{ 556019Shines@cs.fsu.edu typedef uint32_t MachInst; 566251Sgblack@eecs.umich.edu 578205SAli.Saidi@ARM.com BitUnion8(ITSTATE) 588205SAli.Saidi@ARM.com /* Note that the split (cond, mask) below is not as in ARM ARM. 598205SAli.Saidi@ARM.com * But it is more convenient for simulation. The condition 608205SAli.Saidi@ARM.com * is always the concatenation of the top 3 bits and the next bit, 618205SAli.Saidi@ARM.com * which applies when one of the bottom 4 bits is set. 628205SAli.Saidi@ARM.com * Refer to predecoder.cc for the use case. 638205SAli.Saidi@ARM.com */ 648205SAli.Saidi@ARM.com Bitfield<7, 4> cond; 658205SAli.Saidi@ARM.com Bitfield<3, 0> mask; 668205SAli.Saidi@ARM.com // Bitfields for moving to/from CPSR 678205SAli.Saidi@ARM.com Bitfield<7, 2> top6; 688205SAli.Saidi@ARM.com Bitfield<1, 0> bottom2; 698205SAli.Saidi@ARM.com EndBitUnion(ITSTATE) 708205SAli.Saidi@ARM.com 718205SAli.Saidi@ARM.com 726267Sgblack@eecs.umich.edu BitUnion64(ExtMachInst) 737408Sgblack@eecs.umich.edu // ITSTATE bits 747408Sgblack@eecs.umich.edu Bitfield<55, 48> itstate; 757408Sgblack@eecs.umich.edu Bitfield<55, 52> itstateCond; 767408Sgblack@eecs.umich.edu Bitfield<51, 48> itstateMask; 777408Sgblack@eecs.umich.edu 787376Sgblack@eecs.umich.edu // FPSCR fields 797376Sgblack@eecs.umich.edu Bitfield<41, 40> fpscrStride; 807376Sgblack@eecs.umich.edu Bitfield<39, 37> fpscrLen; 817376Sgblack@eecs.umich.edu 827097Sgblack@eecs.umich.edu // Bitfields to select mode. 837097Sgblack@eecs.umich.edu Bitfield<36> thumb; 847097Sgblack@eecs.umich.edu Bitfield<35> bigThumb; 857097Sgblack@eecs.umich.edu 866267Sgblack@eecs.umich.edu // Made up bitfields that make life easier. 876267Sgblack@eecs.umich.edu Bitfield<33> sevenAndFour; 886267Sgblack@eecs.umich.edu Bitfield<32> isMisc; 896267Sgblack@eecs.umich.edu 907098Sgblack@eecs.umich.edu uint32_t instBits; 917098Sgblack@eecs.umich.edu 926251Sgblack@eecs.umich.edu // All the different types of opcode fields. 936268Sgblack@eecs.umich.edu Bitfield<27, 25> encoding; 946749Sgblack@eecs.umich.edu Bitfield<25> useImm; 956268Sgblack@eecs.umich.edu Bitfield<24, 21> opcode; 966269Sgblack@eecs.umich.edu Bitfield<24, 20> mediaOpcode; 976251Sgblack@eecs.umich.edu Bitfield<24> opcode24; 987161Sgblack@eecs.umich.edu Bitfield<24, 23> opcode24_23; 996251Sgblack@eecs.umich.edu Bitfield<23, 20> opcode23_20; 1006251Sgblack@eecs.umich.edu Bitfield<23, 21> opcode23_21; 1016743Ssaidi@eecs.umich.edu Bitfield<20> opcode20; 1026251Sgblack@eecs.umich.edu Bitfield<22> opcode22; 1037105Sgblack@eecs.umich.edu Bitfield<19, 16> opcode19_16; 1046251Sgblack@eecs.umich.edu Bitfield<19> opcode19; 1056741Sgblack@eecs.umich.edu Bitfield<18> opcode18; 1066251Sgblack@eecs.umich.edu Bitfield<15, 12> opcode15_12; 1076251Sgblack@eecs.umich.edu Bitfield<15> opcode15; 1086268Sgblack@eecs.umich.edu Bitfield<7, 4> miscOpcode; 1096759SAli.Saidi@ARM.com Bitfield<7,5> opc2; 1106251Sgblack@eecs.umich.edu Bitfield<7> opcode7; 1117105Sgblack@eecs.umich.edu Bitfield<6> opcode6; 1126251Sgblack@eecs.umich.edu Bitfield<4> opcode4; 1136251Sgblack@eecs.umich.edu 1146251Sgblack@eecs.umich.edu Bitfield<31, 28> condCode; 1156251Sgblack@eecs.umich.edu Bitfield<20> sField; 1166251Sgblack@eecs.umich.edu Bitfield<19, 16> rn; 1176251Sgblack@eecs.umich.edu Bitfield<15, 12> rd; 1187121Sgblack@eecs.umich.edu Bitfield<15, 12> rt; 1196251Sgblack@eecs.umich.edu Bitfield<11, 7> shiftSize; 1206251Sgblack@eecs.umich.edu Bitfield<6, 5> shift; 1216251Sgblack@eecs.umich.edu Bitfield<3, 0> rm; 1226251Sgblack@eecs.umich.edu 1236251Sgblack@eecs.umich.edu Bitfield<11, 8> rs; 1246251Sgblack@eecs.umich.edu 1256251Sgblack@eecs.umich.edu SubBitUnion(puswl, 24, 20) 1266251Sgblack@eecs.umich.edu Bitfield<24> prepost; 1276251Sgblack@eecs.umich.edu Bitfield<23> up; 1286251Sgblack@eecs.umich.edu Bitfield<22> psruser; 1296251Sgblack@eecs.umich.edu Bitfield<21> writeback; 1306251Sgblack@eecs.umich.edu Bitfield<20> loadOp; 1316251Sgblack@eecs.umich.edu EndSubBitUnion(puswl) 1326251Sgblack@eecs.umich.edu 1336251Sgblack@eecs.umich.edu Bitfield<24, 20> pubwl; 1346251Sgblack@eecs.umich.edu 1356275Sgblack@eecs.umich.edu Bitfield<7, 0> imm; 1366251Sgblack@eecs.umich.edu 1376251Sgblack@eecs.umich.edu Bitfield<11, 8> rotate; 1386275Sgblack@eecs.umich.edu 1396275Sgblack@eecs.umich.edu Bitfield<11, 0> immed11_0; 1406251Sgblack@eecs.umich.edu Bitfield<7, 0> immed7_0; 1416251Sgblack@eecs.umich.edu 1426251Sgblack@eecs.umich.edu Bitfield<11, 8> immedHi11_8; 1436251Sgblack@eecs.umich.edu Bitfield<3, 0> immedLo3_0; 1446251Sgblack@eecs.umich.edu 1456251Sgblack@eecs.umich.edu Bitfield<15, 0> regList; 1466251Sgblack@eecs.umich.edu 1476251Sgblack@eecs.umich.edu Bitfield<23, 0> offset; 1486251Sgblack@eecs.umich.edu 1496251Sgblack@eecs.umich.edu Bitfield<23, 0> immed23_0; 1506251Sgblack@eecs.umich.edu 1516251Sgblack@eecs.umich.edu Bitfield<11, 8> cpNum; 1526251Sgblack@eecs.umich.edu Bitfield<18, 16> fn; 1536251Sgblack@eecs.umich.edu Bitfield<14, 12> fd; 1546251Sgblack@eecs.umich.edu Bitfield<3> fpRegImm; 1556251Sgblack@eecs.umich.edu Bitfield<3, 0> fm; 1566251Sgblack@eecs.umich.edu Bitfield<2, 0> fpImm; 1576251Sgblack@eecs.umich.edu Bitfield<24, 20> punwl; 1586251Sgblack@eecs.umich.edu 1597732SAli.Saidi@ARM.com Bitfield<15, 8> m5Func; 1607103Sgblack@eecs.umich.edu 1617103Sgblack@eecs.umich.edu // 16 bit thumb bitfields 1627103Sgblack@eecs.umich.edu Bitfield<15, 13> topcode15_13; 1637103Sgblack@eecs.umich.edu Bitfield<13, 11> topcode13_11; 1647103Sgblack@eecs.umich.edu Bitfield<12, 11> topcode12_11; 1657103Sgblack@eecs.umich.edu Bitfield<12, 10> topcode12_10; 1667103Sgblack@eecs.umich.edu Bitfield<11, 9> topcode11_9; 1677103Sgblack@eecs.umich.edu Bitfield<11, 8> topcode11_8; 1687103Sgblack@eecs.umich.edu Bitfield<10, 9> topcode10_9; 1697103Sgblack@eecs.umich.edu Bitfield<10, 8> topcode10_8; 1707103Sgblack@eecs.umich.edu Bitfield<9, 6> topcode9_6; 1717103Sgblack@eecs.umich.edu Bitfield<7> topcode7; 1727103Sgblack@eecs.umich.edu Bitfield<7, 6> topcode7_6; 1737103Sgblack@eecs.umich.edu Bitfield<7, 5> topcode7_5; 1747103Sgblack@eecs.umich.edu Bitfield<7, 4> topcode7_4; 1757103Sgblack@eecs.umich.edu Bitfield<3, 0> topcode3_0; 1767106Sgblack@eecs.umich.edu 1777106Sgblack@eecs.umich.edu // 32 bit thumb bitfields 1787106Sgblack@eecs.umich.edu Bitfield<28, 27> htopcode12_11; 1797106Sgblack@eecs.umich.edu Bitfield<26, 25> htopcode10_9; 1807106Sgblack@eecs.umich.edu Bitfield<25> htopcode9; 1817106Sgblack@eecs.umich.edu Bitfield<25, 24> htopcode9_8; 1827106Sgblack@eecs.umich.edu Bitfield<25, 21> htopcode9_5; 1837106Sgblack@eecs.umich.edu Bitfield<25, 20> htopcode9_4; 1847106Sgblack@eecs.umich.edu Bitfield<24> htopcode8; 1857106Sgblack@eecs.umich.edu Bitfield<24, 23> htopcode8_7; 1867106Sgblack@eecs.umich.edu Bitfield<24, 22> htopcode8_6; 1877106Sgblack@eecs.umich.edu Bitfield<24, 21> htopcode8_5; 1887113Sgblack@eecs.umich.edu Bitfield<23> htopcode7; 1897116Sgblack@eecs.umich.edu Bitfield<23, 21> htopcode7_5; 1907245Sgblack@eecs.umich.edu Bitfield<22> htopcode6; 1917106Sgblack@eecs.umich.edu Bitfield<22, 21> htopcode6_5; 1927106Sgblack@eecs.umich.edu Bitfield<21, 20> htopcode5_4; 1937106Sgblack@eecs.umich.edu Bitfield<20> htopcode4; 1947106Sgblack@eecs.umich.edu 1957106Sgblack@eecs.umich.edu Bitfield<19, 16> htrn; 1967106Sgblack@eecs.umich.edu Bitfield<20> hts; 1977106Sgblack@eecs.umich.edu 1987106Sgblack@eecs.umich.edu Bitfield<15> ltopcode15; 1997113Sgblack@eecs.umich.edu Bitfield<11, 8> ltopcode11_8; 2007113Sgblack@eecs.umich.edu Bitfield<7, 6> ltopcode7_6; 2017106Sgblack@eecs.umich.edu Bitfield<7, 4> ltopcode7_4; 2027106Sgblack@eecs.umich.edu Bitfield<4> ltopcode4; 2037106Sgblack@eecs.umich.edu 2047106Sgblack@eecs.umich.edu Bitfield<11, 8> ltrd; 2057106Sgblack@eecs.umich.edu Bitfield<11, 8> ltcoproc; 2066251Sgblack@eecs.umich.edu EndBitUnion(ExtMachInst) 2076251Sgblack@eecs.umich.edu 2087720Sgblack@eecs.umich.edu class PCState : public GenericISA::UPCState<MachInst> 2097720Sgblack@eecs.umich.edu { 2107720Sgblack@eecs.umich.edu protected: 2117720Sgblack@eecs.umich.edu 2127720Sgblack@eecs.umich.edu typedef GenericISA::UPCState<MachInst> Base; 2137720Sgblack@eecs.umich.edu 2147720Sgblack@eecs.umich.edu enum FlagBits { 2157720Sgblack@eecs.umich.edu ThumbBit = (1 << 0), 2167720Sgblack@eecs.umich.edu JazelleBit = (1 << 1) 2177720Sgblack@eecs.umich.edu }; 2187720Sgblack@eecs.umich.edu uint8_t flags; 2197720Sgblack@eecs.umich.edu uint8_t nextFlags; 2208205SAli.Saidi@ARM.com uint8_t _itstate; 2218205SAli.Saidi@ARM.com uint8_t _nextItstate; 2228146SAli.Saidi@ARM.com uint8_t _size; 2237720Sgblack@eecs.umich.edu public: 2248205SAli.Saidi@ARM.com PCState() : flags(0), nextFlags(0), _itstate(0), _nextItstate(0) 2257720Sgblack@eecs.umich.edu {} 2267720Sgblack@eecs.umich.edu 2277720Sgblack@eecs.umich.edu void 2287720Sgblack@eecs.umich.edu set(Addr val) 2297720Sgblack@eecs.umich.edu { 2307720Sgblack@eecs.umich.edu Base::set(val); 2317720Sgblack@eecs.umich.edu npc(val + (thumb() ? 2 : 4)); 2327720Sgblack@eecs.umich.edu } 2337720Sgblack@eecs.umich.edu 2348205SAli.Saidi@ARM.com PCState(Addr val) : flags(0), nextFlags(0), _itstate(0), _nextItstate(0) 2357720Sgblack@eecs.umich.edu { set(val); } 2367720Sgblack@eecs.umich.edu 2377720Sgblack@eecs.umich.edu bool 2387720Sgblack@eecs.umich.edu thumb() const 2397720Sgblack@eecs.umich.edu { 2407720Sgblack@eecs.umich.edu return flags & ThumbBit; 2417720Sgblack@eecs.umich.edu } 2427720Sgblack@eecs.umich.edu 2437720Sgblack@eecs.umich.edu void 2447720Sgblack@eecs.umich.edu thumb(bool val) 2457720Sgblack@eecs.umich.edu { 2467720Sgblack@eecs.umich.edu if (val) 2477720Sgblack@eecs.umich.edu flags |= ThumbBit; 2487720Sgblack@eecs.umich.edu else 2497720Sgblack@eecs.umich.edu flags &= ~ThumbBit; 2507720Sgblack@eecs.umich.edu } 2517720Sgblack@eecs.umich.edu 2527720Sgblack@eecs.umich.edu bool 2537720Sgblack@eecs.umich.edu nextThumb() const 2547720Sgblack@eecs.umich.edu { 2557720Sgblack@eecs.umich.edu return nextFlags & ThumbBit; 2567720Sgblack@eecs.umich.edu } 2577720Sgblack@eecs.umich.edu 2587720Sgblack@eecs.umich.edu void 2597720Sgblack@eecs.umich.edu nextThumb(bool val) 2607720Sgblack@eecs.umich.edu { 2617720Sgblack@eecs.umich.edu if (val) 2627720Sgblack@eecs.umich.edu nextFlags |= ThumbBit; 2637720Sgblack@eecs.umich.edu else 2647720Sgblack@eecs.umich.edu nextFlags &= ~ThumbBit; 2657720Sgblack@eecs.umich.edu } 2667720Sgblack@eecs.umich.edu 2678146SAli.Saidi@ARM.com void size(uint8_t s) { _size = s; } 2688146SAli.Saidi@ARM.com uint8_t size() const { return _size; } 2698146SAli.Saidi@ARM.com 2708146SAli.Saidi@ARM.com bool 2718146SAli.Saidi@ARM.com branching() const 2728146SAli.Saidi@ARM.com { 2738146SAli.Saidi@ARM.com return ((this->pc() + this->size()) != this->npc()); 2748146SAli.Saidi@ARM.com } 2758146SAli.Saidi@ARM.com 2768146SAli.Saidi@ARM.com 2777720Sgblack@eecs.umich.edu bool 2787720Sgblack@eecs.umich.edu jazelle() const 2797720Sgblack@eecs.umich.edu { 2807720Sgblack@eecs.umich.edu return flags & JazelleBit; 2817720Sgblack@eecs.umich.edu } 2827720Sgblack@eecs.umich.edu 2837720Sgblack@eecs.umich.edu void 2847720Sgblack@eecs.umich.edu jazelle(bool val) 2857720Sgblack@eecs.umich.edu { 2867720Sgblack@eecs.umich.edu if (val) 2877720Sgblack@eecs.umich.edu flags |= JazelleBit; 2887720Sgblack@eecs.umich.edu else 2897720Sgblack@eecs.umich.edu flags &= ~JazelleBit; 2907720Sgblack@eecs.umich.edu } 2917720Sgblack@eecs.umich.edu 2927720Sgblack@eecs.umich.edu bool 2937720Sgblack@eecs.umich.edu nextJazelle() const 2947720Sgblack@eecs.umich.edu { 2957720Sgblack@eecs.umich.edu return nextFlags & JazelleBit; 2967720Sgblack@eecs.umich.edu } 2977720Sgblack@eecs.umich.edu 2987720Sgblack@eecs.umich.edu void 2997720Sgblack@eecs.umich.edu nextJazelle(bool val) 3007720Sgblack@eecs.umich.edu { 3017720Sgblack@eecs.umich.edu if (val) 3027720Sgblack@eecs.umich.edu nextFlags |= JazelleBit; 3037720Sgblack@eecs.umich.edu else 3047720Sgblack@eecs.umich.edu nextFlags &= ~JazelleBit; 3057720Sgblack@eecs.umich.edu } 3067720Sgblack@eecs.umich.edu 3077858SMatt.Horsnell@arm.com uint8_t 3088205SAli.Saidi@ARM.com itstate() const 3097858SMatt.Horsnell@arm.com { 3108205SAli.Saidi@ARM.com return _itstate; 3117858SMatt.Horsnell@arm.com } 3127858SMatt.Horsnell@arm.com 3137858SMatt.Horsnell@arm.com void 3148205SAli.Saidi@ARM.com itstate(uint8_t value) 3157858SMatt.Horsnell@arm.com { 3168205SAli.Saidi@ARM.com _itstate = value; 3177858SMatt.Horsnell@arm.com } 3187858SMatt.Horsnell@arm.com 3198205SAli.Saidi@ARM.com uint8_t 3208205SAli.Saidi@ARM.com nextItstate() const 3217858SMatt.Horsnell@arm.com { 3228205SAli.Saidi@ARM.com return _nextItstate; 3238205SAli.Saidi@ARM.com } 3248205SAli.Saidi@ARM.com 3258205SAli.Saidi@ARM.com void 3268205SAli.Saidi@ARM.com nextItstate(uint8_t value) 3278205SAli.Saidi@ARM.com { 3288205SAli.Saidi@ARM.com _nextItstate = value; 3297858SMatt.Horsnell@arm.com } 3307858SMatt.Horsnell@arm.com 3317720Sgblack@eecs.umich.edu void 3327720Sgblack@eecs.umich.edu advance() 3337720Sgblack@eecs.umich.edu { 3347720Sgblack@eecs.umich.edu Base::advance(); 3359074SAli.Saidi@ARM.com flags = nextFlags; 3367720Sgblack@eecs.umich.edu npc(pc() + (thumb() ? 2 : 4)); 3377858SMatt.Horsnell@arm.com 3388205SAli.Saidi@ARM.com if (_nextItstate) { 3398205SAli.Saidi@ARM.com _itstate = _nextItstate; 3408205SAli.Saidi@ARM.com _nextItstate = 0; 3418205SAli.Saidi@ARM.com } else if (_itstate) { 3428205SAli.Saidi@ARM.com ITSTATE it = _itstate; 3438205SAli.Saidi@ARM.com uint8_t cond_mask = it.mask; 3448205SAli.Saidi@ARM.com uint8_t thumb_cond = it.cond; 3459023Sgblack@eecs.umich.edu DPRINTF(Decoder, "Advancing ITSTATE from %#x,%#x.\n", 3468205SAli.Saidi@ARM.com thumb_cond, cond_mask); 3478205SAli.Saidi@ARM.com cond_mask <<= 1; 3488205SAli.Saidi@ARM.com uint8_t new_bit = bits(cond_mask, 4); 3498205SAli.Saidi@ARM.com cond_mask &= mask(4); 3508205SAli.Saidi@ARM.com if (cond_mask == 0) 3518205SAli.Saidi@ARM.com thumb_cond = 0; 3528205SAli.Saidi@ARM.com else 3538205SAli.Saidi@ARM.com replaceBits(thumb_cond, 0, new_bit); 3549023Sgblack@eecs.umich.edu DPRINTF(Decoder, "Advancing ITSTATE to %#x,%#x.\n", 3558205SAli.Saidi@ARM.com thumb_cond, cond_mask); 3568205SAli.Saidi@ARM.com it.mask = cond_mask; 3578205SAli.Saidi@ARM.com it.cond = thumb_cond; 3588205SAli.Saidi@ARM.com _itstate = it; 3597858SMatt.Horsnell@arm.com } 3607720Sgblack@eecs.umich.edu } 3617720Sgblack@eecs.umich.edu 3627720Sgblack@eecs.umich.edu void 3637720Sgblack@eecs.umich.edu uEnd() 3647720Sgblack@eecs.umich.edu { 3657720Sgblack@eecs.umich.edu advance(); 3667720Sgblack@eecs.umich.edu upc(0); 3677720Sgblack@eecs.umich.edu nupc(1); 3687720Sgblack@eecs.umich.edu } 3697720Sgblack@eecs.umich.edu 3707720Sgblack@eecs.umich.edu Addr 3717720Sgblack@eecs.umich.edu instPC() const 3727720Sgblack@eecs.umich.edu { 3737720Sgblack@eecs.umich.edu return pc() + (thumb() ? 4 : 8); 3747720Sgblack@eecs.umich.edu } 3757720Sgblack@eecs.umich.edu 3767720Sgblack@eecs.umich.edu void 3777720Sgblack@eecs.umich.edu instNPC(uint32_t val) 3787720Sgblack@eecs.umich.edu { 3797720Sgblack@eecs.umich.edu npc(val &~ mask(nextThumb() ? 1 : 2)); 3807720Sgblack@eecs.umich.edu } 3817720Sgblack@eecs.umich.edu 3827720Sgblack@eecs.umich.edu Addr 3837720Sgblack@eecs.umich.edu instNPC() const 3847720Sgblack@eecs.umich.edu { 3857720Sgblack@eecs.umich.edu return npc(); 3867720Sgblack@eecs.umich.edu } 3877720Sgblack@eecs.umich.edu 3887720Sgblack@eecs.umich.edu // Perform an interworking branch. 3897720Sgblack@eecs.umich.edu void 3907720Sgblack@eecs.umich.edu instIWNPC(uint32_t val) 3917720Sgblack@eecs.umich.edu { 3927720Sgblack@eecs.umich.edu bool thumbEE = (thumb() && jazelle()); 3937720Sgblack@eecs.umich.edu 3947720Sgblack@eecs.umich.edu Addr newPC = val; 3957720Sgblack@eecs.umich.edu if (thumbEE) { 3967720Sgblack@eecs.umich.edu if (bits(newPC, 0)) { 3977720Sgblack@eecs.umich.edu newPC = newPC & ~mask(1); 3988075SAli.Saidi@ARM.com } // else we have a bad interworking address; do not call 3998075SAli.Saidi@ARM.com // panic() since the instruction could be executed 4008075SAli.Saidi@ARM.com // speculatively 4017720Sgblack@eecs.umich.edu } else { 4027720Sgblack@eecs.umich.edu if (bits(newPC, 0)) { 4037720Sgblack@eecs.umich.edu nextThumb(true); 4047720Sgblack@eecs.umich.edu newPC = newPC & ~mask(1); 4057720Sgblack@eecs.umich.edu } else if (!bits(newPC, 1)) { 4067720Sgblack@eecs.umich.edu nextThumb(false); 4077720Sgblack@eecs.umich.edu } else { 4087744SAli.Saidi@ARM.com // This state is UNPREDICTABLE in the ARM architecture 4097744SAli.Saidi@ARM.com // The easy thing to do is just mask off the bit and 4107744SAli.Saidi@ARM.com // stay in the current mode, so we'll do that. 4117744SAli.Saidi@ARM.com newPC &= ~mask(2); 4127720Sgblack@eecs.umich.edu } 4137720Sgblack@eecs.umich.edu } 4147720Sgblack@eecs.umich.edu npc(newPC); 4157720Sgblack@eecs.umich.edu } 4167720Sgblack@eecs.umich.edu 4177720Sgblack@eecs.umich.edu // Perform an interworking branch in ARM mode, a regular branch 4187720Sgblack@eecs.umich.edu // otherwise. 4197720Sgblack@eecs.umich.edu void 4207720Sgblack@eecs.umich.edu instAIWNPC(uint32_t val) 4217720Sgblack@eecs.umich.edu { 4227720Sgblack@eecs.umich.edu if (!thumb() && !jazelle()) 4237720Sgblack@eecs.umich.edu instIWNPC(val); 4247720Sgblack@eecs.umich.edu else 4257720Sgblack@eecs.umich.edu instNPC(val); 4267720Sgblack@eecs.umich.edu } 4277720Sgblack@eecs.umich.edu 4287720Sgblack@eecs.umich.edu bool 4297720Sgblack@eecs.umich.edu operator == (const PCState &opc) const 4307720Sgblack@eecs.umich.edu { 4317720Sgblack@eecs.umich.edu return Base::operator == (opc) && 4328205SAli.Saidi@ARM.com flags == opc.flags && nextFlags == opc.nextFlags && 4338205SAli.Saidi@ARM.com _itstate == opc._itstate && _nextItstate == opc._nextItstate; 4347720Sgblack@eecs.umich.edu } 4357720Sgblack@eecs.umich.edu 4368361Sksewell@umich.edu bool 4378361Sksewell@umich.edu operator != (const PCState &opc) const 4388361Sksewell@umich.edu { 4398361Sksewell@umich.edu return !(*this == opc); 4408361Sksewell@umich.edu } 4418361Sksewell@umich.edu 4427720Sgblack@eecs.umich.edu void 4437720Sgblack@eecs.umich.edu serialize(std::ostream &os) 4447720Sgblack@eecs.umich.edu { 4457720Sgblack@eecs.umich.edu Base::serialize(os); 4467720Sgblack@eecs.umich.edu SERIALIZE_SCALAR(flags); 4478146SAli.Saidi@ARM.com SERIALIZE_SCALAR(_size); 4487720Sgblack@eecs.umich.edu SERIALIZE_SCALAR(nextFlags); 4498205SAli.Saidi@ARM.com SERIALIZE_SCALAR(_itstate); 4508205SAli.Saidi@ARM.com SERIALIZE_SCALAR(_nextItstate); 4517720Sgblack@eecs.umich.edu } 4527720Sgblack@eecs.umich.edu 4537720Sgblack@eecs.umich.edu void 4547720Sgblack@eecs.umich.edu unserialize(Checkpoint *cp, const std::string §ion) 4557720Sgblack@eecs.umich.edu { 4567720Sgblack@eecs.umich.edu Base::unserialize(cp, section); 4577720Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(flags); 4588146SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(_size); 4597720Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(nextFlags); 4608205SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(_itstate); 4618205SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(_nextItstate); 4627720Sgblack@eecs.umich.edu } 4637720Sgblack@eecs.umich.edu }; 4647720Sgblack@eecs.umich.edu 4656254Sgblack@eecs.umich.edu // Shift types for ARM instructions 4666254Sgblack@eecs.umich.edu enum ArmShiftType { 4676254Sgblack@eecs.umich.edu LSL = 0, 4686254Sgblack@eecs.umich.edu LSR, 4696254Sgblack@eecs.umich.edu ASR, 4706254Sgblack@eecs.umich.edu ROR 4716254Sgblack@eecs.umich.edu }; 4726254Sgblack@eecs.umich.edu 4736019Shines@cs.fsu.edu typedef uint64_t LargestRead; 4746019Shines@cs.fsu.edu // Need to use 64 bits to make sure that read requests get handled properly 4756019Shines@cs.fsu.edu 4766019Shines@cs.fsu.edu typedef int RegContextParam; 4776019Shines@cs.fsu.edu typedef int RegContextVal; 4786019Shines@cs.fsu.edu 4796019Shines@cs.fsu.edu //used in FP convert & round function 4806019Shines@cs.fsu.edu enum ConvertType{ 4816019Shines@cs.fsu.edu SINGLE_TO_DOUBLE, 4826019Shines@cs.fsu.edu SINGLE_TO_WORD, 4836019Shines@cs.fsu.edu SINGLE_TO_LONG, 4846019Shines@cs.fsu.edu 4856019Shines@cs.fsu.edu DOUBLE_TO_SINGLE, 4866019Shines@cs.fsu.edu DOUBLE_TO_WORD, 4876019Shines@cs.fsu.edu DOUBLE_TO_LONG, 4886019Shines@cs.fsu.edu 4896019Shines@cs.fsu.edu LONG_TO_SINGLE, 4906019Shines@cs.fsu.edu LONG_TO_DOUBLE, 4916019Shines@cs.fsu.edu LONG_TO_WORD, 4926019Shines@cs.fsu.edu LONG_TO_PS, 4936019Shines@cs.fsu.edu 4946019Shines@cs.fsu.edu WORD_TO_SINGLE, 4956019Shines@cs.fsu.edu WORD_TO_DOUBLE, 4966019Shines@cs.fsu.edu WORD_TO_LONG, 4976019Shines@cs.fsu.edu WORD_TO_PS, 4986019Shines@cs.fsu.edu 4996019Shines@cs.fsu.edu PL_TO_SINGLE, 5006019Shines@cs.fsu.edu PU_TO_SINGLE 5016019Shines@cs.fsu.edu }; 5026019Shines@cs.fsu.edu 5036019Shines@cs.fsu.edu //used in FP convert & round function 5046019Shines@cs.fsu.edu enum RoundMode{ 5056019Shines@cs.fsu.edu RND_ZERO, 5066019Shines@cs.fsu.edu RND_DOWN, 5076019Shines@cs.fsu.edu RND_UP, 5086019Shines@cs.fsu.edu RND_NEAREST 5096019Shines@cs.fsu.edu }; 5106019Shines@cs.fsu.edu 5116019Shines@cs.fsu.edu enum OperatingMode { 5126019Shines@cs.fsu.edu MODE_USER = 16, 5136019Shines@cs.fsu.edu MODE_FIQ = 17, 5146019Shines@cs.fsu.edu MODE_IRQ = 18, 5156019Shines@cs.fsu.edu MODE_SVC = 19, 5166723Sgblack@eecs.umich.edu MODE_MON = 22, 5176019Shines@cs.fsu.edu MODE_ABORT = 23, 5186019Shines@cs.fsu.edu MODE_UNDEFINED = 27, 5197498Sgblack@eecs.umich.edu MODE_SYSTEM = 31, 5207498Sgblack@eecs.umich.edu MODE_MAXMODE = MODE_SYSTEM 5216019Shines@cs.fsu.edu }; 5226019Shines@cs.fsu.edu 5237311Sgblack@eecs.umich.edu static inline bool 5247311Sgblack@eecs.umich.edu badMode(OperatingMode mode) 5257311Sgblack@eecs.umich.edu { 5267311Sgblack@eecs.umich.edu switch (mode) { 5277311Sgblack@eecs.umich.edu case MODE_USER: 5287311Sgblack@eecs.umich.edu case MODE_FIQ: 5297311Sgblack@eecs.umich.edu case MODE_IRQ: 5307311Sgblack@eecs.umich.edu case MODE_SVC: 5317311Sgblack@eecs.umich.edu case MODE_MON: 5327311Sgblack@eecs.umich.edu case MODE_ABORT: 5337311Sgblack@eecs.umich.edu case MODE_UNDEFINED: 5347311Sgblack@eecs.umich.edu case MODE_SYSTEM: 5357311Sgblack@eecs.umich.edu return false; 5367311Sgblack@eecs.umich.edu default: 5377311Sgblack@eecs.umich.edu return true; 5387311Sgblack@eecs.umich.edu } 5397311Sgblack@eecs.umich.edu } 5407311Sgblack@eecs.umich.edu 5416019Shines@cs.fsu.edu} // namespace ArmISA 5426019Shines@cs.fsu.edu 5438946Sandreas.hansson@arm.com__hash_namespace_begin 5447680Sgblack@eecs.umich.edu template<> 5457680Sgblack@eecs.umich.edu struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> { 5467680Sgblack@eecs.umich.edu size_t operator()(const ArmISA::ExtMachInst &emi) const { 5477680Sgblack@eecs.umich.edu return hash<uint32_t>::operator()((uint32_t)emi); 5487680Sgblack@eecs.umich.edu }; 5497680Sgblack@eecs.umich.edu }; 5508946Sandreas.hansson@arm.com__hash_namespace_end 5517680Sgblack@eecs.umich.edu 5526019Shines@cs.fsu.edu#endif 553