types.hh revision 8146
16019Shines@cs.fsu.edu/* 27097Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37097Sgblack@eecs.umich.edu * All rights reserved 47097Sgblack@eecs.umich.edu * 57097Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67097Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77097Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87097Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97097Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107097Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117097Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127097Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137097Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 156019Shines@cs.fsu.edu * All rights reserved. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 266019Shines@cs.fsu.edu * this software without specific prior written permission. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019Shines@cs.fsu.edu * 406019Shines@cs.fsu.edu * Authors: Stephen Hines 416019Shines@cs.fsu.edu */ 426019Shines@cs.fsu.edu 436019Shines@cs.fsu.edu#ifndef __ARCH_ARM_TYPES_HH__ 446019Shines@cs.fsu.edu#define __ARCH_ARM_TYPES_HH__ 456019Shines@cs.fsu.edu 467720Sgblack@eecs.umich.edu#include "arch/generic/types.hh" 476251Sgblack@eecs.umich.edu#include "base/bitunion.hh" 487680Sgblack@eecs.umich.edu#include "base/hashmap.hh" 497720Sgblack@eecs.umich.edu#include "base/misc.hh" 506214Snate@binkert.org#include "base/types.hh" 516019Shines@cs.fsu.edu 526019Shines@cs.fsu.edunamespace ArmISA 536019Shines@cs.fsu.edu{ 546019Shines@cs.fsu.edu typedef uint32_t MachInst; 556251Sgblack@eecs.umich.edu 566267Sgblack@eecs.umich.edu BitUnion64(ExtMachInst) 577408Sgblack@eecs.umich.edu Bitfield<63, 56> newItstate; 587408Sgblack@eecs.umich.edu // ITSTATE bits 597408Sgblack@eecs.umich.edu Bitfield<55, 48> itstate; 607408Sgblack@eecs.umich.edu Bitfield<55, 52> itstateCond; 617408Sgblack@eecs.umich.edu Bitfield<51, 48> itstateMask; 627408Sgblack@eecs.umich.edu 637376Sgblack@eecs.umich.edu // FPSCR fields 647376Sgblack@eecs.umich.edu Bitfield<41, 40> fpscrStride; 657376Sgblack@eecs.umich.edu Bitfield<39, 37> fpscrLen; 667376Sgblack@eecs.umich.edu 677097Sgblack@eecs.umich.edu // Bitfields to select mode. 687097Sgblack@eecs.umich.edu Bitfield<36> thumb; 697097Sgblack@eecs.umich.edu Bitfield<35> bigThumb; 707097Sgblack@eecs.umich.edu 716267Sgblack@eecs.umich.edu // Made up bitfields that make life easier. 726267Sgblack@eecs.umich.edu Bitfield<33> sevenAndFour; 736267Sgblack@eecs.umich.edu Bitfield<32> isMisc; 746267Sgblack@eecs.umich.edu 757098Sgblack@eecs.umich.edu uint32_t instBits; 767098Sgblack@eecs.umich.edu 776251Sgblack@eecs.umich.edu // All the different types of opcode fields. 786268Sgblack@eecs.umich.edu Bitfield<27, 25> encoding; 796749Sgblack@eecs.umich.edu Bitfield<25> useImm; 806268Sgblack@eecs.umich.edu Bitfield<24, 21> opcode; 816269Sgblack@eecs.umich.edu Bitfield<24, 20> mediaOpcode; 826251Sgblack@eecs.umich.edu Bitfield<24> opcode24; 837161Sgblack@eecs.umich.edu Bitfield<24, 23> opcode24_23; 846251Sgblack@eecs.umich.edu Bitfield<23, 20> opcode23_20; 856251Sgblack@eecs.umich.edu Bitfield<23, 21> opcode23_21; 866743Ssaidi@eecs.umich.edu Bitfield<20> opcode20; 876251Sgblack@eecs.umich.edu Bitfield<22> opcode22; 887105Sgblack@eecs.umich.edu Bitfield<19, 16> opcode19_16; 896251Sgblack@eecs.umich.edu Bitfield<19> opcode19; 906741Sgblack@eecs.umich.edu Bitfield<18> opcode18; 916251Sgblack@eecs.umich.edu Bitfield<15, 12> opcode15_12; 926251Sgblack@eecs.umich.edu Bitfield<15> opcode15; 936268Sgblack@eecs.umich.edu Bitfield<7, 4> miscOpcode; 946759SAli.Saidi@ARM.com Bitfield<7,5> opc2; 956251Sgblack@eecs.umich.edu Bitfield<7> opcode7; 967105Sgblack@eecs.umich.edu Bitfield<6> opcode6; 976251Sgblack@eecs.umich.edu Bitfield<4> opcode4; 986251Sgblack@eecs.umich.edu 996251Sgblack@eecs.umich.edu Bitfield<31, 28> condCode; 1006251Sgblack@eecs.umich.edu Bitfield<20> sField; 1016251Sgblack@eecs.umich.edu Bitfield<19, 16> rn; 1026251Sgblack@eecs.umich.edu Bitfield<15, 12> rd; 1037121Sgblack@eecs.umich.edu Bitfield<15, 12> rt; 1046251Sgblack@eecs.umich.edu Bitfield<11, 7> shiftSize; 1056251Sgblack@eecs.umich.edu Bitfield<6, 5> shift; 1066251Sgblack@eecs.umich.edu Bitfield<3, 0> rm; 1076251Sgblack@eecs.umich.edu 1086251Sgblack@eecs.umich.edu Bitfield<11, 8> rs; 1096251Sgblack@eecs.umich.edu 1106251Sgblack@eecs.umich.edu SubBitUnion(puswl, 24, 20) 1116251Sgblack@eecs.umich.edu Bitfield<24> prepost; 1126251Sgblack@eecs.umich.edu Bitfield<23> up; 1136251Sgblack@eecs.umich.edu Bitfield<22> psruser; 1146251Sgblack@eecs.umich.edu Bitfield<21> writeback; 1156251Sgblack@eecs.umich.edu Bitfield<20> loadOp; 1166251Sgblack@eecs.umich.edu EndSubBitUnion(puswl) 1176251Sgblack@eecs.umich.edu 1186251Sgblack@eecs.umich.edu Bitfield<24, 20> pubwl; 1196251Sgblack@eecs.umich.edu 1206275Sgblack@eecs.umich.edu Bitfield<7, 0> imm; 1216251Sgblack@eecs.umich.edu 1226251Sgblack@eecs.umich.edu Bitfield<11, 8> rotate; 1236275Sgblack@eecs.umich.edu 1246275Sgblack@eecs.umich.edu Bitfield<11, 0> immed11_0; 1256251Sgblack@eecs.umich.edu Bitfield<7, 0> immed7_0; 1266251Sgblack@eecs.umich.edu 1276251Sgblack@eecs.umich.edu Bitfield<11, 8> immedHi11_8; 1286251Sgblack@eecs.umich.edu Bitfield<3, 0> immedLo3_0; 1296251Sgblack@eecs.umich.edu 1306251Sgblack@eecs.umich.edu Bitfield<15, 0> regList; 1316251Sgblack@eecs.umich.edu 1326251Sgblack@eecs.umich.edu Bitfield<23, 0> offset; 1336251Sgblack@eecs.umich.edu 1346251Sgblack@eecs.umich.edu Bitfield<23, 0> immed23_0; 1356251Sgblack@eecs.umich.edu 1366251Sgblack@eecs.umich.edu Bitfield<11, 8> cpNum; 1376251Sgblack@eecs.umich.edu Bitfield<18, 16> fn; 1386251Sgblack@eecs.umich.edu Bitfield<14, 12> fd; 1396251Sgblack@eecs.umich.edu Bitfield<3> fpRegImm; 1406251Sgblack@eecs.umich.edu Bitfield<3, 0> fm; 1416251Sgblack@eecs.umich.edu Bitfield<2, 0> fpImm; 1426251Sgblack@eecs.umich.edu Bitfield<24, 20> punwl; 1436251Sgblack@eecs.umich.edu 1447732SAli.Saidi@ARM.com Bitfield<15, 8> m5Func; 1457103Sgblack@eecs.umich.edu 1467103Sgblack@eecs.umich.edu // 16 bit thumb bitfields 1477103Sgblack@eecs.umich.edu Bitfield<15, 13> topcode15_13; 1487103Sgblack@eecs.umich.edu Bitfield<13, 11> topcode13_11; 1497103Sgblack@eecs.umich.edu Bitfield<12, 11> topcode12_11; 1507103Sgblack@eecs.umich.edu Bitfield<12, 10> topcode12_10; 1517103Sgblack@eecs.umich.edu Bitfield<11, 9> topcode11_9; 1527103Sgblack@eecs.umich.edu Bitfield<11, 8> topcode11_8; 1537103Sgblack@eecs.umich.edu Bitfield<10, 9> topcode10_9; 1547103Sgblack@eecs.umich.edu Bitfield<10, 8> topcode10_8; 1557103Sgblack@eecs.umich.edu Bitfield<9, 6> topcode9_6; 1567103Sgblack@eecs.umich.edu Bitfield<7> topcode7; 1577103Sgblack@eecs.umich.edu Bitfield<7, 6> topcode7_6; 1587103Sgblack@eecs.umich.edu Bitfield<7, 5> topcode7_5; 1597103Sgblack@eecs.umich.edu Bitfield<7, 4> topcode7_4; 1607103Sgblack@eecs.umich.edu Bitfield<3, 0> topcode3_0; 1617106Sgblack@eecs.umich.edu 1627106Sgblack@eecs.umich.edu // 32 bit thumb bitfields 1637106Sgblack@eecs.umich.edu Bitfield<28, 27> htopcode12_11; 1647106Sgblack@eecs.umich.edu Bitfield<26, 25> htopcode10_9; 1657106Sgblack@eecs.umich.edu Bitfield<25> htopcode9; 1667106Sgblack@eecs.umich.edu Bitfield<25, 24> htopcode9_8; 1677106Sgblack@eecs.umich.edu Bitfield<25, 21> htopcode9_5; 1687106Sgblack@eecs.umich.edu Bitfield<25, 20> htopcode9_4; 1697106Sgblack@eecs.umich.edu Bitfield<24> htopcode8; 1707106Sgblack@eecs.umich.edu Bitfield<24, 23> htopcode8_7; 1717106Sgblack@eecs.umich.edu Bitfield<24, 22> htopcode8_6; 1727106Sgblack@eecs.umich.edu Bitfield<24, 21> htopcode8_5; 1737113Sgblack@eecs.umich.edu Bitfield<23> htopcode7; 1747116Sgblack@eecs.umich.edu Bitfield<23, 21> htopcode7_5; 1757245Sgblack@eecs.umich.edu Bitfield<22> htopcode6; 1767106Sgblack@eecs.umich.edu Bitfield<22, 21> htopcode6_5; 1777106Sgblack@eecs.umich.edu Bitfield<21, 20> htopcode5_4; 1787106Sgblack@eecs.umich.edu Bitfield<20> htopcode4; 1797106Sgblack@eecs.umich.edu 1807106Sgblack@eecs.umich.edu Bitfield<19, 16> htrn; 1817106Sgblack@eecs.umich.edu Bitfield<20> hts; 1827106Sgblack@eecs.umich.edu 1837106Sgblack@eecs.umich.edu Bitfield<15> ltopcode15; 1847113Sgblack@eecs.umich.edu Bitfield<11, 8> ltopcode11_8; 1857113Sgblack@eecs.umich.edu Bitfield<7, 6> ltopcode7_6; 1867106Sgblack@eecs.umich.edu Bitfield<7, 4> ltopcode7_4; 1877106Sgblack@eecs.umich.edu Bitfield<4> ltopcode4; 1887106Sgblack@eecs.umich.edu 1897106Sgblack@eecs.umich.edu Bitfield<11, 8> ltrd; 1907106Sgblack@eecs.umich.edu Bitfield<11, 8> ltcoproc; 1916251Sgblack@eecs.umich.edu EndBitUnion(ExtMachInst) 1926251Sgblack@eecs.umich.edu 1937720Sgblack@eecs.umich.edu class PCState : public GenericISA::UPCState<MachInst> 1947720Sgblack@eecs.umich.edu { 1957720Sgblack@eecs.umich.edu protected: 1967720Sgblack@eecs.umich.edu 1977720Sgblack@eecs.umich.edu typedef GenericISA::UPCState<MachInst> Base; 1987720Sgblack@eecs.umich.edu 1997720Sgblack@eecs.umich.edu enum FlagBits { 2007720Sgblack@eecs.umich.edu ThumbBit = (1 << 0), 2017720Sgblack@eecs.umich.edu JazelleBit = (1 << 1) 2027720Sgblack@eecs.umich.edu }; 2037720Sgblack@eecs.umich.edu uint8_t flags; 2047720Sgblack@eecs.umich.edu uint8_t nextFlags; 2057858SMatt.Horsnell@arm.com uint8_t forcedItStateValue; 2068146SAli.Saidi@ARM.com uint8_t _size; 2077858SMatt.Horsnell@arm.com bool forcedItStateValid; 2087720Sgblack@eecs.umich.edu public: 2097858SMatt.Horsnell@arm.com PCState() : flags(0), nextFlags(0), forcedItStateValue(0), forcedItStateValid(false) 2107720Sgblack@eecs.umich.edu {} 2117720Sgblack@eecs.umich.edu 2127720Sgblack@eecs.umich.edu void 2137720Sgblack@eecs.umich.edu set(Addr val) 2147720Sgblack@eecs.umich.edu { 2157720Sgblack@eecs.umich.edu Base::set(val); 2167720Sgblack@eecs.umich.edu npc(val + (thumb() ? 2 : 4)); 2177720Sgblack@eecs.umich.edu } 2187720Sgblack@eecs.umich.edu 2197858SMatt.Horsnell@arm.com PCState(Addr val) : flags(0), nextFlags(0), forcedItStateValue(0), forcedItStateValid(false) 2207720Sgblack@eecs.umich.edu { set(val); } 2217720Sgblack@eecs.umich.edu 2227720Sgblack@eecs.umich.edu bool 2237720Sgblack@eecs.umich.edu thumb() const 2247720Sgblack@eecs.umich.edu { 2257720Sgblack@eecs.umich.edu return flags & ThumbBit; 2267720Sgblack@eecs.umich.edu } 2277720Sgblack@eecs.umich.edu 2287720Sgblack@eecs.umich.edu void 2297720Sgblack@eecs.umich.edu thumb(bool val) 2307720Sgblack@eecs.umich.edu { 2317720Sgblack@eecs.umich.edu if (val) 2327720Sgblack@eecs.umich.edu flags |= ThumbBit; 2337720Sgblack@eecs.umich.edu else 2347720Sgblack@eecs.umich.edu flags &= ~ThumbBit; 2357720Sgblack@eecs.umich.edu } 2367720Sgblack@eecs.umich.edu 2377720Sgblack@eecs.umich.edu bool 2387720Sgblack@eecs.umich.edu nextThumb() const 2397720Sgblack@eecs.umich.edu { 2407720Sgblack@eecs.umich.edu return nextFlags & ThumbBit; 2417720Sgblack@eecs.umich.edu } 2427720Sgblack@eecs.umich.edu 2437720Sgblack@eecs.umich.edu void 2447720Sgblack@eecs.umich.edu nextThumb(bool val) 2457720Sgblack@eecs.umich.edu { 2467720Sgblack@eecs.umich.edu if (val) 2477720Sgblack@eecs.umich.edu nextFlags |= ThumbBit; 2487720Sgblack@eecs.umich.edu else 2497720Sgblack@eecs.umich.edu nextFlags &= ~ThumbBit; 2507720Sgblack@eecs.umich.edu } 2517720Sgblack@eecs.umich.edu 2528146SAli.Saidi@ARM.com void size(uint8_t s) { _size = s; } 2538146SAli.Saidi@ARM.com uint8_t size() const { return _size; } 2548146SAli.Saidi@ARM.com 2558146SAli.Saidi@ARM.com bool 2568146SAli.Saidi@ARM.com branching() const 2578146SAli.Saidi@ARM.com { 2588146SAli.Saidi@ARM.com return ((this->pc() + this->size()) != this->npc()); 2598146SAli.Saidi@ARM.com } 2608146SAli.Saidi@ARM.com 2618146SAli.Saidi@ARM.com 2627720Sgblack@eecs.umich.edu bool 2637720Sgblack@eecs.umich.edu jazelle() const 2647720Sgblack@eecs.umich.edu { 2657720Sgblack@eecs.umich.edu return flags & JazelleBit; 2667720Sgblack@eecs.umich.edu } 2677720Sgblack@eecs.umich.edu 2687720Sgblack@eecs.umich.edu void 2697720Sgblack@eecs.umich.edu jazelle(bool val) 2707720Sgblack@eecs.umich.edu { 2717720Sgblack@eecs.umich.edu if (val) 2727720Sgblack@eecs.umich.edu flags |= JazelleBit; 2737720Sgblack@eecs.umich.edu else 2747720Sgblack@eecs.umich.edu flags &= ~JazelleBit; 2757720Sgblack@eecs.umich.edu } 2767720Sgblack@eecs.umich.edu 2777720Sgblack@eecs.umich.edu bool 2787720Sgblack@eecs.umich.edu nextJazelle() const 2797720Sgblack@eecs.umich.edu { 2807720Sgblack@eecs.umich.edu return nextFlags & JazelleBit; 2817720Sgblack@eecs.umich.edu } 2827720Sgblack@eecs.umich.edu 2837720Sgblack@eecs.umich.edu void 2847720Sgblack@eecs.umich.edu nextJazelle(bool val) 2857720Sgblack@eecs.umich.edu { 2867720Sgblack@eecs.umich.edu if (val) 2877720Sgblack@eecs.umich.edu nextFlags |= JazelleBit; 2887720Sgblack@eecs.umich.edu else 2897720Sgblack@eecs.umich.edu nextFlags &= ~JazelleBit; 2907720Sgblack@eecs.umich.edu } 2917720Sgblack@eecs.umich.edu 2927858SMatt.Horsnell@arm.com uint8_t 2937858SMatt.Horsnell@arm.com forcedItState() const 2947858SMatt.Horsnell@arm.com { 2957858SMatt.Horsnell@arm.com return forcedItStateValue; 2967858SMatt.Horsnell@arm.com } 2977858SMatt.Horsnell@arm.com 2987858SMatt.Horsnell@arm.com void 2997858SMatt.Horsnell@arm.com forcedItState(uint8_t value) 3007858SMatt.Horsnell@arm.com { 3017858SMatt.Horsnell@arm.com forcedItStateValue = value; 3027858SMatt.Horsnell@arm.com // Not valid unless the advance is called. 3037858SMatt.Horsnell@arm.com forcedItStateValid = false; 3047858SMatt.Horsnell@arm.com } 3057858SMatt.Horsnell@arm.com 3067858SMatt.Horsnell@arm.com bool 3077858SMatt.Horsnell@arm.com forcedItStateIsValid() const 3087858SMatt.Horsnell@arm.com { 3097858SMatt.Horsnell@arm.com return forcedItStateValid; 3107858SMatt.Horsnell@arm.com } 3117858SMatt.Horsnell@arm.com 3127720Sgblack@eecs.umich.edu void 3137720Sgblack@eecs.umich.edu advance() 3147720Sgblack@eecs.umich.edu { 3157720Sgblack@eecs.umich.edu Base::advance(); 3167720Sgblack@eecs.umich.edu npc(pc() + (thumb() ? 2 : 4)); 3177720Sgblack@eecs.umich.edu flags = nextFlags; 3187858SMatt.Horsnell@arm.com 3197858SMatt.Horsnell@arm.com // Validate the itState 3207858SMatt.Horsnell@arm.com if (forcedItStateValue != 0 && !forcedItStateValid) { 3217858SMatt.Horsnell@arm.com forcedItStateValid = true; 3227858SMatt.Horsnell@arm.com } else { 3237858SMatt.Horsnell@arm.com forcedItStateValid = false; 3247858SMatt.Horsnell@arm.com forcedItStateValue = 0; 3257858SMatt.Horsnell@arm.com } 3267720Sgblack@eecs.umich.edu } 3277720Sgblack@eecs.umich.edu 3287720Sgblack@eecs.umich.edu void 3297720Sgblack@eecs.umich.edu uEnd() 3307720Sgblack@eecs.umich.edu { 3317720Sgblack@eecs.umich.edu advance(); 3327720Sgblack@eecs.umich.edu upc(0); 3337720Sgblack@eecs.umich.edu nupc(1); 3347720Sgblack@eecs.umich.edu } 3357720Sgblack@eecs.umich.edu 3367720Sgblack@eecs.umich.edu Addr 3377720Sgblack@eecs.umich.edu instPC() const 3387720Sgblack@eecs.umich.edu { 3397720Sgblack@eecs.umich.edu return pc() + (thumb() ? 4 : 8); 3407720Sgblack@eecs.umich.edu } 3417720Sgblack@eecs.umich.edu 3427720Sgblack@eecs.umich.edu void 3437720Sgblack@eecs.umich.edu instNPC(uint32_t val) 3447720Sgblack@eecs.umich.edu { 3457720Sgblack@eecs.umich.edu npc(val &~ mask(nextThumb() ? 1 : 2)); 3467720Sgblack@eecs.umich.edu } 3477720Sgblack@eecs.umich.edu 3487720Sgblack@eecs.umich.edu Addr 3497720Sgblack@eecs.umich.edu instNPC() const 3507720Sgblack@eecs.umich.edu { 3517720Sgblack@eecs.umich.edu return npc(); 3527720Sgblack@eecs.umich.edu } 3537720Sgblack@eecs.umich.edu 3547720Sgblack@eecs.umich.edu // Perform an interworking branch. 3557720Sgblack@eecs.umich.edu void 3567720Sgblack@eecs.umich.edu instIWNPC(uint32_t val) 3577720Sgblack@eecs.umich.edu { 3587720Sgblack@eecs.umich.edu bool thumbEE = (thumb() && jazelle()); 3597720Sgblack@eecs.umich.edu 3607720Sgblack@eecs.umich.edu Addr newPC = val; 3617720Sgblack@eecs.umich.edu if (thumbEE) { 3627720Sgblack@eecs.umich.edu if (bits(newPC, 0)) { 3637720Sgblack@eecs.umich.edu newPC = newPC & ~mask(1); 3648075SAli.Saidi@ARM.com } // else we have a bad interworking address; do not call 3658075SAli.Saidi@ARM.com // panic() since the instruction could be executed 3668075SAli.Saidi@ARM.com // speculatively 3677720Sgblack@eecs.umich.edu } else { 3687720Sgblack@eecs.umich.edu if (bits(newPC, 0)) { 3697720Sgblack@eecs.umich.edu nextThumb(true); 3707720Sgblack@eecs.umich.edu newPC = newPC & ~mask(1); 3717720Sgblack@eecs.umich.edu } else if (!bits(newPC, 1)) { 3727720Sgblack@eecs.umich.edu nextThumb(false); 3737720Sgblack@eecs.umich.edu } else { 3747744SAli.Saidi@ARM.com // This state is UNPREDICTABLE in the ARM architecture 3757744SAli.Saidi@ARM.com // The easy thing to do is just mask off the bit and 3767744SAli.Saidi@ARM.com // stay in the current mode, so we'll do that. 3777744SAli.Saidi@ARM.com newPC &= ~mask(2); 3787720Sgblack@eecs.umich.edu } 3797720Sgblack@eecs.umich.edu } 3807720Sgblack@eecs.umich.edu npc(newPC); 3817720Sgblack@eecs.umich.edu } 3827720Sgblack@eecs.umich.edu 3837720Sgblack@eecs.umich.edu // Perform an interworking branch in ARM mode, a regular branch 3847720Sgblack@eecs.umich.edu // otherwise. 3857720Sgblack@eecs.umich.edu void 3867720Sgblack@eecs.umich.edu instAIWNPC(uint32_t val) 3877720Sgblack@eecs.umich.edu { 3887720Sgblack@eecs.umich.edu if (!thumb() && !jazelle()) 3897720Sgblack@eecs.umich.edu instIWNPC(val); 3907720Sgblack@eecs.umich.edu else 3917720Sgblack@eecs.umich.edu instNPC(val); 3927720Sgblack@eecs.umich.edu } 3937720Sgblack@eecs.umich.edu 3947720Sgblack@eecs.umich.edu bool 3957720Sgblack@eecs.umich.edu operator == (const PCState &opc) const 3967720Sgblack@eecs.umich.edu { 3977720Sgblack@eecs.umich.edu return Base::operator == (opc) && 3987720Sgblack@eecs.umich.edu flags == opc.flags && nextFlags == opc.nextFlags; 3997720Sgblack@eecs.umich.edu } 4007720Sgblack@eecs.umich.edu 4017720Sgblack@eecs.umich.edu void 4027720Sgblack@eecs.umich.edu serialize(std::ostream &os) 4037720Sgblack@eecs.umich.edu { 4047720Sgblack@eecs.umich.edu Base::serialize(os); 4057720Sgblack@eecs.umich.edu SERIALIZE_SCALAR(flags); 4068146SAli.Saidi@ARM.com SERIALIZE_SCALAR(_size); 4077720Sgblack@eecs.umich.edu SERIALIZE_SCALAR(nextFlags); 4087858SMatt.Horsnell@arm.com SERIALIZE_SCALAR(forcedItStateValue); 4097858SMatt.Horsnell@arm.com SERIALIZE_SCALAR(forcedItStateValid); 4107720Sgblack@eecs.umich.edu } 4117720Sgblack@eecs.umich.edu 4127720Sgblack@eecs.umich.edu void 4137720Sgblack@eecs.umich.edu unserialize(Checkpoint *cp, const std::string §ion) 4147720Sgblack@eecs.umich.edu { 4157720Sgblack@eecs.umich.edu Base::unserialize(cp, section); 4167720Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(flags); 4178146SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(_size); 4187720Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(nextFlags); 4197858SMatt.Horsnell@arm.com UNSERIALIZE_SCALAR(forcedItStateValue); 4207858SMatt.Horsnell@arm.com UNSERIALIZE_SCALAR(forcedItStateValid); 4217720Sgblack@eecs.umich.edu } 4227720Sgblack@eecs.umich.edu }; 4237720Sgblack@eecs.umich.edu 4246254Sgblack@eecs.umich.edu // Shift types for ARM instructions 4256254Sgblack@eecs.umich.edu enum ArmShiftType { 4266254Sgblack@eecs.umich.edu LSL = 0, 4276254Sgblack@eecs.umich.edu LSR, 4286254Sgblack@eecs.umich.edu ASR, 4296254Sgblack@eecs.umich.edu ROR 4306254Sgblack@eecs.umich.edu }; 4316254Sgblack@eecs.umich.edu 4326019Shines@cs.fsu.edu typedef uint64_t LargestRead; 4336019Shines@cs.fsu.edu // Need to use 64 bits to make sure that read requests get handled properly 4346019Shines@cs.fsu.edu 4356019Shines@cs.fsu.edu typedef int RegContextParam; 4366019Shines@cs.fsu.edu typedef int RegContextVal; 4376019Shines@cs.fsu.edu 4386019Shines@cs.fsu.edu //used in FP convert & round function 4396019Shines@cs.fsu.edu enum ConvertType{ 4406019Shines@cs.fsu.edu SINGLE_TO_DOUBLE, 4416019Shines@cs.fsu.edu SINGLE_TO_WORD, 4426019Shines@cs.fsu.edu SINGLE_TO_LONG, 4436019Shines@cs.fsu.edu 4446019Shines@cs.fsu.edu DOUBLE_TO_SINGLE, 4456019Shines@cs.fsu.edu DOUBLE_TO_WORD, 4466019Shines@cs.fsu.edu DOUBLE_TO_LONG, 4476019Shines@cs.fsu.edu 4486019Shines@cs.fsu.edu LONG_TO_SINGLE, 4496019Shines@cs.fsu.edu LONG_TO_DOUBLE, 4506019Shines@cs.fsu.edu LONG_TO_WORD, 4516019Shines@cs.fsu.edu LONG_TO_PS, 4526019Shines@cs.fsu.edu 4536019Shines@cs.fsu.edu WORD_TO_SINGLE, 4546019Shines@cs.fsu.edu WORD_TO_DOUBLE, 4556019Shines@cs.fsu.edu WORD_TO_LONG, 4566019Shines@cs.fsu.edu WORD_TO_PS, 4576019Shines@cs.fsu.edu 4586019Shines@cs.fsu.edu PL_TO_SINGLE, 4596019Shines@cs.fsu.edu PU_TO_SINGLE 4606019Shines@cs.fsu.edu }; 4616019Shines@cs.fsu.edu 4626019Shines@cs.fsu.edu //used in FP convert & round function 4636019Shines@cs.fsu.edu enum RoundMode{ 4646019Shines@cs.fsu.edu RND_ZERO, 4656019Shines@cs.fsu.edu RND_DOWN, 4666019Shines@cs.fsu.edu RND_UP, 4676019Shines@cs.fsu.edu RND_NEAREST 4686019Shines@cs.fsu.edu }; 4696019Shines@cs.fsu.edu 4706019Shines@cs.fsu.edu enum OperatingMode { 4716019Shines@cs.fsu.edu MODE_USER = 16, 4726019Shines@cs.fsu.edu MODE_FIQ = 17, 4736019Shines@cs.fsu.edu MODE_IRQ = 18, 4746019Shines@cs.fsu.edu MODE_SVC = 19, 4756723Sgblack@eecs.umich.edu MODE_MON = 22, 4766019Shines@cs.fsu.edu MODE_ABORT = 23, 4776019Shines@cs.fsu.edu MODE_UNDEFINED = 27, 4787498Sgblack@eecs.umich.edu MODE_SYSTEM = 31, 4797498Sgblack@eecs.umich.edu MODE_MAXMODE = MODE_SYSTEM 4806019Shines@cs.fsu.edu }; 4816019Shines@cs.fsu.edu 4827311Sgblack@eecs.umich.edu static inline bool 4837311Sgblack@eecs.umich.edu badMode(OperatingMode mode) 4847311Sgblack@eecs.umich.edu { 4857311Sgblack@eecs.umich.edu switch (mode) { 4867311Sgblack@eecs.umich.edu case MODE_USER: 4877311Sgblack@eecs.umich.edu case MODE_FIQ: 4887311Sgblack@eecs.umich.edu case MODE_IRQ: 4897311Sgblack@eecs.umich.edu case MODE_SVC: 4907311Sgblack@eecs.umich.edu case MODE_MON: 4917311Sgblack@eecs.umich.edu case MODE_ABORT: 4927311Sgblack@eecs.umich.edu case MODE_UNDEFINED: 4937311Sgblack@eecs.umich.edu case MODE_SYSTEM: 4947311Sgblack@eecs.umich.edu return false; 4957311Sgblack@eecs.umich.edu default: 4967311Sgblack@eecs.umich.edu return true; 4977311Sgblack@eecs.umich.edu } 4987311Sgblack@eecs.umich.edu } 4997311Sgblack@eecs.umich.edu 5006019Shines@cs.fsu.edu struct CoreSpecific { 5016019Shines@cs.fsu.edu // Empty for now on the ARM 5026019Shines@cs.fsu.edu }; 5036019Shines@cs.fsu.edu 5046019Shines@cs.fsu.edu} // namespace ArmISA 5056019Shines@cs.fsu.edu 5067680Sgblack@eecs.umich.edunamespace __hash_namespace { 5077680Sgblack@eecs.umich.edu template<> 5087680Sgblack@eecs.umich.edu struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> { 5097680Sgblack@eecs.umich.edu size_t operator()(const ArmISA::ExtMachInst &emi) const { 5107680Sgblack@eecs.umich.edu return hash<uint32_t>::operator()((uint32_t)emi); 5117680Sgblack@eecs.umich.edu }; 5127680Sgblack@eecs.umich.edu }; 5137680Sgblack@eecs.umich.edu} 5147680Sgblack@eecs.umich.edu 5156019Shines@cs.fsu.edu#endif 516