types.hh revision 6275
16019Shines@cs.fsu.edu/* 26019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 36019Shines@cs.fsu.edu * All rights reserved. 46019Shines@cs.fsu.edu * 56019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 66019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 76019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 86019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 96019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 106019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 116019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 126019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 136019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 146019Shines@cs.fsu.edu * this software without specific prior written permission. 156019Shines@cs.fsu.edu * 166019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * Authors: Stephen Hines 296019Shines@cs.fsu.edu */ 306019Shines@cs.fsu.edu 316019Shines@cs.fsu.edu#ifndef __ARCH_ARM_TYPES_HH__ 326019Shines@cs.fsu.edu#define __ARCH_ARM_TYPES_HH__ 336019Shines@cs.fsu.edu 346251Sgblack@eecs.umich.edu#include "base/bitunion.hh" 356214Snate@binkert.org#include "base/types.hh" 366019Shines@cs.fsu.edu 376019Shines@cs.fsu.edunamespace ArmISA 386019Shines@cs.fsu.edu{ 396019Shines@cs.fsu.edu typedef uint32_t MachInst; 406251Sgblack@eecs.umich.edu 416267Sgblack@eecs.umich.edu BitUnion64(ExtMachInst) 426267Sgblack@eecs.umich.edu // Made up bitfields that make life easier. 436267Sgblack@eecs.umich.edu Bitfield<33> sevenAndFour; 446267Sgblack@eecs.umich.edu Bitfield<32> isMisc; 456267Sgblack@eecs.umich.edu 466251Sgblack@eecs.umich.edu // All the different types of opcode fields. 476268Sgblack@eecs.umich.edu Bitfield<27, 25> encoding; 486268Sgblack@eecs.umich.edu Bitfield<24, 21> opcode; 496269Sgblack@eecs.umich.edu Bitfield<24, 20> mediaOpcode; 506251Sgblack@eecs.umich.edu Bitfield<24> opcode24; 516251Sgblack@eecs.umich.edu Bitfield<23, 20> opcode23_20; 526251Sgblack@eecs.umich.edu Bitfield<23, 21> opcode23_21; 536251Sgblack@eecs.umich.edu Bitfield<22> opcode22; 546251Sgblack@eecs.umich.edu Bitfield<19> opcode19; 556251Sgblack@eecs.umich.edu Bitfield<15, 12> opcode15_12; 566251Sgblack@eecs.umich.edu Bitfield<15> opcode15; 576268Sgblack@eecs.umich.edu Bitfield<7, 4> miscOpcode; 586251Sgblack@eecs.umich.edu Bitfield<7> opcode7; 596251Sgblack@eecs.umich.edu Bitfield<4> opcode4; 606251Sgblack@eecs.umich.edu 616251Sgblack@eecs.umich.edu Bitfield<31, 28> condCode; 626251Sgblack@eecs.umich.edu Bitfield<20> sField; 636251Sgblack@eecs.umich.edu Bitfield<19, 16> rn; 646251Sgblack@eecs.umich.edu Bitfield<15, 12> rd; 656251Sgblack@eecs.umich.edu Bitfield<11, 7> shiftSize; 666251Sgblack@eecs.umich.edu Bitfield<6, 5> shift; 676251Sgblack@eecs.umich.edu Bitfield<3, 0> rm; 686251Sgblack@eecs.umich.edu 696251Sgblack@eecs.umich.edu Bitfield<11, 8> rs; 706251Sgblack@eecs.umich.edu 716251Sgblack@eecs.umich.edu SubBitUnion(puswl, 24, 20) 726251Sgblack@eecs.umich.edu Bitfield<24> prepost; 736251Sgblack@eecs.umich.edu Bitfield<23> up; 746251Sgblack@eecs.umich.edu Bitfield<22> psruser; 756251Sgblack@eecs.umich.edu Bitfield<21> writeback; 766251Sgblack@eecs.umich.edu Bitfield<20> loadOp; 776251Sgblack@eecs.umich.edu EndSubBitUnion(puswl) 786251Sgblack@eecs.umich.edu 796251Sgblack@eecs.umich.edu Bitfield<24, 20> pubwl; 806251Sgblack@eecs.umich.edu 816275Sgblack@eecs.umich.edu Bitfield<7, 0> imm; 826251Sgblack@eecs.umich.edu 836251Sgblack@eecs.umich.edu Bitfield<11, 8> rotate; 846275Sgblack@eecs.umich.edu 856275Sgblack@eecs.umich.edu Bitfield<11, 0> immed11_0; 866251Sgblack@eecs.umich.edu Bitfield<7, 0> immed7_0; 876251Sgblack@eecs.umich.edu 886251Sgblack@eecs.umich.edu Bitfield<11, 8> immedHi11_8; 896251Sgblack@eecs.umich.edu Bitfield<3, 0> immedLo3_0; 906251Sgblack@eecs.umich.edu 916251Sgblack@eecs.umich.edu Bitfield<15, 0> regList; 926251Sgblack@eecs.umich.edu 936251Sgblack@eecs.umich.edu Bitfield<23, 0> offset; 946251Sgblack@eecs.umich.edu 956251Sgblack@eecs.umich.edu Bitfield<23, 0> immed23_0; 966251Sgblack@eecs.umich.edu 976251Sgblack@eecs.umich.edu Bitfield<11, 8> cpNum; 986251Sgblack@eecs.umich.edu Bitfield<18, 16> fn; 996251Sgblack@eecs.umich.edu Bitfield<14, 12> fd; 1006251Sgblack@eecs.umich.edu Bitfield<3> fpRegImm; 1016251Sgblack@eecs.umich.edu Bitfield<3, 0> fm; 1026251Sgblack@eecs.umich.edu Bitfield<2, 0> fpImm; 1036251Sgblack@eecs.umich.edu Bitfield<24, 20> punwl; 1046251Sgblack@eecs.umich.edu 1056251Sgblack@eecs.umich.edu Bitfield<7, 0> m5Func; 1066251Sgblack@eecs.umich.edu EndBitUnion(ExtMachInst) 1076251Sgblack@eecs.umich.edu 1086254Sgblack@eecs.umich.edu // Shift types for ARM instructions 1096254Sgblack@eecs.umich.edu enum ArmShiftType { 1106254Sgblack@eecs.umich.edu LSL = 0, 1116254Sgblack@eecs.umich.edu LSR, 1126254Sgblack@eecs.umich.edu ASR, 1136254Sgblack@eecs.umich.edu ROR 1146254Sgblack@eecs.umich.edu }; 1156254Sgblack@eecs.umich.edu 1166019Shines@cs.fsu.edu typedef uint8_t RegIndex; 1176019Shines@cs.fsu.edu 1186019Shines@cs.fsu.edu typedef uint64_t IntReg; 1196019Shines@cs.fsu.edu typedef uint64_t LargestRead; 1206019Shines@cs.fsu.edu // Need to use 64 bits to make sure that read requests get handled properly 1216019Shines@cs.fsu.edu 1226019Shines@cs.fsu.edu // floating point register file entry type 1236019Shines@cs.fsu.edu typedef uint32_t FloatReg32; 1246019Shines@cs.fsu.edu typedef uint64_t FloatReg64; 1256019Shines@cs.fsu.edu typedef uint64_t FloatRegBits; 1266019Shines@cs.fsu.edu 1276019Shines@cs.fsu.edu typedef double FloatRegVal; 1286019Shines@cs.fsu.edu typedef double FloatReg; 1296019Shines@cs.fsu.edu 1306019Shines@cs.fsu.edu // cop-0/cop-1 system control register 1316019Shines@cs.fsu.edu typedef uint64_t MiscReg; 1326019Shines@cs.fsu.edu 1336019Shines@cs.fsu.edu typedef union { 1346019Shines@cs.fsu.edu IntReg intreg; 1356019Shines@cs.fsu.edu FloatReg fpreg; 1366019Shines@cs.fsu.edu MiscReg ctrlreg; 1376019Shines@cs.fsu.edu } AnyReg; 1386019Shines@cs.fsu.edu 1396019Shines@cs.fsu.edu typedef int RegContextParam; 1406019Shines@cs.fsu.edu typedef int RegContextVal; 1416019Shines@cs.fsu.edu 1426019Shines@cs.fsu.edu //used in FP convert & round function 1436019Shines@cs.fsu.edu enum ConvertType{ 1446019Shines@cs.fsu.edu SINGLE_TO_DOUBLE, 1456019Shines@cs.fsu.edu SINGLE_TO_WORD, 1466019Shines@cs.fsu.edu SINGLE_TO_LONG, 1476019Shines@cs.fsu.edu 1486019Shines@cs.fsu.edu DOUBLE_TO_SINGLE, 1496019Shines@cs.fsu.edu DOUBLE_TO_WORD, 1506019Shines@cs.fsu.edu DOUBLE_TO_LONG, 1516019Shines@cs.fsu.edu 1526019Shines@cs.fsu.edu LONG_TO_SINGLE, 1536019Shines@cs.fsu.edu LONG_TO_DOUBLE, 1546019Shines@cs.fsu.edu LONG_TO_WORD, 1556019Shines@cs.fsu.edu LONG_TO_PS, 1566019Shines@cs.fsu.edu 1576019Shines@cs.fsu.edu WORD_TO_SINGLE, 1586019Shines@cs.fsu.edu WORD_TO_DOUBLE, 1596019Shines@cs.fsu.edu WORD_TO_LONG, 1606019Shines@cs.fsu.edu WORD_TO_PS, 1616019Shines@cs.fsu.edu 1626019Shines@cs.fsu.edu PL_TO_SINGLE, 1636019Shines@cs.fsu.edu PU_TO_SINGLE 1646019Shines@cs.fsu.edu }; 1656019Shines@cs.fsu.edu 1666019Shines@cs.fsu.edu //used in FP convert & round function 1676019Shines@cs.fsu.edu enum RoundMode{ 1686019Shines@cs.fsu.edu RND_ZERO, 1696019Shines@cs.fsu.edu RND_DOWN, 1706019Shines@cs.fsu.edu RND_UP, 1716019Shines@cs.fsu.edu RND_NEAREST 1726019Shines@cs.fsu.edu }; 1736019Shines@cs.fsu.edu 1746019Shines@cs.fsu.edu enum OperatingMode { 1756019Shines@cs.fsu.edu MODE_USER = 16, 1766019Shines@cs.fsu.edu MODE_FIQ = 17, 1776019Shines@cs.fsu.edu MODE_IRQ = 18, 1786019Shines@cs.fsu.edu MODE_SVC = 19, 1796019Shines@cs.fsu.edu MODE_ABORT = 23, 1806019Shines@cs.fsu.edu MODE_UNDEFINED = 27, 1816019Shines@cs.fsu.edu MODE_SYSTEM = 31 1826019Shines@cs.fsu.edu }; 1836019Shines@cs.fsu.edu 1846019Shines@cs.fsu.edu struct CoreSpecific { 1856019Shines@cs.fsu.edu // Empty for now on the ARM 1866019Shines@cs.fsu.edu }; 1876019Shines@cs.fsu.edu 1886019Shines@cs.fsu.edu} // namespace ArmISA 1896019Shines@cs.fsu.edu 1906019Shines@cs.fsu.edu#endif 191