types.hh revision 12334
16019Shines@cs.fsu.edu/* 212299Sandreas.sandberg@arm.com * Copyright (c) 2010, 2012-2013, 2017 ARM Limited 37097Sgblack@eecs.umich.edu * All rights reserved 47097Sgblack@eecs.umich.edu * 57097Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67097Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77097Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87097Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97097Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107097Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117097Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127097Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137097Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 156019Shines@cs.fsu.edu * All rights reserved. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 266019Shines@cs.fsu.edu * this software without specific prior written permission. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019Shines@cs.fsu.edu * 406019Shines@cs.fsu.edu * Authors: Stephen Hines 416019Shines@cs.fsu.edu */ 426019Shines@cs.fsu.edu 436019Shines@cs.fsu.edu#ifndef __ARCH_ARM_TYPES_HH__ 446019Shines@cs.fsu.edu#define __ARCH_ARM_TYPES_HH__ 456019Shines@cs.fsu.edu 467720Sgblack@eecs.umich.edu#include "arch/generic/types.hh" 476251Sgblack@eecs.umich.edu#include "base/bitunion.hh" 4812334Sgabeblack@google.com#include "base/logging.hh" 496214Snate@binkert.org#include "base/types.hh" 509023Sgblack@eecs.umich.edu#include "debug/Decoder.hh" 516019Shines@cs.fsu.edu 526019Shines@cs.fsu.edunamespace ArmISA 536019Shines@cs.fsu.edu{ 546019Shines@cs.fsu.edu typedef uint32_t MachInst; 556251Sgblack@eecs.umich.edu 568205SAli.Saidi@ARM.com BitUnion8(ITSTATE) 578205SAli.Saidi@ARM.com /* Note that the split (cond, mask) below is not as in ARM ARM. 588205SAli.Saidi@ARM.com * But it is more convenient for simulation. The condition 598205SAli.Saidi@ARM.com * is always the concatenation of the top 3 bits and the next bit, 608205SAli.Saidi@ARM.com * which applies when one of the bottom 4 bits is set. 618205SAli.Saidi@ARM.com * Refer to predecoder.cc for the use case. 628205SAli.Saidi@ARM.com */ 638205SAli.Saidi@ARM.com Bitfield<7, 4> cond; 648205SAli.Saidi@ARM.com Bitfield<3, 0> mask; 658205SAli.Saidi@ARM.com // Bitfields for moving to/from CPSR 668205SAli.Saidi@ARM.com Bitfield<7, 2> top6; 678205SAli.Saidi@ARM.com Bitfield<1, 0> bottom2; 688205SAli.Saidi@ARM.com EndBitUnion(ITSTATE) 698205SAli.Saidi@ARM.com 7010611SAndreas.Sandberg@ARM.com BitUnion64(ExtMachInst) 7110611SAndreas.Sandberg@ARM.com // Decoder state 7210611SAndreas.Sandberg@ARM.com Bitfield<63, 62> decoderFault; // See DecoderFault 738205SAli.Saidi@ARM.com 747408Sgblack@eecs.umich.edu // ITSTATE bits 757408Sgblack@eecs.umich.edu Bitfield<55, 48> itstate; 767408Sgblack@eecs.umich.edu Bitfield<55, 52> itstateCond; 777408Sgblack@eecs.umich.edu Bitfield<51, 48> itstateMask; 787408Sgblack@eecs.umich.edu 797376Sgblack@eecs.umich.edu // FPSCR fields 807376Sgblack@eecs.umich.edu Bitfield<41, 40> fpscrStride; 817376Sgblack@eecs.umich.edu Bitfield<39, 37> fpscrLen; 827376Sgblack@eecs.umich.edu 837097Sgblack@eecs.umich.edu // Bitfields to select mode. 847097Sgblack@eecs.umich.edu Bitfield<36> thumb; 857097Sgblack@eecs.umich.edu Bitfield<35> bigThumb; 8610037SARM gem5 Developers Bitfield<34> aarch64; 877097Sgblack@eecs.umich.edu 886267Sgblack@eecs.umich.edu // Made up bitfields that make life easier. 896267Sgblack@eecs.umich.edu Bitfield<33> sevenAndFour; 906267Sgblack@eecs.umich.edu Bitfield<32> isMisc; 916267Sgblack@eecs.umich.edu 927098Sgblack@eecs.umich.edu uint32_t instBits; 937098Sgblack@eecs.umich.edu 946251Sgblack@eecs.umich.edu // All the different types of opcode fields. 956268Sgblack@eecs.umich.edu Bitfield<27, 25> encoding; 966749Sgblack@eecs.umich.edu Bitfield<25> useImm; 976268Sgblack@eecs.umich.edu Bitfield<24, 21> opcode; 986269Sgblack@eecs.umich.edu Bitfield<24, 20> mediaOpcode; 996251Sgblack@eecs.umich.edu Bitfield<24> opcode24; 1007161Sgblack@eecs.umich.edu Bitfield<24, 23> opcode24_23; 1016251Sgblack@eecs.umich.edu Bitfield<23, 20> opcode23_20; 1026251Sgblack@eecs.umich.edu Bitfield<23, 21> opcode23_21; 1036743Ssaidi@eecs.umich.edu Bitfield<20> opcode20; 1046251Sgblack@eecs.umich.edu Bitfield<22> opcode22; 1057105Sgblack@eecs.umich.edu Bitfield<19, 16> opcode19_16; 1066251Sgblack@eecs.umich.edu Bitfield<19> opcode19; 1076741Sgblack@eecs.umich.edu Bitfield<18> opcode18; 1086251Sgblack@eecs.umich.edu Bitfield<15, 12> opcode15_12; 1096251Sgblack@eecs.umich.edu Bitfield<15> opcode15; 1106268Sgblack@eecs.umich.edu Bitfield<7, 4> miscOpcode; 1116759SAli.Saidi@ARM.com Bitfield<7,5> opc2; 1126251Sgblack@eecs.umich.edu Bitfield<7> opcode7; 1137105Sgblack@eecs.umich.edu Bitfield<6> opcode6; 1146251Sgblack@eecs.umich.edu Bitfield<4> opcode4; 1156251Sgblack@eecs.umich.edu 1166251Sgblack@eecs.umich.edu Bitfield<31, 28> condCode; 1176251Sgblack@eecs.umich.edu Bitfield<20> sField; 1186251Sgblack@eecs.umich.edu Bitfield<19, 16> rn; 1196251Sgblack@eecs.umich.edu Bitfield<15, 12> rd; 1207121Sgblack@eecs.umich.edu Bitfield<15, 12> rt; 1216251Sgblack@eecs.umich.edu Bitfield<11, 7> shiftSize; 1226251Sgblack@eecs.umich.edu Bitfield<6, 5> shift; 1236251Sgblack@eecs.umich.edu Bitfield<3, 0> rm; 1246251Sgblack@eecs.umich.edu 1256251Sgblack@eecs.umich.edu Bitfield<11, 8> rs; 1266251Sgblack@eecs.umich.edu 1276251Sgblack@eecs.umich.edu SubBitUnion(puswl, 24, 20) 1286251Sgblack@eecs.umich.edu Bitfield<24> prepost; 1296251Sgblack@eecs.umich.edu Bitfield<23> up; 1306251Sgblack@eecs.umich.edu Bitfield<22> psruser; 1316251Sgblack@eecs.umich.edu Bitfield<21> writeback; 1326251Sgblack@eecs.umich.edu Bitfield<20> loadOp; 1336251Sgblack@eecs.umich.edu EndSubBitUnion(puswl) 1346251Sgblack@eecs.umich.edu 1356251Sgblack@eecs.umich.edu Bitfield<24, 20> pubwl; 1366251Sgblack@eecs.umich.edu 1376275Sgblack@eecs.umich.edu Bitfield<7, 0> imm; 1386251Sgblack@eecs.umich.edu 1396251Sgblack@eecs.umich.edu Bitfield<11, 8> rotate; 1406275Sgblack@eecs.umich.edu 1416275Sgblack@eecs.umich.edu Bitfield<11, 0> immed11_0; 1426251Sgblack@eecs.umich.edu Bitfield<7, 0> immed7_0; 1436251Sgblack@eecs.umich.edu 1446251Sgblack@eecs.umich.edu Bitfield<11, 8> immedHi11_8; 1456251Sgblack@eecs.umich.edu Bitfield<3, 0> immedLo3_0; 1466251Sgblack@eecs.umich.edu 1476251Sgblack@eecs.umich.edu Bitfield<15, 0> regList; 14810037SARM gem5 Developers 1496251Sgblack@eecs.umich.edu Bitfield<23, 0> offset; 15010037SARM gem5 Developers 1516251Sgblack@eecs.umich.edu Bitfield<23, 0> immed23_0; 1526251Sgblack@eecs.umich.edu 1536251Sgblack@eecs.umich.edu Bitfield<11, 8> cpNum; 1546251Sgblack@eecs.umich.edu Bitfield<18, 16> fn; 1556251Sgblack@eecs.umich.edu Bitfield<14, 12> fd; 1566251Sgblack@eecs.umich.edu Bitfield<3> fpRegImm; 1576251Sgblack@eecs.umich.edu Bitfield<3, 0> fm; 1586251Sgblack@eecs.umich.edu Bitfield<2, 0> fpImm; 1596251Sgblack@eecs.umich.edu Bitfield<24, 20> punwl; 1606251Sgblack@eecs.umich.edu 1617732SAli.Saidi@ARM.com Bitfield<15, 8> m5Func; 1627103Sgblack@eecs.umich.edu 1637103Sgblack@eecs.umich.edu // 16 bit thumb bitfields 1647103Sgblack@eecs.umich.edu Bitfield<15, 13> topcode15_13; 1657103Sgblack@eecs.umich.edu Bitfield<13, 11> topcode13_11; 1667103Sgblack@eecs.umich.edu Bitfield<12, 11> topcode12_11; 1677103Sgblack@eecs.umich.edu Bitfield<12, 10> topcode12_10; 1687103Sgblack@eecs.umich.edu Bitfield<11, 9> topcode11_9; 1697103Sgblack@eecs.umich.edu Bitfield<11, 8> topcode11_8; 1707103Sgblack@eecs.umich.edu Bitfield<10, 9> topcode10_9; 1717103Sgblack@eecs.umich.edu Bitfield<10, 8> topcode10_8; 1727103Sgblack@eecs.umich.edu Bitfield<9, 6> topcode9_6; 1737103Sgblack@eecs.umich.edu Bitfield<7> topcode7; 1747103Sgblack@eecs.umich.edu Bitfield<7, 6> topcode7_6; 1757103Sgblack@eecs.umich.edu Bitfield<7, 5> topcode7_5; 1767103Sgblack@eecs.umich.edu Bitfield<7, 4> topcode7_4; 1777103Sgblack@eecs.umich.edu Bitfield<3, 0> topcode3_0; 1787106Sgblack@eecs.umich.edu 1797106Sgblack@eecs.umich.edu // 32 bit thumb bitfields 1807106Sgblack@eecs.umich.edu Bitfield<28, 27> htopcode12_11; 1817106Sgblack@eecs.umich.edu Bitfield<26, 25> htopcode10_9; 1827106Sgblack@eecs.umich.edu Bitfield<25> htopcode9; 1837106Sgblack@eecs.umich.edu Bitfield<25, 24> htopcode9_8; 1847106Sgblack@eecs.umich.edu Bitfield<25, 21> htopcode9_5; 1857106Sgblack@eecs.umich.edu Bitfield<25, 20> htopcode9_4; 1867106Sgblack@eecs.umich.edu Bitfield<24> htopcode8; 1877106Sgblack@eecs.umich.edu Bitfield<24, 23> htopcode8_7; 1887106Sgblack@eecs.umich.edu Bitfield<24, 22> htopcode8_6; 1897106Sgblack@eecs.umich.edu Bitfield<24, 21> htopcode8_5; 1907113Sgblack@eecs.umich.edu Bitfield<23> htopcode7; 1917116Sgblack@eecs.umich.edu Bitfield<23, 21> htopcode7_5; 1927245Sgblack@eecs.umich.edu Bitfield<22> htopcode6; 1937106Sgblack@eecs.umich.edu Bitfield<22, 21> htopcode6_5; 1947106Sgblack@eecs.umich.edu Bitfield<21, 20> htopcode5_4; 1957106Sgblack@eecs.umich.edu Bitfield<20> htopcode4; 1967106Sgblack@eecs.umich.edu 1977106Sgblack@eecs.umich.edu Bitfield<19, 16> htrn; 1987106Sgblack@eecs.umich.edu Bitfield<20> hts; 1997106Sgblack@eecs.umich.edu 2007106Sgblack@eecs.umich.edu Bitfield<15> ltopcode15; 2017113Sgblack@eecs.umich.edu Bitfield<11, 8> ltopcode11_8; 2027113Sgblack@eecs.umich.edu Bitfield<7, 6> ltopcode7_6; 2037106Sgblack@eecs.umich.edu Bitfield<7, 4> ltopcode7_4; 2047106Sgblack@eecs.umich.edu Bitfield<4> ltopcode4; 2057106Sgblack@eecs.umich.edu 2067106Sgblack@eecs.umich.edu Bitfield<11, 8> ltrd; 2077106Sgblack@eecs.umich.edu Bitfield<11, 8> ltcoproc; 2086251Sgblack@eecs.umich.edu EndBitUnion(ExtMachInst) 2096251Sgblack@eecs.umich.edu 2107720Sgblack@eecs.umich.edu class PCState : public GenericISA::UPCState<MachInst> 2117720Sgblack@eecs.umich.edu { 2127720Sgblack@eecs.umich.edu protected: 2137720Sgblack@eecs.umich.edu 2147720Sgblack@eecs.umich.edu typedef GenericISA::UPCState<MachInst> Base; 2157720Sgblack@eecs.umich.edu 2167720Sgblack@eecs.umich.edu enum FlagBits { 2177720Sgblack@eecs.umich.edu ThumbBit = (1 << 0), 21810037SARM gem5 Developers JazelleBit = (1 << 1), 21910037SARM gem5 Developers AArch64Bit = (1 << 2) 2207720Sgblack@eecs.umich.edu }; 2217720Sgblack@eecs.umich.edu uint8_t flags; 2227720Sgblack@eecs.umich.edu uint8_t nextFlags; 2238205SAli.Saidi@ARM.com uint8_t _itstate; 2248205SAli.Saidi@ARM.com uint8_t _nextItstate; 2258146SAli.Saidi@ARM.com uint8_t _size; 2267720Sgblack@eecs.umich.edu public: 22710537Sandreas.hansson@arm.com PCState() : flags(0), nextFlags(0), _itstate(0), _nextItstate(0), 22810537Sandreas.hansson@arm.com _size(0) 2297720Sgblack@eecs.umich.edu {} 2307720Sgblack@eecs.umich.edu 2317720Sgblack@eecs.umich.edu void 2327720Sgblack@eecs.umich.edu set(Addr val) 2337720Sgblack@eecs.umich.edu { 2347720Sgblack@eecs.umich.edu Base::set(val); 2357720Sgblack@eecs.umich.edu npc(val + (thumb() ? 2 : 4)); 2367720Sgblack@eecs.umich.edu } 2377720Sgblack@eecs.umich.edu 23810537Sandreas.hansson@arm.com PCState(Addr val) : flags(0), nextFlags(0), _itstate(0), 23910537Sandreas.hansson@arm.com _nextItstate(0), _size(0) 2407720Sgblack@eecs.umich.edu { set(val); } 2417720Sgblack@eecs.umich.edu 2427720Sgblack@eecs.umich.edu bool 2437720Sgblack@eecs.umich.edu thumb() const 2447720Sgblack@eecs.umich.edu { 2457720Sgblack@eecs.umich.edu return flags & ThumbBit; 2467720Sgblack@eecs.umich.edu } 2477720Sgblack@eecs.umich.edu 2487720Sgblack@eecs.umich.edu void 2497720Sgblack@eecs.umich.edu thumb(bool val) 2507720Sgblack@eecs.umich.edu { 2517720Sgblack@eecs.umich.edu if (val) 2527720Sgblack@eecs.umich.edu flags |= ThumbBit; 2537720Sgblack@eecs.umich.edu else 2547720Sgblack@eecs.umich.edu flags &= ~ThumbBit; 2557720Sgblack@eecs.umich.edu } 2567720Sgblack@eecs.umich.edu 2577720Sgblack@eecs.umich.edu bool 2587720Sgblack@eecs.umich.edu nextThumb() const 2597720Sgblack@eecs.umich.edu { 2607720Sgblack@eecs.umich.edu return nextFlags & ThumbBit; 2617720Sgblack@eecs.umich.edu } 2627720Sgblack@eecs.umich.edu 2637720Sgblack@eecs.umich.edu void 2647720Sgblack@eecs.umich.edu nextThumb(bool val) 2657720Sgblack@eecs.umich.edu { 2667720Sgblack@eecs.umich.edu if (val) 2677720Sgblack@eecs.umich.edu nextFlags |= ThumbBit; 2687720Sgblack@eecs.umich.edu else 2697720Sgblack@eecs.umich.edu nextFlags &= ~ThumbBit; 2707720Sgblack@eecs.umich.edu } 2717720Sgblack@eecs.umich.edu 2728146SAli.Saidi@ARM.com void size(uint8_t s) { _size = s; } 2738146SAli.Saidi@ARM.com uint8_t size() const { return _size; } 2748146SAli.Saidi@ARM.com 2758146SAli.Saidi@ARM.com bool 2768146SAli.Saidi@ARM.com branching() const 2778146SAli.Saidi@ARM.com { 2788146SAli.Saidi@ARM.com return ((this->pc() + this->size()) != this->npc()); 2798146SAli.Saidi@ARM.com } 2808146SAli.Saidi@ARM.com 2818146SAli.Saidi@ARM.com 2827720Sgblack@eecs.umich.edu bool 2837720Sgblack@eecs.umich.edu jazelle() const 2847720Sgblack@eecs.umich.edu { 2857720Sgblack@eecs.umich.edu return flags & JazelleBit; 2867720Sgblack@eecs.umich.edu } 2877720Sgblack@eecs.umich.edu 2887720Sgblack@eecs.umich.edu void 2897720Sgblack@eecs.umich.edu jazelle(bool val) 2907720Sgblack@eecs.umich.edu { 2917720Sgblack@eecs.umich.edu if (val) 2927720Sgblack@eecs.umich.edu flags |= JazelleBit; 2937720Sgblack@eecs.umich.edu else 2947720Sgblack@eecs.umich.edu flags &= ~JazelleBit; 2957720Sgblack@eecs.umich.edu } 2967720Sgblack@eecs.umich.edu 2977720Sgblack@eecs.umich.edu bool 2987720Sgblack@eecs.umich.edu nextJazelle() const 2997720Sgblack@eecs.umich.edu { 3007720Sgblack@eecs.umich.edu return nextFlags & JazelleBit; 3017720Sgblack@eecs.umich.edu } 3027720Sgblack@eecs.umich.edu 3037720Sgblack@eecs.umich.edu void 3047720Sgblack@eecs.umich.edu nextJazelle(bool val) 3057720Sgblack@eecs.umich.edu { 3067720Sgblack@eecs.umich.edu if (val) 3077720Sgblack@eecs.umich.edu nextFlags |= JazelleBit; 3087720Sgblack@eecs.umich.edu else 3097720Sgblack@eecs.umich.edu nextFlags &= ~JazelleBit; 3107720Sgblack@eecs.umich.edu } 3117720Sgblack@eecs.umich.edu 31210037SARM gem5 Developers bool 31310037SARM gem5 Developers aarch64() const 31410037SARM gem5 Developers { 31510037SARM gem5 Developers return flags & AArch64Bit; 31610037SARM gem5 Developers } 31710037SARM gem5 Developers 31810037SARM gem5 Developers void 31910037SARM gem5 Developers aarch64(bool val) 32010037SARM gem5 Developers { 32110037SARM gem5 Developers if (val) 32210037SARM gem5 Developers flags |= AArch64Bit; 32310037SARM gem5 Developers else 32410037SARM gem5 Developers flags &= ~AArch64Bit; 32510037SARM gem5 Developers } 32610037SARM gem5 Developers 32710037SARM gem5 Developers bool 32810037SARM gem5 Developers nextAArch64() const 32910037SARM gem5 Developers { 33010037SARM gem5 Developers return nextFlags & AArch64Bit; 33110037SARM gem5 Developers } 33210037SARM gem5 Developers 33310037SARM gem5 Developers void 33410037SARM gem5 Developers nextAArch64(bool val) 33510037SARM gem5 Developers { 33610037SARM gem5 Developers if (val) 33710037SARM gem5 Developers nextFlags |= AArch64Bit; 33810037SARM gem5 Developers else 33910037SARM gem5 Developers nextFlags &= ~AArch64Bit; 34010037SARM gem5 Developers } 34110037SARM gem5 Developers 34210037SARM gem5 Developers 3437858SMatt.Horsnell@arm.com uint8_t 3448205SAli.Saidi@ARM.com itstate() const 3457858SMatt.Horsnell@arm.com { 3468205SAli.Saidi@ARM.com return _itstate; 3477858SMatt.Horsnell@arm.com } 3487858SMatt.Horsnell@arm.com 3497858SMatt.Horsnell@arm.com void 3508205SAli.Saidi@ARM.com itstate(uint8_t value) 3517858SMatt.Horsnell@arm.com { 3528205SAli.Saidi@ARM.com _itstate = value; 3537858SMatt.Horsnell@arm.com } 3547858SMatt.Horsnell@arm.com 3558205SAli.Saidi@ARM.com uint8_t 3568205SAli.Saidi@ARM.com nextItstate() const 3577858SMatt.Horsnell@arm.com { 3588205SAli.Saidi@ARM.com return _nextItstate; 3598205SAli.Saidi@ARM.com } 3608205SAli.Saidi@ARM.com 3618205SAli.Saidi@ARM.com void 3628205SAli.Saidi@ARM.com nextItstate(uint8_t value) 3638205SAli.Saidi@ARM.com { 3648205SAli.Saidi@ARM.com _nextItstate = value; 3657858SMatt.Horsnell@arm.com } 3667858SMatt.Horsnell@arm.com 3677720Sgblack@eecs.umich.edu void 3687720Sgblack@eecs.umich.edu advance() 3697720Sgblack@eecs.umich.edu { 3707720Sgblack@eecs.umich.edu Base::advance(); 3719074SAli.Saidi@ARM.com flags = nextFlags; 3727720Sgblack@eecs.umich.edu npc(pc() + (thumb() ? 2 : 4)); 3737858SMatt.Horsnell@arm.com 3748205SAli.Saidi@ARM.com if (_nextItstate) { 3758205SAli.Saidi@ARM.com _itstate = _nextItstate; 3768205SAli.Saidi@ARM.com _nextItstate = 0; 3778205SAli.Saidi@ARM.com } else if (_itstate) { 3788205SAli.Saidi@ARM.com ITSTATE it = _itstate; 3798205SAli.Saidi@ARM.com uint8_t cond_mask = it.mask; 3808205SAli.Saidi@ARM.com uint8_t thumb_cond = it.cond; 3819023Sgblack@eecs.umich.edu DPRINTF(Decoder, "Advancing ITSTATE from %#x,%#x.\n", 3828205SAli.Saidi@ARM.com thumb_cond, cond_mask); 3838205SAli.Saidi@ARM.com cond_mask <<= 1; 3848205SAli.Saidi@ARM.com uint8_t new_bit = bits(cond_mask, 4); 3858205SAli.Saidi@ARM.com cond_mask &= mask(4); 3868205SAli.Saidi@ARM.com if (cond_mask == 0) 3878205SAli.Saidi@ARM.com thumb_cond = 0; 3888205SAli.Saidi@ARM.com else 3898205SAli.Saidi@ARM.com replaceBits(thumb_cond, 0, new_bit); 3909023Sgblack@eecs.umich.edu DPRINTF(Decoder, "Advancing ITSTATE to %#x,%#x.\n", 3918205SAli.Saidi@ARM.com thumb_cond, cond_mask); 3928205SAli.Saidi@ARM.com it.mask = cond_mask; 3938205SAli.Saidi@ARM.com it.cond = thumb_cond; 3948205SAli.Saidi@ARM.com _itstate = it; 3957858SMatt.Horsnell@arm.com } 3967720Sgblack@eecs.umich.edu } 3977720Sgblack@eecs.umich.edu 3987720Sgblack@eecs.umich.edu void 3997720Sgblack@eecs.umich.edu uEnd() 4007720Sgblack@eecs.umich.edu { 4017720Sgblack@eecs.umich.edu advance(); 4027720Sgblack@eecs.umich.edu upc(0); 4037720Sgblack@eecs.umich.edu nupc(1); 4047720Sgblack@eecs.umich.edu } 4057720Sgblack@eecs.umich.edu 4067720Sgblack@eecs.umich.edu Addr 4077720Sgblack@eecs.umich.edu instPC() const 4087720Sgblack@eecs.umich.edu { 4097720Sgblack@eecs.umich.edu return pc() + (thumb() ? 4 : 8); 4107720Sgblack@eecs.umich.edu } 4117720Sgblack@eecs.umich.edu 4127720Sgblack@eecs.umich.edu void 41310037SARM gem5 Developers instNPC(Addr val) 4147720Sgblack@eecs.umich.edu { 41510037SARM gem5 Developers // @todo: review this when AArch32/64 interprocessing is 41610037SARM gem5 Developers // supported 41710037SARM gem5 Developers if (aarch64()) 41810037SARM gem5 Developers npc(val); // AArch64 doesn't force PC alignment, a PC 41910037SARM gem5 Developers // Alignment Fault can be raised instead 42010037SARM gem5 Developers else 42110037SARM gem5 Developers npc(val &~ mask(nextThumb() ? 1 : 2)); 4227720Sgblack@eecs.umich.edu } 4237720Sgblack@eecs.umich.edu 4247720Sgblack@eecs.umich.edu Addr 4257720Sgblack@eecs.umich.edu instNPC() const 4267720Sgblack@eecs.umich.edu { 4277720Sgblack@eecs.umich.edu return npc(); 4287720Sgblack@eecs.umich.edu } 4297720Sgblack@eecs.umich.edu 4307720Sgblack@eecs.umich.edu // Perform an interworking branch. 4317720Sgblack@eecs.umich.edu void 43210037SARM gem5 Developers instIWNPC(Addr val) 4337720Sgblack@eecs.umich.edu { 4347720Sgblack@eecs.umich.edu bool thumbEE = (thumb() && jazelle()); 4357720Sgblack@eecs.umich.edu 4367720Sgblack@eecs.umich.edu Addr newPC = val; 4377720Sgblack@eecs.umich.edu if (thumbEE) { 4387720Sgblack@eecs.umich.edu if (bits(newPC, 0)) { 4397720Sgblack@eecs.umich.edu newPC = newPC & ~mask(1); 4408075SAli.Saidi@ARM.com } // else we have a bad interworking address; do not call 4418075SAli.Saidi@ARM.com // panic() since the instruction could be executed 4428075SAli.Saidi@ARM.com // speculatively 4437720Sgblack@eecs.umich.edu } else { 4447720Sgblack@eecs.umich.edu if (bits(newPC, 0)) { 4457720Sgblack@eecs.umich.edu nextThumb(true); 4467720Sgblack@eecs.umich.edu newPC = newPC & ~mask(1); 4477720Sgblack@eecs.umich.edu } else if (!bits(newPC, 1)) { 4487720Sgblack@eecs.umich.edu nextThumb(false); 4497720Sgblack@eecs.umich.edu } else { 4507744SAli.Saidi@ARM.com // This state is UNPREDICTABLE in the ARM architecture 4517744SAli.Saidi@ARM.com // The easy thing to do is just mask off the bit and 4527744SAli.Saidi@ARM.com // stay in the current mode, so we'll do that. 4537744SAli.Saidi@ARM.com newPC &= ~mask(2); 4547720Sgblack@eecs.umich.edu } 4557720Sgblack@eecs.umich.edu } 4567720Sgblack@eecs.umich.edu npc(newPC); 4577720Sgblack@eecs.umich.edu } 4587720Sgblack@eecs.umich.edu 4597720Sgblack@eecs.umich.edu // Perform an interworking branch in ARM mode, a regular branch 4607720Sgblack@eecs.umich.edu // otherwise. 4617720Sgblack@eecs.umich.edu void 46210037SARM gem5 Developers instAIWNPC(Addr val) 4637720Sgblack@eecs.umich.edu { 4647720Sgblack@eecs.umich.edu if (!thumb() && !jazelle()) 4657720Sgblack@eecs.umich.edu instIWNPC(val); 4667720Sgblack@eecs.umich.edu else 4677720Sgblack@eecs.umich.edu instNPC(val); 4687720Sgblack@eecs.umich.edu } 4697720Sgblack@eecs.umich.edu 4707720Sgblack@eecs.umich.edu bool 4717720Sgblack@eecs.umich.edu operator == (const PCState &opc) const 4727720Sgblack@eecs.umich.edu { 4737720Sgblack@eecs.umich.edu return Base::operator == (opc) && 4748205SAli.Saidi@ARM.com flags == opc.flags && nextFlags == opc.nextFlags && 4758205SAli.Saidi@ARM.com _itstate == opc._itstate && _nextItstate == opc._nextItstate; 4767720Sgblack@eecs.umich.edu } 4777720Sgblack@eecs.umich.edu 4788361Sksewell@umich.edu bool 4798361Sksewell@umich.edu operator != (const PCState &opc) const 4808361Sksewell@umich.edu { 4818361Sksewell@umich.edu return !(*this == opc); 4828361Sksewell@umich.edu } 4838361Sksewell@umich.edu 4847720Sgblack@eecs.umich.edu void 48511168Sandreas.hansson@arm.com serialize(CheckpointOut &cp) const override 4867720Sgblack@eecs.umich.edu { 48710905Sandreas.sandberg@arm.com Base::serialize(cp); 4887720Sgblack@eecs.umich.edu SERIALIZE_SCALAR(flags); 4898146SAli.Saidi@ARM.com SERIALIZE_SCALAR(_size); 4907720Sgblack@eecs.umich.edu SERIALIZE_SCALAR(nextFlags); 4918205SAli.Saidi@ARM.com SERIALIZE_SCALAR(_itstate); 4928205SAli.Saidi@ARM.com SERIALIZE_SCALAR(_nextItstate); 4937720Sgblack@eecs.umich.edu } 4947720Sgblack@eecs.umich.edu 4957720Sgblack@eecs.umich.edu void 49611168Sandreas.hansson@arm.com unserialize(CheckpointIn &cp) override 4977720Sgblack@eecs.umich.edu { 49810905Sandreas.sandberg@arm.com Base::unserialize(cp); 4997720Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(flags); 5008146SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(_size); 5017720Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(nextFlags); 5028205SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(_itstate); 5038205SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(_nextItstate); 5047720Sgblack@eecs.umich.edu } 5057720Sgblack@eecs.umich.edu }; 5067720Sgblack@eecs.umich.edu 5076254Sgblack@eecs.umich.edu // Shift types for ARM instructions 5086254Sgblack@eecs.umich.edu enum ArmShiftType { 5096254Sgblack@eecs.umich.edu LSL = 0, 5106254Sgblack@eecs.umich.edu LSR, 5116254Sgblack@eecs.umich.edu ASR, 5126254Sgblack@eecs.umich.edu ROR 5136254Sgblack@eecs.umich.edu }; 5146254Sgblack@eecs.umich.edu 51510037SARM gem5 Developers // Extension types for ARM instructions 51610037SARM gem5 Developers enum ArmExtendType { 51710037SARM gem5 Developers UXTB = 0, 51810037SARM gem5 Developers UXTH = 1, 51910037SARM gem5 Developers UXTW = 2, 52010037SARM gem5 Developers UXTX = 3, 52110037SARM gem5 Developers SXTB = 4, 52210037SARM gem5 Developers SXTH = 5, 52310037SARM gem5 Developers SXTW = 6, 52410037SARM gem5 Developers SXTX = 7 52510037SARM gem5 Developers }; 52610037SARM gem5 Developers 5276019Shines@cs.fsu.edu typedef int RegContextParam; 5286019Shines@cs.fsu.edu typedef int RegContextVal; 5296019Shines@cs.fsu.edu 5306019Shines@cs.fsu.edu //used in FP convert & round function 5316019Shines@cs.fsu.edu enum ConvertType{ 5326019Shines@cs.fsu.edu SINGLE_TO_DOUBLE, 5336019Shines@cs.fsu.edu SINGLE_TO_WORD, 5346019Shines@cs.fsu.edu SINGLE_TO_LONG, 5356019Shines@cs.fsu.edu 5366019Shines@cs.fsu.edu DOUBLE_TO_SINGLE, 5376019Shines@cs.fsu.edu DOUBLE_TO_WORD, 5386019Shines@cs.fsu.edu DOUBLE_TO_LONG, 5396019Shines@cs.fsu.edu 5406019Shines@cs.fsu.edu LONG_TO_SINGLE, 5416019Shines@cs.fsu.edu LONG_TO_DOUBLE, 5426019Shines@cs.fsu.edu LONG_TO_WORD, 5436019Shines@cs.fsu.edu LONG_TO_PS, 5446019Shines@cs.fsu.edu 5456019Shines@cs.fsu.edu WORD_TO_SINGLE, 5466019Shines@cs.fsu.edu WORD_TO_DOUBLE, 5476019Shines@cs.fsu.edu WORD_TO_LONG, 5486019Shines@cs.fsu.edu WORD_TO_PS, 5496019Shines@cs.fsu.edu 5506019Shines@cs.fsu.edu PL_TO_SINGLE, 5516019Shines@cs.fsu.edu PU_TO_SINGLE 5526019Shines@cs.fsu.edu }; 5536019Shines@cs.fsu.edu 5546019Shines@cs.fsu.edu //used in FP convert & round function 5556019Shines@cs.fsu.edu enum RoundMode{ 5566019Shines@cs.fsu.edu RND_ZERO, 5576019Shines@cs.fsu.edu RND_DOWN, 5586019Shines@cs.fsu.edu RND_UP, 5596019Shines@cs.fsu.edu RND_NEAREST 5606019Shines@cs.fsu.edu }; 5616019Shines@cs.fsu.edu 56210037SARM gem5 Developers enum ExceptionLevel { 56310037SARM gem5 Developers EL0 = 0, 56410037SARM gem5 Developers EL1, 56510037SARM gem5 Developers EL2, 56610037SARM gem5 Developers EL3 56710037SARM gem5 Developers }; 56810037SARM gem5 Developers 5696019Shines@cs.fsu.edu enum OperatingMode { 57010037SARM gem5 Developers MODE_EL0T = 0x0, 57110037SARM gem5 Developers MODE_EL1T = 0x4, 57210037SARM gem5 Developers MODE_EL1H = 0x5, 57310037SARM gem5 Developers MODE_EL2T = 0x8, 57410037SARM gem5 Developers MODE_EL2H = 0x9, 57510037SARM gem5 Developers MODE_EL3T = 0xC, 57610037SARM gem5 Developers MODE_EL3H = 0xD, 5776019Shines@cs.fsu.edu MODE_USER = 16, 5786019Shines@cs.fsu.edu MODE_FIQ = 17, 5796019Shines@cs.fsu.edu MODE_IRQ = 18, 5806019Shines@cs.fsu.edu MODE_SVC = 19, 5816723Sgblack@eecs.umich.edu MODE_MON = 22, 5826019Shines@cs.fsu.edu MODE_ABORT = 23, 58310037SARM gem5 Developers MODE_HYP = 26, 5846019Shines@cs.fsu.edu MODE_UNDEFINED = 27, 5857498Sgblack@eecs.umich.edu MODE_SYSTEM = 31, 5867498Sgblack@eecs.umich.edu MODE_MAXMODE = MODE_SYSTEM 5876019Shines@cs.fsu.edu }; 5886019Shines@cs.fsu.edu 58910037SARM gem5 Developers enum ExceptionClass { 59010037SARM gem5 Developers EC_INVALID = -1, 59110037SARM gem5 Developers EC_UNKNOWN = 0x0, 59210037SARM gem5 Developers EC_TRAPPED_WFI_WFE = 0x1, 59310037SARM gem5 Developers EC_TRAPPED_CP15_MCR_MRC = 0x3, 59410037SARM gem5 Developers EC_TRAPPED_CP15_MCRR_MRRC = 0x4, 59510037SARM gem5 Developers EC_TRAPPED_CP14_MCR_MRC = 0x5, 59610037SARM gem5 Developers EC_TRAPPED_CP14_LDC_STC = 0x6, 59710037SARM gem5 Developers EC_TRAPPED_HCPTR = 0x7, 59810037SARM gem5 Developers EC_TRAPPED_SIMD_FP = 0x7, // AArch64 alias 59910037SARM gem5 Developers EC_TRAPPED_CP10_MRC_VMRS = 0x8, 60010037SARM gem5 Developers EC_TRAPPED_BXJ = 0xA, 60110037SARM gem5 Developers EC_TRAPPED_CP14_MCRR_MRRC = 0xC, 60210037SARM gem5 Developers EC_ILLEGAL_INST = 0xE, 60310037SARM gem5 Developers EC_SVC_TO_HYP = 0x11, 60410037SARM gem5 Developers EC_SVC = 0x11, // AArch64 alias 60510037SARM gem5 Developers EC_HVC = 0x12, 60610037SARM gem5 Developers EC_SMC_TO_HYP = 0x13, 60710037SARM gem5 Developers EC_SMC = 0x13, // AArch64 alias 60810037SARM gem5 Developers EC_SVC_64 = 0x15, 60910037SARM gem5 Developers EC_HVC_64 = 0x16, 61010037SARM gem5 Developers EC_SMC_64 = 0x17, 61110037SARM gem5 Developers EC_TRAPPED_MSR_MRS_64 = 0x18, 61210037SARM gem5 Developers EC_PREFETCH_ABORT_TO_HYP = 0x20, 61310037SARM gem5 Developers EC_PREFETCH_ABORT_LOWER_EL = 0x20, // AArch64 alias 61410037SARM gem5 Developers EC_PREFETCH_ABORT_FROM_HYP = 0x21, 61510037SARM gem5 Developers EC_PREFETCH_ABORT_CURR_EL = 0x21, // AArch64 alias 61610037SARM gem5 Developers EC_PC_ALIGNMENT = 0x22, 61710037SARM gem5 Developers EC_DATA_ABORT_TO_HYP = 0x24, 61810037SARM gem5 Developers EC_DATA_ABORT_LOWER_EL = 0x24, // AArch64 alias 61910037SARM gem5 Developers EC_DATA_ABORT_FROM_HYP = 0x25, 62010037SARM gem5 Developers EC_DATA_ABORT_CURR_EL = 0x25, // AArch64 alias 62110037SARM gem5 Developers EC_STACK_PTR_ALIGNMENT = 0x26, 62210037SARM gem5 Developers EC_FP_EXCEPTION = 0x28, 62310037SARM gem5 Developers EC_FP_EXCEPTION_64 = 0x2C, 62412299Sandreas.sandberg@arm.com EC_SERROR = 0x2F, 62512299Sandreas.sandberg@arm.com EC_SOFTWARE_BREAKPOINT = 0x38, 62610037SARM gem5 Developers }; 62710037SARM gem5 Developers 62810611SAndreas.Sandberg@ARM.com /** 62910611SAndreas.Sandberg@ARM.com * Instruction decoder fault codes in ExtMachInst. 63010611SAndreas.Sandberg@ARM.com */ 63110611SAndreas.Sandberg@ARM.com enum DecoderFault : std::uint8_t { 63210611SAndreas.Sandberg@ARM.com OK = 0x0, ///< No fault 63310611SAndreas.Sandberg@ARM.com UNALIGNED = 0x1, ///< Unaligned instruction fault 63410611SAndreas.Sandberg@ARM.com 63510611SAndreas.Sandberg@ARM.com PANIC = 0x3, ///< Internal gem5 error 63610611SAndreas.Sandberg@ARM.com }; 63710611SAndreas.Sandberg@ARM.com 63810037SARM gem5 Developers BitUnion8(OperatingMode64) 63910037SARM gem5 Developers Bitfield<0> spX; 64010037SARM gem5 Developers Bitfield<3, 2> el; 64110037SARM gem5 Developers Bitfield<4> width; 64210037SARM gem5 Developers EndBitUnion(OperatingMode64) 64310037SARM gem5 Developers 64410037SARM gem5 Developers static bool inline 64510037SARM gem5 Developers opModeIs64(OperatingMode mode) 64610037SARM gem5 Developers { 64710037SARM gem5 Developers return ((OperatingMode64)(uint8_t)mode).width == 0; 64810037SARM gem5 Developers } 64910037SARM gem5 Developers 65010037SARM gem5 Developers static bool inline 65110037SARM gem5 Developers opModeIsH(OperatingMode mode) 65210037SARM gem5 Developers { 65310037SARM gem5 Developers return (mode == MODE_EL1H || mode == MODE_EL2H || mode == MODE_EL3H); 65410037SARM gem5 Developers } 65510037SARM gem5 Developers 65610037SARM gem5 Developers static bool inline 65710037SARM gem5 Developers opModeIsT(OperatingMode mode) 65810037SARM gem5 Developers { 65910037SARM gem5 Developers return (mode == MODE_EL0T || mode == MODE_EL1T || mode == MODE_EL2T || 66010037SARM gem5 Developers mode == MODE_EL3T); 66110037SARM gem5 Developers } 66210037SARM gem5 Developers 66310037SARM gem5 Developers static ExceptionLevel inline 66410037SARM gem5 Developers opModeToEL(OperatingMode mode) 66510037SARM gem5 Developers { 66610037SARM gem5 Developers bool aarch32 = ((mode >> 4) & 1) ? true : false; 66710037SARM gem5 Developers if (aarch32) { 66810037SARM gem5 Developers switch (mode) { 66910037SARM gem5 Developers case MODE_USER: 67010037SARM gem5 Developers return EL0; 67110037SARM gem5 Developers case MODE_FIQ: 67210037SARM gem5 Developers case MODE_IRQ: 67310037SARM gem5 Developers case MODE_SVC: 67410037SARM gem5 Developers case MODE_ABORT: 67510037SARM gem5 Developers case MODE_UNDEFINED: 67610037SARM gem5 Developers case MODE_SYSTEM: 67710037SARM gem5 Developers return EL1; 67810037SARM gem5 Developers case MODE_HYP: 67910037SARM gem5 Developers return EL2; 68010037SARM gem5 Developers case MODE_MON: 68110037SARM gem5 Developers return EL3; 68210037SARM gem5 Developers default: 68310037SARM gem5 Developers panic("Invalid operating mode: %d", mode); 68410037SARM gem5 Developers break; 68510037SARM gem5 Developers } 68610037SARM gem5 Developers } else { 68710037SARM gem5 Developers // aarch64 68810037SARM gem5 Developers return (ExceptionLevel) ((mode >> 2) & 3); 68910037SARM gem5 Developers } 69010037SARM gem5 Developers } 69110037SARM gem5 Developers 6927311Sgblack@eecs.umich.edu static inline bool 6937311Sgblack@eecs.umich.edu badMode(OperatingMode mode) 6947311Sgblack@eecs.umich.edu { 6957311Sgblack@eecs.umich.edu switch (mode) { 69610037SARM gem5 Developers case MODE_EL0T: 69710037SARM gem5 Developers case MODE_EL1T: 69810037SARM gem5 Developers case MODE_EL1H: 69910037SARM gem5 Developers case MODE_EL2T: 70010037SARM gem5 Developers case MODE_EL2H: 70110037SARM gem5 Developers case MODE_EL3T: 70210037SARM gem5 Developers case MODE_EL3H: 70310037SARM gem5 Developers case MODE_USER: 70410037SARM gem5 Developers case MODE_FIQ: 70510037SARM gem5 Developers case MODE_IRQ: 70610037SARM gem5 Developers case MODE_SVC: 70710037SARM gem5 Developers case MODE_MON: 70810037SARM gem5 Developers case MODE_ABORT: 70910037SARM gem5 Developers case MODE_HYP: 71010037SARM gem5 Developers case MODE_UNDEFINED: 71110037SARM gem5 Developers case MODE_SYSTEM: 71210037SARM gem5 Developers return false; 71310037SARM gem5 Developers default: 71410037SARM gem5 Developers return true; 71510037SARM gem5 Developers } 71610037SARM gem5 Developers } 71710037SARM gem5 Developers 71810037SARM gem5 Developers 71910037SARM gem5 Developers static inline bool 72010037SARM gem5 Developers badMode32(OperatingMode mode) 72110037SARM gem5 Developers { 72210037SARM gem5 Developers switch (mode) { 7237311Sgblack@eecs.umich.edu case MODE_USER: 7247311Sgblack@eecs.umich.edu case MODE_FIQ: 7257311Sgblack@eecs.umich.edu case MODE_IRQ: 7267311Sgblack@eecs.umich.edu case MODE_SVC: 7277311Sgblack@eecs.umich.edu case MODE_MON: 7287311Sgblack@eecs.umich.edu case MODE_ABORT: 72910037SARM gem5 Developers case MODE_HYP: 7307311Sgblack@eecs.umich.edu case MODE_UNDEFINED: 7317311Sgblack@eecs.umich.edu case MODE_SYSTEM: 7327311Sgblack@eecs.umich.edu return false; 7337311Sgblack@eecs.umich.edu default: 7347311Sgblack@eecs.umich.edu return true; 7357311Sgblack@eecs.umich.edu } 7367311Sgblack@eecs.umich.edu } 7377311Sgblack@eecs.umich.edu 7386019Shines@cs.fsu.edu} // namespace ArmISA 7396019Shines@cs.fsu.edu 74011168Sandreas.hansson@arm.comnamespace std { 74110316Sandreas.hansson@arm.com 74210316Sandreas.hansson@arm.comtemplate<> 74310316Sandreas.hansson@arm.comstruct hash<ArmISA::ExtMachInst> : 74410316Sandreas.hansson@arm.com public hash<ArmISA::ExtMachInst::__DataType> { 74510316Sandreas.hansson@arm.com 74610316Sandreas.hansson@arm.com size_t operator()(const ArmISA::ExtMachInst &emi) const { 74710316Sandreas.hansson@arm.com return hash<ArmISA::ExtMachInst::__DataType>::operator()(emi); 74810316Sandreas.hansson@arm.com } 74910316Sandreas.hansson@arm.com 75010316Sandreas.hansson@arm.com}; 75110316Sandreas.hansson@arm.com 75211168Sandreas.hansson@arm.com} 7537680Sgblack@eecs.umich.edu 7546019Shines@cs.fsu.edu#endif 755