TarmacTrace.py revision 13665
112641Sgiacomo.travaglini@arm.com# Copyright (c) 2018 ARM Limited 212641Sgiacomo.travaglini@arm.com# All rights reserved. 312641Sgiacomo.travaglini@arm.com# 412641Sgiacomo.travaglini@arm.com# The license below extends only to copyright in the software and shall 512641Sgiacomo.travaglini@arm.com# not be construed as granting a license to any other intellectual 612641Sgiacomo.travaglini@arm.com# property including but not limited to intellectual property relating 712641Sgiacomo.travaglini@arm.com# to a hardware implementation of the functionality of the software 812641Sgiacomo.travaglini@arm.com# licensed hereunder. You may use the software subject to the license 912641Sgiacomo.travaglini@arm.com# terms below provided that you ensure that this notice is replicated 1012641Sgiacomo.travaglini@arm.com# unmodified and in its entirety in all distributions of the software, 1112641Sgiacomo.travaglini@arm.com# modified or unmodified, in source code or in binary form. 1212641Sgiacomo.travaglini@arm.com# 1312641Sgiacomo.travaglini@arm.com# Redistribution and use in source and binary forms, with or without 1412641Sgiacomo.travaglini@arm.com# modification, are permitted provided that the following conditions are 1512641Sgiacomo.travaglini@arm.com# met: redistributions of source code must retain the above copyright 1612641Sgiacomo.travaglini@arm.com# notice, this list of conditions and the following disclaimer; 1712641Sgiacomo.travaglini@arm.com# redistributions in binary form must reproduce the above copyright 1812641Sgiacomo.travaglini@arm.com# notice, this list of conditions and the following disclaimer in the 1912641Sgiacomo.travaglini@arm.com# documentation and/or other materials provided with the distribution; 2012641Sgiacomo.travaglini@arm.com# neither the name of the copyright holders nor the names of its 2112641Sgiacomo.travaglini@arm.com# contributors may be used to endorse or promote products derived from 2212641Sgiacomo.travaglini@arm.com# this software without specific prior written permission. 2312641Sgiacomo.travaglini@arm.com# 2412641Sgiacomo.travaglini@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2512641Sgiacomo.travaglini@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2612641Sgiacomo.travaglini@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2712641Sgiacomo.travaglini@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2812641Sgiacomo.travaglini@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2912641Sgiacomo.travaglini@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3012641Sgiacomo.travaglini@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3112641Sgiacomo.travaglini@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3212641Sgiacomo.travaglini@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3312641Sgiacomo.travaglini@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3412641Sgiacomo.travaglini@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3512641Sgiacomo.travaglini@arm.com# 3612641Sgiacomo.travaglini@arm.com# Authors: Giacomo Gabrielli 3712641Sgiacomo.travaglini@arm.com# Giacomo Travaglini 3812641Sgiacomo.travaglini@arm.com 3912641Sgiacomo.travaglini@arm.comfrom m5.SimObject import SimObject 4012641Sgiacomo.travaglini@arm.comfrom m5.params import * 4113665Sandreas.sandberg@arm.comfrom m5.objects.InstTracer import InstTracer 4212641Sgiacomo.travaglini@arm.com 4312641Sgiacomo.travaglini@arm.comclass TarmacParser(InstTracer): 4412641Sgiacomo.travaglini@arm.com type = 'TarmacParser' 4512641Sgiacomo.travaglini@arm.com cxx_class = 'Trace::TarmacParser' 4612641Sgiacomo.travaglini@arm.com cxx_header = "arch/arm/tracers/tarmac_parser.hh" 4712641Sgiacomo.travaglini@arm.com 4812641Sgiacomo.travaglini@arm.com path_to_trace = Param.String("tarmac.log", "path to TARMAC trace") 4912641Sgiacomo.travaglini@arm.com 5012641Sgiacomo.travaglini@arm.com start_pc = Param.Int( 5112641Sgiacomo.travaglini@arm.com 0x0, "tracing starts when the PC gets this value; ignored if 0x0") 5212641Sgiacomo.travaglini@arm.com 5312641Sgiacomo.travaglini@arm.com exit_on_diff = Param.Bool(False, 5412641Sgiacomo.travaglini@arm.com "stop simulation after first mismatch is detected") 5512641Sgiacomo.travaglini@arm.com 5612641Sgiacomo.travaglini@arm.com exit_on_insn_diff = Param.Bool(False, 5712641Sgiacomo.travaglini@arm.com "stop simulation after first mismatch on PC or opcode is detected") 5812641Sgiacomo.travaglini@arm.com 5912641Sgiacomo.travaglini@arm.com mem_wr_check = Param.Bool(False, 6012641Sgiacomo.travaglini@arm.com "enable check of memory write accesses") 6112641Sgiacomo.travaglini@arm.com 6212641Sgiacomo.travaglini@arm.com cpu_id = Param.Bool(False, 6312641Sgiacomo.travaglini@arm.com "true if trace format includes the CPU id") 6412641Sgiacomo.travaglini@arm.com 6512641Sgiacomo.travaglini@arm.com ignore_mem_addr = Param.AddrRange(AddrRange(0, size=0), 6612641Sgiacomo.travaglini@arm.com "Range of unverifiable memory addresses") 6712642Sgiacomo.travaglini@arm.com 6812642Sgiacomo.travaglini@arm.comclass TarmacTracer(InstTracer): 6912642Sgiacomo.travaglini@arm.com type = 'TarmacTracer' 7012642Sgiacomo.travaglini@arm.com cxx_class = 'Trace::TarmacTracer' 7112642Sgiacomo.travaglini@arm.com cxx_header = "arch/arm/tracers/tarmac_tracer.hh" 7212642Sgiacomo.travaglini@arm.com 7312642Sgiacomo.travaglini@arm.com start_tick = Param.Tick(0, 7412642Sgiacomo.travaglini@arm.com "tracing starts when the tick time gets this value") 7512642Sgiacomo.travaglini@arm.com 7612642Sgiacomo.travaglini@arm.com end_tick = Param.Tick(MaxTick, 7712642Sgiacomo.travaglini@arm.com "tracing ends when the tick time gets this value") 78