tlb.hh revision 7294 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * Copyright (c) 2007-2008 The Florida State University
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
9 * met: redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer;
11 * redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution;
14 * neither the name of the copyright holders nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * Authors: Nathan Binkert
31 *          Steve Reinhardt
32 *          Stephen Hines
33 */
34
35#ifndef __ARCH_ARM_TLB_HH__
36#define __ARCH_ARM_TLB_HH__
37
38#include <map>
39
40#include "arch/arm/isa_traits.hh"
41#include "arch/arm/utility.hh"
42#include "arch/arm/vtophys.hh"
43#include "arch/arm/pagetable.hh"
44#include "base/statistics.hh"
45#include "mem/request.hh"
46#include "params/ArmTLB.hh"
47#include "sim/faults.hh"
48#include "sim/tlb.hh"
49
50class ThreadContext;
51
52/* ARM does not distinguish between a DTLB and an ITLB -> unified TLB
53   However, to maintain compatibility with other architectures, we'll
54   simply create an ITLB and DTLB that will point to the real TLB */
55namespace ArmISA {
56
57// WARN: This particular TLB entry is not necessarily conformed to ARM ISA
58struct TlbEntry
59{
60    Addr _pageStart;
61    TlbEntry() {}
62    TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
63
64    void
65    updateVaddr(Addr new_vaddr)
66    {
67        panic("unimplemented");
68    }
69
70    Addr pageStart()
71    {
72        return _pageStart;
73    }
74
75    void serialize(std::ostream &os)
76    {
77        SERIALIZE_SCALAR(_pageStart);
78    }
79
80    void unserialize(Checkpoint *cp, const std::string &section)
81    {
82        UNSERIALIZE_SCALAR(_pageStart);
83    }
84
85};
86
87class TLB : public BaseTLB
88{
89  public:
90    enum ArmFlags {
91        AlignmentMask = 0x7,
92
93        AlignByte = 0x0,
94        AlignHalfWord = 0x1,
95        AlignWord = 0x3,
96        AlignDoubleWord = 0x7,
97
98        AllowUnaligned = 0x8,
99        // Because zero otherwise looks like a valid setting and may be used
100        // accidentally, this bit must be non-zero to show it was used on
101        // purpose.
102        MustBeOne = 0x10
103    };
104  protected:
105    typedef std::multimap<Addr, int> PageTable;
106    PageTable lookupTable;	// Quick lookup into page table
107
108    ArmISA::PTE *table;	// the Page Table
109    int size;			// TLB Size
110    int nlu;			// not last used entry (for replacement)
111
112    void nextnlu() { if (++nlu >= size) nlu = 0; }
113    ArmISA::PTE *lookup(Addr vpn, uint8_t asn) const;
114
115    mutable Stats::Scalar read_hits;
116    mutable Stats::Scalar read_misses;
117    mutable Stats::Scalar read_acv;
118    mutable Stats::Scalar read_accesses;
119    mutable Stats::Scalar write_hits;
120    mutable Stats::Scalar write_misses;
121    mutable Stats::Scalar write_acv;
122    mutable Stats::Scalar write_accesses;
123    Stats::Formula hits;
124    Stats::Formula misses;
125    Stats::Formula invalids;
126    Stats::Formula accesses;
127
128  public:
129    typedef ArmTLBParams Params;
130    TLB(const Params *p);
131
132    int probeEntry(Addr vpn,uint8_t) const;
133    ArmISA::PTE *getEntry(unsigned) const;
134    virtual ~TLB();
135    int smallPages;
136    int getsize() const { return size; }
137
138    ArmISA::PTE &index(bool advance = true);
139    void insert(Addr vaddr, ArmISA::PTE &pte);
140    void insertAt(ArmISA::PTE &pte, unsigned Index, int _smallPages);
141    void flushAll();
142    void demapPage(Addr vaddr, uint64_t asn)
143    {
144        panic("demapPage unimplemented.\n");
145    }
146
147    // static helper functions... really
148    static bool validVirtualAddress(Addr vaddr);
149
150    static Fault checkCacheability(RequestPtr &req);
151
152    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
153    void translateTiming(RequestPtr req, ThreadContext *tc,
154            Translation *translation, Mode mode);
155
156    // Checkpointing
157    void serialize(std::ostream &os);
158    void unserialize(Checkpoint *cp, const std::string &section);
159
160    void regStats();
161};
162
163/* namespace ArmISA */ }
164
165#endif // __ARCH_ARM_TLB_HH__
166