tlb.hh revision 6116
1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * Copyright (c) 2007-2008 The Florida State University 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are 9 * met: redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer; 11 * redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution; 14 * neither the name of the copyright holders nor the names of its 15 * contributors may be used to endorse or promote products derived from 16 * this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 * 30 * Authors: Nathan Binkert 31 * Steve Reinhardt 32 * Stephen Hines 33 */ 34 35#ifndef __ARCH_ARM_TLB_HH__ 36#define __ARCH_ARM_TLB_HH__ 37 38#include <map> 39 40#include "arch/arm/isa_traits.hh" 41#include "arch/arm/utility.hh" 42#include "arch/arm/vtophys.hh" 43#include "arch/arm/pagetable.hh" 44#include "base/statistics.hh" 45#include "mem/request.hh" 46#include "params/ArmTLB.hh" 47#include "sim/faults.hh" 48#include "sim/tlb.hh" 49 50class ThreadContext; 51 52/* ARM does not distinguish between a DTLB and an ITLB -> unified TLB 53 However, to maintain compatibility with other architectures, we'll 54 simply create an ITLB and DTLB that will point to the real TLB */ 55namespace ArmISA { 56 57// WARN: This particular TLB entry is not necessarily conformed to ARM ISA 58struct TlbEntry 59{ 60 Addr _pageStart; 61 TlbEntry() {} 62 TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {} 63 64 void 65 updateVaddr(Addr new_vaddr) 66 { 67 panic("unimplemented"); 68 } 69 70 Addr pageStart() 71 { 72 return _pageStart; 73 } 74 75 void serialize(std::ostream &os) 76 { 77 SERIALIZE_SCALAR(_pageStart); 78 } 79 80 void unserialize(Checkpoint *cp, const std::string §ion) 81 { 82 UNSERIALIZE_SCALAR(_pageStart); 83 } 84 85}; 86 87class TLB : public BaseTLB 88{ 89 protected: 90 typedef std::multimap<Addr, int> PageTable; 91 PageTable lookupTable; // Quick lookup into page table 92 93 ArmISA::PTE *table; // the Page Table 94 int size; // TLB Size 95 int nlu; // not last used entry (for replacement) 96 97 void nextnlu() { if (++nlu >= size) nlu = 0; } 98 ArmISA::PTE *lookup(Addr vpn, uint8_t asn) const; 99 100 mutable Stats::Scalar read_hits; 101 mutable Stats::Scalar read_misses; 102 mutable Stats::Scalar read_acv; 103 mutable Stats::Scalar read_accesses; 104 mutable Stats::Scalar write_hits; 105 mutable Stats::Scalar write_misses; 106 mutable Stats::Scalar write_acv; 107 mutable Stats::Scalar write_accesses; 108 Stats::Formula hits; 109 Stats::Formula misses; 110 Stats::Formula invalids; 111 Stats::Formula accesses; 112 113 public: 114 typedef ArmTLBParams Params; 115 TLB(const Params *p); 116 117 int probeEntry(Addr vpn,uint8_t) const; 118 ArmISA::PTE *getEntry(unsigned) const; 119 virtual ~TLB(); 120 int smallPages; 121 int getsize() const { return size; } 122 123 ArmISA::PTE &index(bool advance = true); 124 void insert(Addr vaddr, ArmISA::PTE &pte); 125 void insertAt(ArmISA::PTE &pte, unsigned Index, int _smallPages); 126 void flushAll(); 127 void demapPage(Addr vaddr, uint64_t asn) 128 { 129 panic("demapPage unimplemented.\n"); 130 } 131 132 // static helper functions... really 133 static bool validVirtualAddress(Addr vaddr); 134 135 static Fault checkCacheability(RequestPtr &req); 136 137 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); 138 void translateTiming(RequestPtr req, ThreadContext *tc, 139 Translation *translation, Mode mode); 140 141 // Checkpointing 142 void serialize(std::ostream &os); 143 void unserialize(Checkpoint *cp, const std::string §ion); 144 145 void regStats(); 146}; 147 148/* namespace ArmISA */ } 149 150#endif // __ARCH_ARM_TLB_HH__ 151