tlb.hh revision 6019:76890d8b28f5 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * Copyright (c) 2007-2008 The Florida State University
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
9 * met: redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer;
11 * redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution;
14 * neither the name of the copyright holders nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * Authors: Nathan Binkert
31 *          Steve Reinhardt
32 *          Stephen Hines
33 */
34
35#ifndef __ARCH_ARM_TLB_HH__
36#define __ARCH_ARM_TLB_HH__
37
38#include <map>
39
40#include "arch/arm/isa_traits.hh"
41#include "arch/arm/utility.hh"
42#include "arch/arm/vtophys.hh"
43#include "arch/arm/pagetable.hh"
44#include "base/statistics.hh"
45#include "mem/request.hh"
46#include "params/ArmDTB.hh"
47#include "params/ArmITB.hh"
48#include "sim/faults.hh"
49#include "sim/tlb.hh"
50
51class ThreadContext;
52
53/* ARM does not distinguish between a DTLB and an ITLB -> unified TLB
54   However, to maintain compatibility with other architectures, we'll
55   simply create an ITLB and DTLB that will point to the real TLB */
56namespace ArmISA {
57
58// WARN: This particular TLB entry is not necessarily conformed to ARM ISA
59struct TlbEntry
60{
61    Addr _pageStart;
62    TlbEntry() {}
63    TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
64
65    Addr pageStart()
66    {
67        return _pageStart;
68    }
69
70    void serialize(std::ostream &os)
71    {
72        SERIALIZE_SCALAR(_pageStart);
73    }
74
75    void unserialize(Checkpoint *cp, const std::string &section)
76    {
77        UNSERIALIZE_SCALAR(_pageStart);
78    }
79
80};
81
82class TLB : public BaseTLB
83{
84  protected:
85    typedef std::multimap<Addr, int> PageTable;
86    PageTable lookupTable;	// Quick lookup into page table
87
88    ArmISA::PTE *table;	// the Page Table
89    int size;			// TLB Size
90    int nlu;			// not last used entry (for replacement)
91
92    void nextnlu() { if (++nlu >= size) nlu = 0; }
93    ArmISA::PTE *lookup(Addr vpn, uint8_t asn) const;
94
95    mutable Stats::Scalar<> read_hits;
96    mutable Stats::Scalar<> read_misses;
97    mutable Stats::Scalar<> read_acv;
98    mutable Stats::Scalar<> read_accesses;
99    mutable Stats::Scalar<> write_hits;
100    mutable Stats::Scalar<> write_misses;
101    mutable Stats::Scalar<> write_acv;
102    mutable Stats::Scalar<> write_accesses;
103    Stats::Formula hits;
104    Stats::Formula misses;
105    Stats::Formula invalids;
106    Stats::Formula accesses;
107
108  public:
109    typedef ArmTLBParams Params;
110    TLB(const Params *p);
111
112    int probeEntry(Addr vpn,uint8_t) const;
113    ArmISA::PTE *getEntry(unsigned) const;
114    virtual ~TLB();
115    int smallPages;
116    int getsize() const { return size; }
117
118    ArmISA::PTE &index(bool advance = true);
119    void insert(Addr vaddr, ArmISA::PTE &pte);
120    void insertAt(ArmISA::PTE &pte, unsigned Index, int _smallPages);
121    void flushAll();
122    void demapPage(Addr vaddr, uint64_t asn)
123    {
124        panic("demapPage unimplemented.\n");
125    }
126
127    // static helper functions... really
128    static bool validVirtualAddress(Addr vaddr);
129
130    static Fault checkCacheability(RequestPtr &req);
131
132    // Checkpointing
133    void serialize(std::ostream &os);
134    void unserialize(Checkpoint *cp, const std::string &section);
135
136    void regStats();
137};
138
139class ITB : public TLB {
140  public:
141    typedef ArmTLBParams Params;
142    ITB(const Params *p);
143
144    Fault translate(RequestPtr &req, ThreadContext *tc);
145};
146
147class DTB : public TLB {
148  public:
149    typedef ArmTLBParams Params;
150    DTB(const Params *p);
151
152    Fault translate(RequestPtr &req, ThreadContext *tc, bool write = false);
153};
154
155class UTB : public ITB, public DTB {
156  public:
157    typedef ArmTLBParams Params;
158    UTB(const Params *p);
159
160};
161
162}
163
164#endif // __ARCH_ARM_TLB_HH__
165