tlb.hh revision 10194:e6d2e8083d9c
1/* 2 * Copyright (c) 2010-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 */ 42 43#ifndef __ARCH_ARM_TLB_HH__ 44#define __ARCH_ARM_TLB_HH__ 45 46 47#include "arch/arm/isa_traits.hh" 48#include "arch/arm/pagetable.hh" 49#include "arch/arm/utility.hh" 50#include "arch/arm/vtophys.hh" 51#include "base/statistics.hh" 52#include "dev/dma_device.hh" 53#include "mem/request.hh" 54#include "params/ArmTLB.hh" 55#include "sim/fault_fwd.hh" 56#include "sim/tlb.hh" 57 58class ThreadContext; 59 60namespace ArmISA { 61 62class TableWalker; 63class Stage2LookUp; 64class Stage2MMU; 65 66class TLB : public BaseTLB 67{ 68 public: 69 enum ArmFlags { 70 AlignmentMask = 0x7, 71 72 AlignByte = 0x0, 73 AlignHalfWord = 0x1, 74 AlignWord = 0x2, 75 AlignDoubleWord = 0x3, 76 AlignQuadWord = 0x4, 77 AlignOctWord = 0x5, 78 79 AllowUnaligned = 0x8, 80 // Priv code operating as if it wasn't 81 UserMode = 0x10, 82 // Because zero otherwise looks like a valid setting and may be used 83 // accidentally, this bit must be non-zero to show it was used on 84 // purpose. 85 MustBeOne = 0x40 86 }; 87 88 enum ArmTranslationType { 89 NormalTran = 0, 90 S1CTran = 0x1, 91 HypMode = 0x2, 92 // Secure code operating as if it wasn't (required by some Address 93 // Translate operations) 94 S1S2NsTran = 0x4 95 }; 96 protected: 97 TlbEntry* table; // the Page Table 98 int size; // TLB Size 99 bool isStage2; // Indicates this TLB is part of the second stage MMU 100 bool stage2Req; // Indicates whether a stage 2 lookup is also required 101 uint64_t _attr; // Memory attributes for last accessed TLB entry 102 bool directToStage2; // Indicates whether all translation requests should 103 // be routed directly to the stage 2 TLB 104 105 TableWalker *tableWalker; 106 TLB *stage2Tlb; 107 Stage2MMU *stage2Mmu; 108 109 // Access Stats 110 mutable Stats::Scalar instHits; 111 mutable Stats::Scalar instMisses; 112 mutable Stats::Scalar readHits; 113 mutable Stats::Scalar readMisses; 114 mutable Stats::Scalar writeHits; 115 mutable Stats::Scalar writeMisses; 116 mutable Stats::Scalar inserts; 117 mutable Stats::Scalar flushTlb; 118 mutable Stats::Scalar flushTlbMva; 119 mutable Stats::Scalar flushTlbMvaAsid; 120 mutable Stats::Scalar flushTlbAsid; 121 mutable Stats::Scalar flushedEntries; 122 mutable Stats::Scalar alignFaults; 123 mutable Stats::Scalar prefetchFaults; 124 mutable Stats::Scalar domainFaults; 125 mutable Stats::Scalar permsFaults; 126 127 Stats::Formula readAccesses; 128 Stats::Formula writeAccesses; 129 Stats::Formula instAccesses; 130 Stats::Formula hits; 131 Stats::Formula misses; 132 Stats::Formula accesses; 133 134 int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU 135 136 bool bootUncacheability; 137 138 public: 139 TLB(const ArmTLBParams *p); 140 TLB(const Params *p, int _size, TableWalker *_walker); 141 142 /** Lookup an entry in the TLB 143 * @param vpn virtual address 144 * @param asn context id/address space id to use 145 * @param vmid The virtual machine ID used for stage 2 translation 146 * @param secure if the lookup is secure 147 * @param hyp if the lookup is done from hyp mode 148 * @param functional if the lookup should modify state 149 * @param ignore_asn if on lookup asn should be ignored 150 * @return pointer to TLB entry if it exists 151 */ 152 TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp, 153 bool secure, bool functional, 154 bool ignore_asn, uint8_t target_el); 155 156 virtual ~TLB(); 157 158 void takeOverFrom(BaseTLB *otlb); 159 160 /// setup all the back pointers 161 virtual void init(); 162 163 void setMMU(Stage2MMU *m); 164 165 int getsize() const { return size; } 166 167 void insert(Addr vaddr, TlbEntry &pte); 168 169 Fault getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, 170 Translation *translation, bool timing, bool functional, 171 bool is_secure, ArmTranslationType tranType); 172 173 Fault getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc, 174 Mode mode, Translation *translation, bool timing, 175 bool functional, TlbEntry *mergeTe); 176 177 Fault checkPermissions(TlbEntry *te, RequestPtr req, Mode mode); 178 Fault checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode, 179 ThreadContext *tc); 180 181 182 /** Reset the entire TLB 183 * @param secure_lookup if the operation affects the secure world 184 */ 185 void flushAllSecurity(bool secure_lookup, uint8_t target_el, 186 bool ignore_el = false); 187 188 /** Remove all entries in the non secure world, depending on whether they 189 * were allocated in hyp mode or not 190 * @param hyp if the opperation affects hyp mode 191 */ 192 void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false); 193 194 195 /** Reset the entire TLB. Used for CPU switching to prevent stale 196 * translations after multiple switches 197 */ 198 void flushAll() 199 { 200 flushAllSecurity(false, 0, true); 201 flushAllSecurity(true, 0, true); 202 } 203 204 /** Remove any entries that match both a va and asn 205 * @param mva virtual address to flush 206 * @param asn contextid/asn to flush on match 207 * @param secure_lookup if the operation affects the secure world 208 */ 209 void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup, 210 uint8_t target_el); 211 212 /** Remove any entries that match the asn 213 * @param asn contextid/asn to flush on match 214 * @param secure_lookup if the operation affects the secure world 215 */ 216 void flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el); 217 218 /** Remove all entries that match the va regardless of asn 219 * @param mva address to flush from cache 220 * @param secure_lookup if the operation affects the secure world 221 * @param hyp if the operation affects hyp mode 222 */ 223 void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el); 224 225 Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain); 226 Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec, 227 bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level); 228 229 void printTlb() const; 230 231 void allCpusCaching() { bootUncacheability = true; } 232 void demapPage(Addr vaddr, uint64_t asn) 233 { 234 // needed for x86 only 235 panic("demapPage() is not implemented.\n"); 236 } 237 238 static bool validVirtualAddress(Addr vaddr); 239 240 /** 241 * Do a functional lookup on the TLB (for debugging) 242 * and don't modify any internal state 243 * @param tc thread context to get the context id from 244 * @param vaddr virtual address to translate 245 * @param pa returned physical address 246 * @return if the translation was successful 247 */ 248 bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr); 249 250 /** 251 * Do a functional lookup on the TLB (for checker cpu) that 252 * behaves like a normal lookup without modifying any page table state. 253 */ 254 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode, 255 ArmTranslationType tranType = NormalTran); 256 257 /** Accessor functions for memory attributes for last accessed TLB entry 258 */ 259 void 260 setAttr(uint64_t attr) 261 { 262 _attr = attr; 263 } 264 265 uint64_t 266 getAttr() const 267 { 268 return _attr; 269 } 270 271 Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 272 Translation *translation, bool &delay, 273 bool timing, ArmTranslationType tranType, bool functional = false); 274 Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 275 Translation *translation, bool &delay, bool timing); 276 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode, 277 ArmTranslationType tranType = NormalTran); 278 Fault translateTiming(RequestPtr req, ThreadContext *tc, 279 Translation *translation, Mode mode, 280 ArmTranslationType tranType = NormalTran); 281 Fault translateComplete(RequestPtr req, ThreadContext *tc, 282 Translation *translation, Mode mode, ArmTranslationType tranType, 283 bool callFromS2); 284 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const; 285 286 void drainResume(); 287 288 // Checkpointing 289 void serialize(std::ostream &os); 290 void unserialize(Checkpoint *cp, const std::string §ion); 291 292 void regStats(); 293 294 /** 295 * Get the table walker master port. This is used for migrating 296 * port connections during a CPU takeOverFrom() call. For 297 * architectures that do not have a table walker, NULL is 298 * returned, hence the use of a pointer rather than a 299 * reference. For ARM this method will always return a valid port 300 * pointer. 301 * 302 * @return A pointer to the walker master port 303 */ 304 virtual BaseMasterPort* getMasterPort(); 305 306 /** 307 * Allow the MMU (overseeing both stage 1 and stage 2 TLBs) to 308 * access the table walker port of this TLB so that it can 309 * orchestrate staged translations. 310 * 311 * @return The table walker DMA port 312 */ 313 DmaPort& getWalkerPort(); 314 315 // Caching misc register values here. 316 // Writing to misc registers needs to invalidate them. 317 // translateFunctional/translateSe/translateFs checks if they are 318 // invalid and call updateMiscReg if necessary. 319protected: 320 bool aarch64; 321 ExceptionLevel aarch64EL; 322 SCTLR sctlr; 323 SCR scr; 324 bool isPriv; 325 bool isSecure; 326 bool isHyp; 327 TTBCR ttbcr; 328 uint16_t asid; 329 uint8_t vmid; 330 PRRR prrr; 331 NMRR nmrr; 332 HCR hcr; 333 uint32_t dacr; 334 bool miscRegValid; 335 ArmTranslationType curTranType; 336 337 // Cached copies of system-level properties 338 bool haveLPAE; 339 bool haveVirtualization; 340 bool haveLargeAsid64; 341 342 void updateMiscReg(ThreadContext *tc, 343 ArmTranslationType tranType = NormalTran); 344 345public: 346 const Params * 347 params() const 348 { 349 return dynamic_cast<const Params *>(_params); 350 } 351 inline void invalidateMiscReg() { miscRegValid = false; } 352 353private: 354 /** Remove any entries that match both a va and asn 355 * @param mva virtual address to flush 356 * @param asn contextid/asn to flush on match 357 * @param secure_lookup if the operation affects the secure world 358 * @param hyp if the operation affects hyp mode 359 * @param ignore_asn if the flush should ignore the asn 360 */ 361 void _flushMva(Addr mva, uint64_t asn, bool secure_lookup, 362 bool hyp, bool ignore_asn, uint8_t target_el); 363 364 bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el); 365}; 366 367} // namespace ArmISA 368 369#endif // __ARCH_ARM_TLB_HH__ 370