tlb.hh revision 9738
16019Shines@cs.fsu.edu/*
29439SAndreas.Sandberg@ARM.com * Copyright (c) 2010-2012 ARM Limited
37399SAli.Saidi@ARM.com * All rights reserved
47399SAli.Saidi@ARM.com *
57399SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall
67399SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual
77399SAli.Saidi@ARM.com * property including but not limited to intellectual property relating
87399SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software
97399SAli.Saidi@ARM.com * licensed hereunder.  You may use the software subject to the license
107399SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated
117399SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software,
127399SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form.
137399SAli.Saidi@ARM.com *
146019Shines@cs.fsu.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan
156019Shines@cs.fsu.edu * All rights reserved.
166019Shines@cs.fsu.edu *
176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without
186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are
196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright
206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer;
216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright
226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the
236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution;
246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its
256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from
266019Shines@cs.fsu.edu * this software without specific prior written permission.
276019Shines@cs.fsu.edu *
286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
396019Shines@cs.fsu.edu *
407399SAli.Saidi@ARM.com * Authors: Ali Saidi
416019Shines@cs.fsu.edu */
426019Shines@cs.fsu.edu
436019Shines@cs.fsu.edu#ifndef __ARCH_ARM_TLB_HH__
446019Shines@cs.fsu.edu#define __ARCH_ARM_TLB_HH__
456019Shines@cs.fsu.edu
466019Shines@cs.fsu.edu#include <map>
476019Shines@cs.fsu.edu
486019Shines@cs.fsu.edu#include "arch/arm/isa_traits.hh"
498229Snate@binkert.org#include "arch/arm/pagetable.hh"
506019Shines@cs.fsu.edu#include "arch/arm/utility.hh"
516019Shines@cs.fsu.edu#include "arch/arm/vtophys.hh"
526019Shines@cs.fsu.edu#include "base/statistics.hh"
536019Shines@cs.fsu.edu#include "mem/request.hh"
546116Snate@binkert.org#include "params/ArmTLB.hh"
557878Sgblack@eecs.umich.edu#include "sim/fault_fwd.hh"
566019Shines@cs.fsu.edu#include "sim/tlb.hh"
576019Shines@cs.fsu.edu
586019Shines@cs.fsu.educlass ThreadContext;
596019Shines@cs.fsu.edu
606019Shines@cs.fsu.edunamespace ArmISA {
616019Shines@cs.fsu.edu
627404SAli.Saidi@ARM.comclass TableWalker;
637404SAli.Saidi@ARM.com
646019Shines@cs.fsu.educlass TLB : public BaseTLB
656019Shines@cs.fsu.edu{
667294Sgblack@eecs.umich.edu  public:
677294Sgblack@eecs.umich.edu    enum ArmFlags {
687639Sgblack@eecs.umich.edu        AlignmentMask = 0x1f,
697294Sgblack@eecs.umich.edu
707294Sgblack@eecs.umich.edu        AlignByte = 0x0,
717294Sgblack@eecs.umich.edu        AlignHalfWord = 0x1,
727294Sgblack@eecs.umich.edu        AlignWord = 0x3,
737294Sgblack@eecs.umich.edu        AlignDoubleWord = 0x7,
747639Sgblack@eecs.umich.edu        AlignQuadWord = 0xf,
757639Sgblack@eecs.umich.edu        AlignOctWord = 0x1f,
767294Sgblack@eecs.umich.edu
777639Sgblack@eecs.umich.edu        AllowUnaligned = 0x20,
787404SAli.Saidi@ARM.com        // Priv code operating as if it wasn't
797639Sgblack@eecs.umich.edu        UserMode = 0x40,
807294Sgblack@eecs.umich.edu        // Because zero otherwise looks like a valid setting and may be used
817294Sgblack@eecs.umich.edu        // accidentally, this bit must be non-zero to show it was used on
827294Sgblack@eecs.umich.edu        // purpose.
837639Sgblack@eecs.umich.edu        MustBeOne = 0x80
847294Sgblack@eecs.umich.edu    };
856019Shines@cs.fsu.edu  protected:
866019Shines@cs.fsu.edu
877799Sgblack@eecs.umich.edu    TlbEntry *table;    // the Page Table
887799Sgblack@eecs.umich.edu    int size;           // TLB Size
897406SAli.Saidi@ARM.com
907799Sgblack@eecs.umich.edu    uint32_t _attr;     // Memory attributes for last accessed TLB entry
917436Sdam.sunwoo@arm.com
927404SAli.Saidi@ARM.com    TableWalker *tableWalker;
936019Shines@cs.fsu.edu
947399SAli.Saidi@ARM.com    // Access Stats
957734SAli.Saidi@ARM.com    mutable Stats::Scalar instHits;
967734SAli.Saidi@ARM.com    mutable Stats::Scalar instMisses;
977734SAli.Saidi@ARM.com    mutable Stats::Scalar readHits;
987734SAli.Saidi@ARM.com    mutable Stats::Scalar readMisses;
997734SAli.Saidi@ARM.com    mutable Stats::Scalar writeHits;
1007734SAli.Saidi@ARM.com    mutable Stats::Scalar writeMisses;
1017734SAli.Saidi@ARM.com    mutable Stats::Scalar inserts;
1027734SAli.Saidi@ARM.com    mutable Stats::Scalar flushTlb;
1037734SAli.Saidi@ARM.com    mutable Stats::Scalar flushTlbMva;
1047734SAli.Saidi@ARM.com    mutable Stats::Scalar flushTlbMvaAsid;
1057734SAli.Saidi@ARM.com    mutable Stats::Scalar flushTlbAsid;
1067734SAli.Saidi@ARM.com    mutable Stats::Scalar flushedEntries;
1077734SAli.Saidi@ARM.com    mutable Stats::Scalar alignFaults;
1087734SAli.Saidi@ARM.com    mutable Stats::Scalar prefetchFaults;
1097734SAli.Saidi@ARM.com    mutable Stats::Scalar domainFaults;
1107734SAli.Saidi@ARM.com    mutable Stats::Scalar permsFaults;
1117734SAli.Saidi@ARM.com
1127734SAli.Saidi@ARM.com    Stats::Formula readAccesses;
1137734SAli.Saidi@ARM.com    Stats::Formula writeAccesses;
1147734SAli.Saidi@ARM.com    Stats::Formula instAccesses;
1156019Shines@cs.fsu.edu    Stats::Formula hits;
1166019Shines@cs.fsu.edu    Stats::Formula misses;
1176019Shines@cs.fsu.edu    Stats::Formula accesses;
1186019Shines@cs.fsu.edu
1197697SAli.Saidi@ARM.com    int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
1207404SAli.Saidi@ARM.com
1218527SAli.Saidi@ARM.com    bool bootUncacheability;
1228527SAli.Saidi@ARM.com
1236019Shines@cs.fsu.edu  public:
1246019Shines@cs.fsu.edu    typedef ArmTLBParams Params;
1256019Shines@cs.fsu.edu    TLB(const Params *p);
1266019Shines@cs.fsu.edu
1279535Smrinmoy.ghosh@arm.com    /** Lookup an entry in the TLB
1289535Smrinmoy.ghosh@arm.com     * @param vpn virtual address
1299535Smrinmoy.ghosh@arm.com     * @param asn context id/address space id to use
1309535Smrinmoy.ghosh@arm.com     * @param functional if the lookup should modify state
1319535Smrinmoy.ghosh@arm.com     * @return pointer to TLB entrry if it exists
1329535Smrinmoy.ghosh@arm.com     */
1339535Smrinmoy.ghosh@arm.com    TlbEntry *lookup(Addr vpn, uint8_t asn, bool functional = false);
1349535Smrinmoy.ghosh@arm.com
1356019Shines@cs.fsu.edu    virtual ~TLB();
1366019Shines@cs.fsu.edu    int getsize() const { return size; }
1376019Shines@cs.fsu.edu
1387404SAli.Saidi@ARM.com    void insert(Addr vaddr, TlbEntry &pte);
1397404SAli.Saidi@ARM.com
1407404SAli.Saidi@ARM.com    /** Reset the entire TLB */
1416019Shines@cs.fsu.edu    void flushAll();
1427404SAli.Saidi@ARM.com
1437404SAli.Saidi@ARM.com    /** Remove any entries that match both a va and asn
1447404SAli.Saidi@ARM.com     * @param mva virtual address to flush
1457404SAli.Saidi@ARM.com     * @param asn contextid/asn to flush on match
1467404SAli.Saidi@ARM.com     */
1477404SAli.Saidi@ARM.com    void flushMvaAsid(Addr mva, uint64_t asn);
1487404SAli.Saidi@ARM.com
1497404SAli.Saidi@ARM.com    /** Remove any entries that match the asn
1507404SAli.Saidi@ARM.com     * @param asn contextid/asn to flush on match
1517404SAli.Saidi@ARM.com     */
1527404SAli.Saidi@ARM.com    void flushAsid(uint64_t asn);
1537404SAli.Saidi@ARM.com
1547404SAli.Saidi@ARM.com    /** Remove all entries that match the va regardless of asn
1557404SAli.Saidi@ARM.com     * @param mva address to flush from cache
1567404SAli.Saidi@ARM.com     */
1577404SAli.Saidi@ARM.com    void flushMva(Addr mva);
1587404SAli.Saidi@ARM.com
1597404SAli.Saidi@ARM.com    Fault trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp);
1607406SAli.Saidi@ARM.com    Fault walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
1617406SAli.Saidi@ARM.com            bool is_write, uint8_t domain, bool sNp);
1627404SAli.Saidi@ARM.com
1637404SAli.Saidi@ARM.com    void printTlb();
1647404SAli.Saidi@ARM.com
1658527SAli.Saidi@ARM.com    void allCpusCaching() { bootUncacheability = true; }
1666019Shines@cs.fsu.edu    void demapPage(Addr vaddr, uint64_t asn)
1676019Shines@cs.fsu.edu    {
1687404SAli.Saidi@ARM.com        flushMvaAsid(vaddr, asn);
1696019Shines@cs.fsu.edu    }
1706019Shines@cs.fsu.edu
1716019Shines@cs.fsu.edu    static bool validVirtualAddress(Addr vaddr);
1726019Shines@cs.fsu.edu
1737694SAli.Saidi@ARM.com    /**
1747694SAli.Saidi@ARM.com     * Do a functional lookup on the TLB (for debugging)
1757694SAli.Saidi@ARM.com     * and don't modify any internal state
1767694SAli.Saidi@ARM.com     * @param tc thread context to get the context id from
1777694SAli.Saidi@ARM.com     * @param vaddr virtual address to translate
1787694SAli.Saidi@ARM.com     * @param pa returned physical address
1797694SAli.Saidi@ARM.com     * @return if the translation was successful
1807694SAli.Saidi@ARM.com     */
1817694SAli.Saidi@ARM.com    bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
1827694SAli.Saidi@ARM.com
1838733Sgeoffrey.blake@arm.com    /**
1848733Sgeoffrey.blake@arm.com     * Do a functional lookup on the TLB (for checker cpu) that
1858733Sgeoffrey.blake@arm.com     * behaves like a normal lookup without modifying any page table state.
1868733Sgeoffrey.blake@arm.com     */
1878733Sgeoffrey.blake@arm.com    Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
1888733Sgeoffrey.blake@arm.com
1897436Sdam.sunwoo@arm.com    /** Accessor functions for memory attributes for last accessed TLB entry
1907436Sdam.sunwoo@arm.com     */
1917436Sdam.sunwoo@arm.com    void
1927436Sdam.sunwoo@arm.com    setAttr(uint32_t attr)
1937436Sdam.sunwoo@arm.com    {
1947436Sdam.sunwoo@arm.com        _attr = attr;
1957436Sdam.sunwoo@arm.com    }
1967436Sdam.sunwoo@arm.com    uint32_t
1977436Sdam.sunwoo@arm.com    getAttr() const
1987436Sdam.sunwoo@arm.com    {
1997436Sdam.sunwoo@arm.com        return _attr;
2007436Sdam.sunwoo@arm.com    }
2017436Sdam.sunwoo@arm.com
2027404SAli.Saidi@ARM.com    Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
2038733Sgeoffrey.blake@arm.com            Translation *translation, bool &delay,
2048733Sgeoffrey.blake@arm.com            bool timing, bool functional = false);
2057404SAli.Saidi@ARM.com    Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
2067404SAli.Saidi@ARM.com            Translation *translation, bool &delay, bool timing);
2076116Snate@binkert.org    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
2087404SAli.Saidi@ARM.com    Fault translateTiming(RequestPtr req, ThreadContext *tc,
2096116Snate@binkert.org            Translation *translation, Mode mode);
2109738Sandreas@sandberg.pp.se    Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
2116116Snate@binkert.org
2129439SAndreas.Sandberg@ARM.com    void drainResume();
2139439SAndreas.Sandberg@ARM.com
2146019Shines@cs.fsu.edu    // Checkpointing
2156019Shines@cs.fsu.edu    void serialize(std::ostream &os);
2166019Shines@cs.fsu.edu    void unserialize(Checkpoint *cp, const std::string &section);
2176019Shines@cs.fsu.edu
2186019Shines@cs.fsu.edu    void regStats();
2197749SAli.Saidi@ARM.com
2208922Swilliam.wang@arm.com    /**
2218922Swilliam.wang@arm.com     * Get the table walker master port. This is used for migrating
2228922Swilliam.wang@arm.com     * port connections during a CPU takeOverFrom() call. For
2238922Swilliam.wang@arm.com     * architectures that do not have a table walker, NULL is
2248922Swilliam.wang@arm.com     * returned, hence the use of a pointer rather than a
2258922Swilliam.wang@arm.com     * reference. For ARM this method will always return a valid port
2268922Swilliam.wang@arm.com     * pointer.
2278922Swilliam.wang@arm.com     *
2288922Swilliam.wang@arm.com     * @return A pointer to the walker master port
2298922Swilliam.wang@arm.com     */
2309294Sandreas.hansson@arm.com    virtual BaseMasterPort* getMasterPort();
2317781SAli.Saidi@ARM.com
2327749SAli.Saidi@ARM.com    // Caching misc register values here.
2337749SAli.Saidi@ARM.com    // Writing to misc registers needs to invalidate them.
2347749SAli.Saidi@ARM.com    // translateFunctional/translateSe/translateFs checks if they are
2357749SAli.Saidi@ARM.com    // invalid and call updateMiscReg if necessary.
2367749SAli.Saidi@ARM.comprotected:
2377749SAli.Saidi@ARM.com    SCTLR sctlr;
2387749SAli.Saidi@ARM.com    bool isPriv;
2398552Sdaniel.johnson@arm.com    CONTEXTIDR contextId;
2407749SAli.Saidi@ARM.com    PRRR prrr;
2417749SAli.Saidi@ARM.com    NMRR nmrr;
2427749SAli.Saidi@ARM.com    uint32_t dacr;
2437749SAli.Saidi@ARM.com    bool miscRegValid;
2447749SAli.Saidi@ARM.com    void updateMiscReg(ThreadContext *tc)
2457749SAli.Saidi@ARM.com    {
2467749SAli.Saidi@ARM.com        sctlr = tc->readMiscReg(MISCREG_SCTLR);
2477749SAli.Saidi@ARM.com        CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
2487749SAli.Saidi@ARM.com        isPriv = cpsr.mode != MODE_USER;
2497749SAli.Saidi@ARM.com        contextId = tc->readMiscReg(MISCREG_CONTEXTIDR);
2507749SAli.Saidi@ARM.com        prrr = tc->readMiscReg(MISCREG_PRRR);
2517749SAli.Saidi@ARM.com        nmrr = tc->readMiscReg(MISCREG_NMRR);
2527749SAli.Saidi@ARM.com        dacr = tc->readMiscReg(MISCREG_DACR);
2537749SAli.Saidi@ARM.com        miscRegValid = true;
2547749SAli.Saidi@ARM.com    }
2557749SAli.Saidi@ARM.compublic:
2568299Schander.sudanthi@arm.com    const Params *
2578299Schander.sudanthi@arm.com    params() const
2588299Schander.sudanthi@arm.com    {
2598299Schander.sudanthi@arm.com        return dynamic_cast<const Params *>(_params);
2608299Schander.sudanthi@arm.com    }
2617749SAli.Saidi@ARM.com    inline void invalidateMiscReg() { miscRegValid = false; }
2626019Shines@cs.fsu.edu};
2636019Shines@cs.fsu.edu
2647811Ssteve.reinhardt@amd.com} // namespace ArmISA
2656019Shines@cs.fsu.edu
2666019Shines@cs.fsu.edu#endif // __ARCH_ARM_TLB_HH__
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