tlb.hh revision 7781
16019Shines@cs.fsu.edu/* 27694SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37694SAli.Saidi@ARM.com * All rights reserved 47694SAli.Saidi@ARM.com * 57694SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67694SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77694SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87694SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97694SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107694SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117694SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127694SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137694SAli.Saidi@ARM.com * 146019Shines@cs.fsu.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * All rights reserved. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 266019Shines@cs.fsu.edu * this software without specific prior written permission. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019Shines@cs.fsu.edu * 406019Shines@cs.fsu.edu * Authors: Ali Saidi 416019Shines@cs.fsu.edu */ 426019Shines@cs.fsu.edu 436019Shines@cs.fsu.edu#ifndef __ARCH_ARM_TLB_HH__ 446019Shines@cs.fsu.edu#define __ARCH_ARM_TLB_HH__ 456019Shines@cs.fsu.edu 466019Shines@cs.fsu.edu#include <map> 476019Shines@cs.fsu.edu 487694SAli.Saidi@ARM.com#include "arch/arm/isa_traits.hh" 497694SAli.Saidi@ARM.com#include "arch/arm/utility.hh" 506019Shines@cs.fsu.edu#include "arch/arm/vtophys.hh" 516019Shines@cs.fsu.edu#include "arch/arm/pagetable.hh" 526019Shines@cs.fsu.edu#include "base/statistics.hh" 536019Shines@cs.fsu.edu#include "mem/request.hh" 546019Shines@cs.fsu.edu#include "params/ArmTLB.hh" 556019Shines@cs.fsu.edu#include "sim/fault.hh" 566019Shines@cs.fsu.edu#include "sim/tlb.hh" 576019Shines@cs.fsu.edu 586019Shines@cs.fsu.educlass ThreadContext; 596019Shines@cs.fsu.edu 606019Shines@cs.fsu.edunamespace ArmISA { 616019Shines@cs.fsu.edu 627694SAli.Saidi@ARM.comclass TableWalker; 636019Shines@cs.fsu.edu 646019Shines@cs.fsu.educlass TLB : public BaseTLB 656019Shines@cs.fsu.edu{ 666019Shines@cs.fsu.edu public: 676019Shines@cs.fsu.edu enum ArmFlags { 687694SAli.Saidi@ARM.com AlignmentMask = 0x1f, 697694SAli.Saidi@ARM.com 707694SAli.Saidi@ARM.com AlignByte = 0x0, 717694SAli.Saidi@ARM.com AlignHalfWord = 0x1, 727694SAli.Saidi@ARM.com AlignWord = 0x3, 737694SAli.Saidi@ARM.com AlignDoubleWord = 0x7, 747694SAli.Saidi@ARM.com AlignQuadWord = 0xf, 757694SAli.Saidi@ARM.com AlignOctWord = 0x1f, 767694SAli.Saidi@ARM.com 777694SAli.Saidi@ARM.com AllowUnaligned = 0x20, 787694SAli.Saidi@ARM.com // Priv code operating as if it wasn't 797694SAli.Saidi@ARM.com UserMode = 0x40, 807694SAli.Saidi@ARM.com // Because zero otherwise looks like a valid setting and may be used 817694SAli.Saidi@ARM.com // accidentally, this bit must be non-zero to show it was used on 827694SAli.Saidi@ARM.com // purpose. 837694SAli.Saidi@ARM.com MustBeOne = 0x80 847694SAli.Saidi@ARM.com }; 857694SAli.Saidi@ARM.com protected: 867694SAli.Saidi@ARM.com 877694SAli.Saidi@ARM.com TlbEntry *table; // the Page Table 887694SAli.Saidi@ARM.com int size; // TLB Size 897694SAli.Saidi@ARM.com 907694SAli.Saidi@ARM.com uint32_t _attr; // Memory attributes for last accessed TLB entry 917694SAli.Saidi@ARM.com 927694SAli.Saidi@ARM.com#if FULL_SYSTEM 937694SAli.Saidi@ARM.com TableWalker *tableWalker; 947694SAli.Saidi@ARM.com#endif 957694SAli.Saidi@ARM.com 967694SAli.Saidi@ARM.com /** Lookup an entry in the TLB 977694SAli.Saidi@ARM.com * @param vpn virtual address 987694SAli.Saidi@ARM.com * @param asn context id/address space id to use 997694SAli.Saidi@ARM.com * @param functional if the lookup should modify state 1007694SAli.Saidi@ARM.com * @return pointer to TLB entrry if it exists 1017694SAli.Saidi@ARM.com */ 1027694SAli.Saidi@ARM.com TlbEntry *lookup(Addr vpn, uint8_t asn, bool functional = false); 1037694SAli.Saidi@ARM.com 1047694SAli.Saidi@ARM.com // Access Stats 1057694SAli.Saidi@ARM.com mutable Stats::Scalar instHits; 1067694SAli.Saidi@ARM.com mutable Stats::Scalar instMisses; 1077694SAli.Saidi@ARM.com mutable Stats::Scalar readHits; 1087694SAli.Saidi@ARM.com mutable Stats::Scalar readMisses; 1097694SAli.Saidi@ARM.com mutable Stats::Scalar writeHits; 1107694SAli.Saidi@ARM.com mutable Stats::Scalar writeMisses; 1117694SAli.Saidi@ARM.com mutable Stats::Scalar inserts; 1127694SAli.Saidi@ARM.com mutable Stats::Scalar flushTlb; 1137694SAli.Saidi@ARM.com mutable Stats::Scalar flushTlbMva; 1147694SAli.Saidi@ARM.com mutable Stats::Scalar flushTlbMvaAsid; 1157694SAli.Saidi@ARM.com mutable Stats::Scalar flushTlbAsid; 1167694SAli.Saidi@ARM.com mutable Stats::Scalar flushedEntries; 1177694SAli.Saidi@ARM.com mutable Stats::Scalar alignFaults; 1187694SAli.Saidi@ARM.com mutable Stats::Scalar prefetchFaults; 1197694SAli.Saidi@ARM.com mutable Stats::Scalar domainFaults; 1207694SAli.Saidi@ARM.com mutable Stats::Scalar permsFaults; 1217694SAli.Saidi@ARM.com 1227694SAli.Saidi@ARM.com Stats::Formula readAccesses; 1237694SAli.Saidi@ARM.com Stats::Formula writeAccesses; 1247694SAli.Saidi@ARM.com Stats::Formula instAccesses; 1257694SAli.Saidi@ARM.com Stats::Formula hits; 1267694SAli.Saidi@ARM.com Stats::Formula misses; 1277694SAli.Saidi@ARM.com Stats::Formula accesses; 1286019Shines@cs.fsu.edu 1296019Shines@cs.fsu.edu int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU 1307694SAli.Saidi@ARM.com 1317694SAli.Saidi@ARM.com public: 1327694SAli.Saidi@ARM.com typedef ArmTLBParams Params; 1337694SAli.Saidi@ARM.com TLB(const Params *p); 1347694SAli.Saidi@ARM.com 1357694SAli.Saidi@ARM.com virtual ~TLB(); 1367694SAli.Saidi@ARM.com int getsize() const { return size; } 1377694SAli.Saidi@ARM.com 1387694SAli.Saidi@ARM.com void insert(Addr vaddr, TlbEntry &pte); 139 140 /** Reset the entire TLB */ 141 void flushAll(); 142 143 /** Remove any entries that match both a va and asn 144 * @param mva virtual address to flush 145 * @param asn contextid/asn to flush on match 146 */ 147 void flushMvaAsid(Addr mva, uint64_t asn); 148 149 /** Remove any entries that match the asn 150 * @param asn contextid/asn to flush on match 151 */ 152 void flushAsid(uint64_t asn); 153 154 /** Remove all entries that match the va regardless of asn 155 * @param mva address to flush from cache 156 */ 157 void flushMva(Addr mva); 158 159 Fault trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp); 160 Fault walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec, 161 bool is_write, uint8_t domain, bool sNp); 162 163 void printTlb(); 164 165 void demapPage(Addr vaddr, uint64_t asn) 166 { 167 flushMvaAsid(vaddr, asn); 168 } 169 170 static bool validVirtualAddress(Addr vaddr); 171 172 /** 173 * Do a functional lookup on the TLB (for debugging) 174 * and don't modify any internal state 175 * @param tc thread context to get the context id from 176 * @param vaddr virtual address to translate 177 * @param pa returned physical address 178 * @return if the translation was successful 179 */ 180 bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr); 181 182 /** Accessor functions for memory attributes for last accessed TLB entry 183 */ 184 void 185 setAttr(uint32_t attr) 186 { 187 _attr = attr; 188 } 189 uint32_t 190 getAttr() const 191 { 192 return _attr; 193 } 194 195#if FULL_SYSTEM 196 Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 197 Translation *translation, bool &delay, bool timing); 198#else 199 Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 200 Translation *translation, bool &delay, bool timing); 201#endif 202 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); 203 Fault translateTiming(RequestPtr req, ThreadContext *tc, 204 Translation *translation, Mode mode); 205 206 // Checkpointing 207 void serialize(std::ostream &os); 208 void unserialize(Checkpoint *cp, const std::string §ion); 209 210 void regStats(); 211 212 // Get the port from the table walker and return it 213 virtual Port *getPort(); 214 215 // Caching misc register values here. 216 // Writing to misc registers needs to invalidate them. 217 // translateFunctional/translateSe/translateFs checks if they are 218 // invalid and call updateMiscReg if necessary. 219protected: 220 SCTLR sctlr; 221 bool isPriv; 222 uint32_t contextId; 223 PRRR prrr; 224 NMRR nmrr; 225 uint32_t dacr; 226 bool miscRegValid; 227 void updateMiscReg(ThreadContext *tc) 228 { 229 sctlr = tc->readMiscReg(MISCREG_SCTLR); 230 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 231 isPriv = cpsr.mode != MODE_USER; 232 contextId = tc->readMiscReg(MISCREG_CONTEXTIDR); 233 prrr = tc->readMiscReg(MISCREG_PRRR); 234 nmrr = tc->readMiscReg(MISCREG_NMRR); 235 dacr = tc->readMiscReg(MISCREG_DACR); 236 miscRegValid = true; 237 } 238public: 239 inline void invalidateMiscReg() { miscRegValid = false; } 240}; 241 242/* namespace ArmISA */ } 243 244#endif // __ARCH_ARM_TLB_HH__ 245