tlb.hh revision 7734
112653Sandreas.sandberg@arm.com/* 212653Sandreas.sandberg@arm.com * Copyright (c) 2010 ARM Limited 312653Sandreas.sandberg@arm.com * All rights reserved 412653Sandreas.sandberg@arm.com * 512653Sandreas.sandberg@arm.com * The license below extends only to copyright in the software and shall 612653Sandreas.sandberg@arm.com * not be construed as granting a license to any other intellectual 712653Sandreas.sandberg@arm.com * property including but not limited to intellectual property relating 812653Sandreas.sandberg@arm.com * to a hardware implementation of the functionality of the software 912653Sandreas.sandberg@arm.com * licensed hereunder. You may use the software subject to the license 1012653Sandreas.sandberg@arm.com * terms below provided that you ensure that this notice is replicated 1112653Sandreas.sandberg@arm.com * unmodified and in its entirety in all distributions of the software, 1212653Sandreas.sandberg@arm.com * modified or unmodified, in source code or in binary form. 1312653Sandreas.sandberg@arm.com * 1412653Sandreas.sandberg@arm.com * Copyright (c) 2001-2005 The Regents of The University of Michigan 1512653Sandreas.sandberg@arm.com * All rights reserved. 1612653Sandreas.sandberg@arm.com * 1712653Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 1812653Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 1912653Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 2012653Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 2112653Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 2212653Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 2312653Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 2412653Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 2512653Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 2612653Sandreas.sandberg@arm.com * this software without specific prior written permission. 2712653Sandreas.sandberg@arm.com * 2812653Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2912653Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3012653Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3112653Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3212653Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3312653Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3412653Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3512653Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3612653Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3712653Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3812653Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3912653Sandreas.sandberg@arm.com * 4012653Sandreas.sandberg@arm.com * Authors: Ali Saidi 4112653Sandreas.sandberg@arm.com */ 4212653Sandreas.sandberg@arm.com 4312653Sandreas.sandberg@arm.com#ifndef __ARCH_ARM_TLB_HH__ 4412653Sandreas.sandberg@arm.com#define __ARCH_ARM_TLB_HH__ 4512653Sandreas.sandberg@arm.com 4612653Sandreas.sandberg@arm.com#include <map> 4712653Sandreas.sandberg@arm.com 4812653Sandreas.sandberg@arm.com#include "arch/arm/isa_traits.hh" 4912653Sandreas.sandberg@arm.com#include "arch/arm/utility.hh" 5012653Sandreas.sandberg@arm.com#include "arch/arm/vtophys.hh" 5112653Sandreas.sandberg@arm.com#include "arch/arm/pagetable.hh" 5212653Sandreas.sandberg@arm.com#include "base/statistics.hh" 5312653Sandreas.sandberg@arm.com#include "mem/request.hh" 5412653Sandreas.sandberg@arm.com#include "params/ArmTLB.hh" 5512653Sandreas.sandberg@arm.com#include "sim/fault.hh" 5612653Sandreas.sandberg@arm.com#include "sim/tlb.hh" 5712653Sandreas.sandberg@arm.com 5812653Sandreas.sandberg@arm.comclass ThreadContext; 5912653Sandreas.sandberg@arm.com 6012653Sandreas.sandberg@arm.comnamespace ArmISA { 6112653Sandreas.sandberg@arm.com 6212653Sandreas.sandberg@arm.comclass TableWalker; 6312653Sandreas.sandberg@arm.com 6412653Sandreas.sandberg@arm.comclass TLB : public BaseTLB 6512653Sandreas.sandberg@arm.com{ 6612653Sandreas.sandberg@arm.com public: 6712653Sandreas.sandberg@arm.com enum ArmFlags { 6812653Sandreas.sandberg@arm.com AlignmentMask = 0x1f, 6912653Sandreas.sandberg@arm.com 7012653Sandreas.sandberg@arm.com AlignByte = 0x0, 7112653Sandreas.sandberg@arm.com AlignHalfWord = 0x1, 7212653Sandreas.sandberg@arm.com AlignWord = 0x3, 7312653Sandreas.sandberg@arm.com AlignDoubleWord = 0x7, 7412653Sandreas.sandberg@arm.com AlignQuadWord = 0xf, 7512653Sandreas.sandberg@arm.com AlignOctWord = 0x1f, 7612653Sandreas.sandberg@arm.com 7712653Sandreas.sandberg@arm.com AllowUnaligned = 0x20, 7812653Sandreas.sandberg@arm.com // Priv code operating as if it wasn't 7912653Sandreas.sandberg@arm.com UserMode = 0x40, 8012653Sandreas.sandberg@arm.com // Because zero otherwise looks like a valid setting and may be used 8112653Sandreas.sandberg@arm.com // accidentally, this bit must be non-zero to show it was used on 8212653Sandreas.sandberg@arm.com // purpose. 8312653Sandreas.sandberg@arm.com MustBeOne = 0x80 8412653Sandreas.sandberg@arm.com }; 8512653Sandreas.sandberg@arm.com protected: 8612653Sandreas.sandberg@arm.com 8712653Sandreas.sandberg@arm.com TlbEntry *table; // the Page Table 8812653Sandreas.sandberg@arm.com int size; // TLB Size 8912653Sandreas.sandberg@arm.com 9012653Sandreas.sandberg@arm.com uint32_t _attr; // Memory attributes for last accessed TLB entry 9112653Sandreas.sandberg@arm.com 9212653Sandreas.sandberg@arm.com#if FULL_SYSTEM 9312653Sandreas.sandberg@arm.com TableWalker *tableWalker; 9412653Sandreas.sandberg@arm.com#endif 9512653Sandreas.sandberg@arm.com 9612653Sandreas.sandberg@arm.com /** Lookup an entry in the TLB 9712653Sandreas.sandberg@arm.com * @param vpn virtual address 9812653Sandreas.sandberg@arm.com * @param asn context id/address space id to use 9912653Sandreas.sandberg@arm.com * @param functional if the lookup should modify state 10012653Sandreas.sandberg@arm.com * @return pointer to TLB entrry if it exists 10112653Sandreas.sandberg@arm.com */ 10212653Sandreas.sandberg@arm.com TlbEntry *lookup(Addr vpn, uint8_t asn, bool functional = false); 10312653Sandreas.sandberg@arm.com 10412653Sandreas.sandberg@arm.com // Access Stats 10512653Sandreas.sandberg@arm.com mutable Stats::Scalar instHits; 10612653Sandreas.sandberg@arm.com mutable Stats::Scalar instMisses; 10712653Sandreas.sandberg@arm.com mutable Stats::Scalar readHits; 10812653Sandreas.sandberg@arm.com mutable Stats::Scalar readMisses; 10912653Sandreas.sandberg@arm.com mutable Stats::Scalar writeHits; 11012653Sandreas.sandberg@arm.com mutable Stats::Scalar writeMisses; 11112653Sandreas.sandberg@arm.com mutable Stats::Scalar inserts; 11212653Sandreas.sandberg@arm.com mutable Stats::Scalar flushTlb; 11312653Sandreas.sandberg@arm.com mutable Stats::Scalar flushTlbMva; 11412653Sandreas.sandberg@arm.com mutable Stats::Scalar flushTlbMvaAsid; 11512653Sandreas.sandberg@arm.com mutable Stats::Scalar flushTlbAsid; 11612653Sandreas.sandberg@arm.com mutable Stats::Scalar flushedEntries; 11712653Sandreas.sandberg@arm.com mutable Stats::Scalar alignFaults; 11812653Sandreas.sandberg@arm.com mutable Stats::Scalar prefetchFaults; 11912653Sandreas.sandberg@arm.com mutable Stats::Scalar domainFaults; 12012653Sandreas.sandberg@arm.com mutable Stats::Scalar permsFaults; 12112653Sandreas.sandberg@arm.com 12212653Sandreas.sandberg@arm.com Stats::Formula readAccesses; 12312653Sandreas.sandberg@arm.com Stats::Formula writeAccesses; 12412653Sandreas.sandberg@arm.com Stats::Formula instAccesses; 12512653Sandreas.sandberg@arm.com Stats::Formula hits; 12612653Sandreas.sandberg@arm.com Stats::Formula misses; 12712653Sandreas.sandberg@arm.com Stats::Formula accesses; 12812653Sandreas.sandberg@arm.com 12912653Sandreas.sandberg@arm.com int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU 13012653Sandreas.sandberg@arm.com 13112653Sandreas.sandberg@arm.com public: 13212653Sandreas.sandberg@arm.com typedef ArmTLBParams Params; 13312653Sandreas.sandberg@arm.com TLB(const Params *p); 13412653Sandreas.sandberg@arm.com 135 virtual ~TLB(); 136 int getsize() const { return size; } 137 138 void insert(Addr vaddr, TlbEntry &pte); 139 140 /** Reset the entire TLB */ 141 void flushAll(); 142 143 /** Remove any entries that match both a va and asn 144 * @param mva virtual address to flush 145 * @param asn contextid/asn to flush on match 146 */ 147 void flushMvaAsid(Addr mva, uint64_t asn); 148 149 /** Remove any entries that match the asn 150 * @param asn contextid/asn to flush on match 151 */ 152 void flushAsid(uint64_t asn); 153 154 /** Remove all entries that match the va regardless of asn 155 * @param mva address to flush from cache 156 */ 157 void flushMva(Addr mva); 158 159 Fault trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp); 160 Fault walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec, 161 bool is_write, uint8_t domain, bool sNp); 162 163 void printTlb(); 164 165 void demapPage(Addr vaddr, uint64_t asn) 166 { 167 flushMvaAsid(vaddr, asn); 168 } 169 170 static bool validVirtualAddress(Addr vaddr); 171 172 /** 173 * Do a functional lookup on the TLB (for debugging) 174 * and don't modify any internal state 175 * @param tc thread context to get the context id from 176 * @param vaddr virtual address to translate 177 * @param pa returned physical address 178 * @return if the translation was successful 179 */ 180 bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr); 181 182 /** Accessor functions for memory attributes for last accessed TLB entry 183 */ 184 void 185 setAttr(uint32_t attr) 186 { 187 _attr = attr; 188 } 189 uint32_t 190 getAttr() const 191 { 192 return _attr; 193 } 194 195#if FULL_SYSTEM 196 Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 197 Translation *translation, bool &delay, bool timing); 198#else 199 Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 200 Translation *translation, bool &delay, bool timing); 201#endif 202 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); 203 Fault translateTiming(RequestPtr req, ThreadContext *tc, 204 Translation *translation, Mode mode); 205 206 // Checkpointing 207 void serialize(std::ostream &os); 208 void unserialize(Checkpoint *cp, const std::string §ion); 209 210 void regStats(); 211}; 212 213/* namespace ArmISA */ } 214 215#endif // __ARCH_ARM_TLB_HH__ 216