tlb.hh revision 7436
14120SN/A/* 24120SN/A * Copyright (c) 2010 ARM Limited 39917Ssteve.reinhardt@amd.com * All rights reserved 44120SN/A * 54120SN/A * The license below extends only to copyright in the software and shall 67087Snate@binkert.org * not be construed as granting a license to any other intellectual 77087Snate@binkert.org * property including but not limited to intellectual property relating 87087Snate@binkert.org * to a hardware implementation of the functionality of the software 97087Snate@binkert.org * licensed hereunder. You may use the software subject to the license 107087Snate@binkert.org * terms below provided that you ensure that this notice is replicated 117087Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 127087Snate@binkert.org * modified or unmodified, in source code or in binary form. 137087Snate@binkert.org * 144120SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 157087Snate@binkert.org * All rights reserved. 167087Snate@binkert.org * 177087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 187087Snate@binkert.org * modification, are permitted provided that the following conditions are 197087Snate@binkert.org * met: redistributions of source code must retain the above copyright 207087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 217087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 227087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 234120SN/A * documentation and/or other materials provided with the distribution; 247087Snate@binkert.org * neither the name of the copyright holders nor the names of its 254120SN/A * contributors may be used to endorse or promote products derived from 264120SN/A * this software without specific prior written permission. 274120SN/A * 284120SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294120SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 304120SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 314120SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 324120SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334120SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344120SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354120SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 364120SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374120SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 384120SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394120SN/A * 404120SN/A * Authors: Ali Saidi 416329Sgblack@eecs.umich.edu */ 426329Sgblack@eecs.umich.edu 436216SN/A#ifndef __ARCH_ARM_TLB_HH__ 448961Sgblack@eecs.umich.edu#define __ARCH_ARM_TLB_HH__ 457629Sgblack@eecs.umich.edu 469921Syasuko.eckert@amd.com#include <map> 477629Sgblack@eecs.umich.edu 486315SN/A#include "arch/arm/isa_traits.hh" 494137SN/A#include "arch/arm/utility.hh" 504120SN/A#include "arch/arm/vtophys.hh" 514120SN/A#include "arch/arm/pagetable.hh" 526329Sgblack@eecs.umich.edu#include "base/statistics.hh" 536329Sgblack@eecs.umich.edu#include "mem/request.hh" 549046SAli.Saidi@ARM.com#include "params/ArmTLB.hh" 556329Sgblack@eecs.umich.edu#include "sim/faults.hh" 566313SN/A#include "sim/tlb.hh" 576329Sgblack@eecs.umich.edu 589921Syasuko.eckert@amd.comclass ThreadContext; 599921Syasuko.eckert@amd.com 609921Syasuko.eckert@amd.comnamespace ArmISA { 619921Syasuko.eckert@amd.com 626319SN/Aclass TableWalker; 639917Ssteve.reinhardt@amd.com 649917Ssteve.reinhardt@amd.comclass TLB : public BaseTLB 656329Sgblack@eecs.umich.edu{ 669917Ssteve.reinhardt@amd.com public: 676315SN/A enum ArmFlags { 686329Sgblack@eecs.umich.edu AlignmentMask = 0x7, 696329Sgblack@eecs.umich.edu 709918Ssteve.reinhardt@amd.com AlignByte = 0x0, 719917Ssteve.reinhardt@amd.com AlignHalfWord = 0x1, 729917Ssteve.reinhardt@amd.com AlignWord = 0x3, 739918Ssteve.reinhardt@amd.com AlignDoubleWord = 0x7, 749920Syasuko.eckert@amd.com 7510935Snilay@cs.wisc.edu AllowUnaligned = 0x8, 769918Ssteve.reinhardt@amd.com // Priv code operating as if it wasn't 776329Sgblack@eecs.umich.edu UserMode = 0x10, 784137SN/A // Because zero otherwise looks like a valid setting and may be used 796329Sgblack@eecs.umich.edu // accidentally, this bit must be non-zero to show it was used on 806329Sgblack@eecs.umich.edu // purpose. 816329Sgblack@eecs.umich.edu MustBeOne = 0x20 826329Sgblack@eecs.umich.edu }; 836329Sgblack@eecs.umich.edu protected: 846329Sgblack@eecs.umich.edu typedef std::multimap<Addr, int> PageTable; 856329Sgblack@eecs.umich.edu PageTable lookupTable; // Quick lookup into page table 866329Sgblack@eecs.umich.edu 874137SN/A TlbEntry *table; // the Page Table 886329Sgblack@eecs.umich.edu int size; // TLB Size 896329Sgblack@eecs.umich.edu int nlu; // not last used entry (for replacement) 906329Sgblack@eecs.umich.edu 916329Sgblack@eecs.umich.edu uint32_t _attr; // Memory attributes for last accessed TLB entry 926329Sgblack@eecs.umich.edu 939920Syasuko.eckert@amd.com#if FULL_SYSTEM 946329Sgblack@eecs.umich.edu TableWalker *tableWalker; 956329Sgblack@eecs.umich.edu#endif 966329Sgblack@eecs.umich.edu 976329Sgblack@eecs.umich.edu void nextnlu() { if (++nlu >= size) nlu = 0; } 986329Sgblack@eecs.umich.edu TlbEntry *lookup(Addr vpn, uint8_t asn); 996329Sgblack@eecs.umich.edu 1006329Sgblack@eecs.umich.edu // Access Stats 1016329Sgblack@eecs.umich.edu mutable Stats::Scalar read_hits; 1026329Sgblack@eecs.umich.edu mutable Stats::Scalar read_misses; 1036329Sgblack@eecs.umich.edu mutable Stats::Scalar read_acv; 1046329Sgblack@eecs.umich.edu mutable Stats::Scalar read_accesses; 1056329Sgblack@eecs.umich.edu mutable Stats::Scalar write_hits; 1069921Syasuko.eckert@amd.com mutable Stats::Scalar write_misses; 1076329Sgblack@eecs.umich.edu mutable Stats::Scalar write_acv; 1086329Sgblack@eecs.umich.edu mutable Stats::Scalar write_accesses; 1096329Sgblack@eecs.umich.edu Stats::Formula hits; 1106329Sgblack@eecs.umich.edu Stats::Formula misses; 1114137SN/A Stats::Formula invalids; 1127811Ssteve.reinhardt@amd.com Stats::Formula accesses; 1134120SN/A 1144120SN/A 115 public: 116 typedef ArmTLBParams Params; 117 TLB(const Params *p); 118 119 virtual ~TLB(); 120 int getsize() const { return size; } 121 122 void insert(Addr vaddr, TlbEntry &pte); 123 124 /** Reset the entire TLB */ 125 void flushAll(); 126 127 /** Remove any entries that match both a va and asn 128 * @param mva virtual address to flush 129 * @param asn contextid/asn to flush on match 130 */ 131 void flushMvaAsid(Addr mva, uint64_t asn); 132 133 /** Remove any entries that match the asn 134 * @param asn contextid/asn to flush on match 135 */ 136 void flushAsid(uint64_t asn); 137 138 /** Remove all entries that match the va regardless of asn 139 * @param mva address to flush from cache 140 */ 141 void flushMva(Addr mva); 142 143 Fault trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp); 144 Fault walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec, 145 bool is_write, uint8_t domain, bool sNp); 146 147 void printTlb(); 148 149 void demapPage(Addr vaddr, uint64_t asn) 150 { 151 flushMvaAsid(vaddr, asn); 152 } 153 154 static bool validVirtualAddress(Addr vaddr); 155 156 /** Accessor functions for memory attributes for last accessed TLB entry 157 */ 158 void 159 setAttr(uint32_t attr) 160 { 161 _attr = attr; 162 } 163 uint32_t 164 getAttr() const 165 { 166 return _attr; 167 } 168 169#if FULL_SYSTEM 170 Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 171 Translation *translation, bool &delay, bool timing); 172#else 173 Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 174 Translation *translation, bool &delay, bool timing); 175#endif 176 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); 177 Fault translateTiming(RequestPtr req, ThreadContext *tc, 178 Translation *translation, Mode mode); 179 180 // Checkpointing 181 void serialize(std::ostream &os); 182 void unserialize(Checkpoint *cp, const std::string §ion); 183 184 void regStats(); 185}; 186 187/* namespace ArmISA */ } 188 189#endif // __ARCH_ARM_TLB_HH__ 190