tlb.hh revision 7406
16019Shines@cs.fsu.edu/*
27399SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited
37399SAli.Saidi@ARM.com * All rights reserved
47399SAli.Saidi@ARM.com *
57399SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall
67399SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual
77399SAli.Saidi@ARM.com * property including but not limited to intellectual property relating
87399SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software
97399SAli.Saidi@ARM.com * licensed hereunder.  You may use the software subject to the license
107399SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated
117399SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software,
127399SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form.
137399SAli.Saidi@ARM.com *
146019Shines@cs.fsu.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan
156019Shines@cs.fsu.edu * All rights reserved.
166019Shines@cs.fsu.edu *
176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without
186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are
196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright
206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer;
216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright
226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the
236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution;
246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its
256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from
266019Shines@cs.fsu.edu * this software without specific prior written permission.
276019Shines@cs.fsu.edu *
286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
396019Shines@cs.fsu.edu *
407399SAli.Saidi@ARM.com * Authors: Ali Saidi
416019Shines@cs.fsu.edu */
426019Shines@cs.fsu.edu
436019Shines@cs.fsu.edu#ifndef __ARCH_ARM_TLB_HH__
446019Shines@cs.fsu.edu#define __ARCH_ARM_TLB_HH__
456019Shines@cs.fsu.edu
466019Shines@cs.fsu.edu#include <map>
476019Shines@cs.fsu.edu
486019Shines@cs.fsu.edu#include "arch/arm/isa_traits.hh"
496019Shines@cs.fsu.edu#include "arch/arm/utility.hh"
506019Shines@cs.fsu.edu#include "arch/arm/vtophys.hh"
516019Shines@cs.fsu.edu#include "arch/arm/pagetable.hh"
526019Shines@cs.fsu.edu#include "base/statistics.hh"
536019Shines@cs.fsu.edu#include "mem/request.hh"
546116Snate@binkert.org#include "params/ArmTLB.hh"
556019Shines@cs.fsu.edu#include "sim/faults.hh"
566019Shines@cs.fsu.edu#include "sim/tlb.hh"
576019Shines@cs.fsu.edu
586019Shines@cs.fsu.educlass ThreadContext;
596019Shines@cs.fsu.edu
606019Shines@cs.fsu.edunamespace ArmISA {
616019Shines@cs.fsu.edu
627404SAli.Saidi@ARM.comclass TableWalker;
637404SAli.Saidi@ARM.com
646019Shines@cs.fsu.educlass TLB : public BaseTLB
656019Shines@cs.fsu.edu{
667294Sgblack@eecs.umich.edu  public:
677294Sgblack@eecs.umich.edu    enum ArmFlags {
687294Sgblack@eecs.umich.edu        AlignmentMask = 0x7,
697294Sgblack@eecs.umich.edu
707294Sgblack@eecs.umich.edu        AlignByte = 0x0,
717294Sgblack@eecs.umich.edu        AlignHalfWord = 0x1,
727294Sgblack@eecs.umich.edu        AlignWord = 0x3,
737294Sgblack@eecs.umich.edu        AlignDoubleWord = 0x7,
747294Sgblack@eecs.umich.edu
757294Sgblack@eecs.umich.edu        AllowUnaligned = 0x8,
767404SAli.Saidi@ARM.com        // Priv code operating as if it wasn't
777404SAli.Saidi@ARM.com        UserMode = 0x10,
787294Sgblack@eecs.umich.edu        // Because zero otherwise looks like a valid setting and may be used
797294Sgblack@eecs.umich.edu        // accidentally, this bit must be non-zero to show it was used on
807294Sgblack@eecs.umich.edu        // purpose.
817404SAli.Saidi@ARM.com        MustBeOne = 0x20
827294Sgblack@eecs.umich.edu    };
836019Shines@cs.fsu.edu  protected:
846019Shines@cs.fsu.edu    typedef std::multimap<Addr, int> PageTable;
856019Shines@cs.fsu.edu    PageTable lookupTable;	// Quick lookup into page table
866019Shines@cs.fsu.edu
877404SAli.Saidi@ARM.com    TlbEntry *table;	// the Page Table
886019Shines@cs.fsu.edu    int size;			// TLB Size
896019Shines@cs.fsu.edu    int nlu;			// not last used entry (for replacement)
907406SAli.Saidi@ARM.com
917406SAli.Saidi@ARM.com#if FULL_SYSTEM
927404SAli.Saidi@ARM.com    TableWalker *tableWalker;
937406SAli.Saidi@ARM.com#endif
946019Shines@cs.fsu.edu
956019Shines@cs.fsu.edu    void nextnlu() { if (++nlu >= size) nlu = 0; }
967404SAli.Saidi@ARM.com    TlbEntry *lookup(Addr vpn, uint8_t asn);
976019Shines@cs.fsu.edu
987399SAli.Saidi@ARM.com    // Access Stats
996020Sgblack@eecs.umich.edu    mutable Stats::Scalar read_hits;
1006020Sgblack@eecs.umich.edu    mutable Stats::Scalar read_misses;
1016020Sgblack@eecs.umich.edu    mutable Stats::Scalar read_acv;
1026020Sgblack@eecs.umich.edu    mutable Stats::Scalar read_accesses;
1036020Sgblack@eecs.umich.edu    mutable Stats::Scalar write_hits;
1046020Sgblack@eecs.umich.edu    mutable Stats::Scalar write_misses;
1056020Sgblack@eecs.umich.edu    mutable Stats::Scalar write_acv;
1066020Sgblack@eecs.umich.edu    mutable Stats::Scalar write_accesses;
1076019Shines@cs.fsu.edu    Stats::Formula hits;
1086019Shines@cs.fsu.edu    Stats::Formula misses;
1096019Shines@cs.fsu.edu    Stats::Formula invalids;
1106019Shines@cs.fsu.edu    Stats::Formula accesses;
1116019Shines@cs.fsu.edu
1127404SAli.Saidi@ARM.com
1136019Shines@cs.fsu.edu  public:
1146019Shines@cs.fsu.edu    typedef ArmTLBParams Params;
1156019Shines@cs.fsu.edu    TLB(const Params *p);
1166019Shines@cs.fsu.edu
1176019Shines@cs.fsu.edu    virtual ~TLB();
1186019Shines@cs.fsu.edu    int getsize() const { return size; }
1196019Shines@cs.fsu.edu
1207404SAli.Saidi@ARM.com    void insert(Addr vaddr, TlbEntry &pte);
1217404SAli.Saidi@ARM.com
1227404SAli.Saidi@ARM.com    /** Reset the entire TLB */
1236019Shines@cs.fsu.edu    void flushAll();
1247404SAli.Saidi@ARM.com
1257404SAli.Saidi@ARM.com    /** Remove any entries that match both a va and asn
1267404SAli.Saidi@ARM.com     * @param mva virtual address to flush
1277404SAli.Saidi@ARM.com     * @param asn contextid/asn to flush on match
1287404SAli.Saidi@ARM.com     */
1297404SAli.Saidi@ARM.com    void flushMvaAsid(Addr mva, uint64_t asn);
1307404SAli.Saidi@ARM.com
1317404SAli.Saidi@ARM.com    /** Remove any entries that match the asn
1327404SAli.Saidi@ARM.com     * @param asn contextid/asn to flush on match
1337404SAli.Saidi@ARM.com     */
1347404SAli.Saidi@ARM.com    void flushAsid(uint64_t asn);
1357404SAli.Saidi@ARM.com
1367404SAli.Saidi@ARM.com    /** Remove all entries that match the va regardless of asn
1377404SAli.Saidi@ARM.com     * @param mva address to flush from cache
1387404SAli.Saidi@ARM.com     */
1397404SAli.Saidi@ARM.com    void flushMva(Addr mva);
1407404SAli.Saidi@ARM.com
1417404SAli.Saidi@ARM.com    Fault trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp);
1427406SAli.Saidi@ARM.com    Fault walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
1437406SAli.Saidi@ARM.com            bool is_write, uint8_t domain, bool sNp);
1447404SAli.Saidi@ARM.com
1457404SAli.Saidi@ARM.com    void printTlb();
1467404SAli.Saidi@ARM.com
1476019Shines@cs.fsu.edu    void demapPage(Addr vaddr, uint64_t asn)
1486019Shines@cs.fsu.edu    {
1497404SAli.Saidi@ARM.com        flushMvaAsid(vaddr, asn);
1506019Shines@cs.fsu.edu    }
1516019Shines@cs.fsu.edu
1526019Shines@cs.fsu.edu    static bool validVirtualAddress(Addr vaddr);
1536019Shines@cs.fsu.edu
1547404SAli.Saidi@ARM.com#if FULL_SYSTEM
1557404SAli.Saidi@ARM.com    Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
1567404SAli.Saidi@ARM.com            Translation *translation, bool &delay, bool timing);
1577404SAli.Saidi@ARM.com#else
1587404SAli.Saidi@ARM.com    Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
1597404SAli.Saidi@ARM.com            Translation *translation, bool &delay, bool timing);
1607404SAli.Saidi@ARM.com#endif
1616116Snate@binkert.org    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
1627404SAli.Saidi@ARM.com    Fault translateTiming(RequestPtr req, ThreadContext *tc,
1636116Snate@binkert.org            Translation *translation, Mode mode);
1646116Snate@binkert.org
1656019Shines@cs.fsu.edu    // Checkpointing
1666019Shines@cs.fsu.edu    void serialize(std::ostream &os);
1676019Shines@cs.fsu.edu    void unserialize(Checkpoint *cp, const std::string &section);
1686019Shines@cs.fsu.edu
1696019Shines@cs.fsu.edu    void regStats();
1706019Shines@cs.fsu.edu};
1716019Shines@cs.fsu.edu
1726116Snate@binkert.org/* namespace ArmISA */ }
1736019Shines@cs.fsu.edu
1746019Shines@cs.fsu.edu#endif // __ARCH_ARM_TLB_HH__
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