tlb.hh revision 12406
12497SN/A/* 214006Stiago.muck@arm.com * Copyright (c) 2010-2013, 2016 ARM Limited 38711SN/A * All rights reserved 48711SN/A * 58711SN/A * The license below extends only to copyright in the software and shall 68711SN/A * not be construed as granting a license to any other intellectual 78711SN/A * property including but not limited to intellectual property relating 88711SN/A * to a hardware implementation of the functionality of the software 98711SN/A * licensed hereunder. You may use the software subject to the license 108711SN/A * terms below provided that you ensure that this notice is replicated 118711SN/A * unmodified and in its entirety in all distributions of the software, 128711SN/A * modified or unmodified, in source code or in binary form. 138711SN/A * 142497SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 152497SN/A * All rights reserved. 162497SN/A * 172497SN/A * Redistribution and use in source and binary forms, with or without 182497SN/A * modification, are permitted provided that the following conditions are 192497SN/A * met: redistributions of source code must retain the above copyright 202497SN/A * notice, this list of conditions and the following disclaimer; 212497SN/A * redistributions in binary form must reproduce the above copyright 222497SN/A * notice, this list of conditions and the following disclaimer in the 232497SN/A * documentation and/or other materials provided with the distribution; 242497SN/A * neither the name of the copyright holders nor the names of its 252497SN/A * contributors may be used to endorse or promote products derived from 262497SN/A * this software without specific prior written permission. 272497SN/A * 282497SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292497SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302497SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312497SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322497SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332497SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342497SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352497SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362497SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372497SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382497SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Ali Saidi 418715SN/A */ 428922SN/A 4312351Snikos.nikoleris@arm.com#ifndef __ARCH_ARM_TLB_HH__ 442497SN/A#define __ARCH_ARM_TLB_HH__ 452497SN/A 462497SN/A 472982SN/A#include "arch/arm/isa_traits.hh" 4810405Sandreas.hansson@arm.com#include "arch/arm/pagetable.hh" 492497SN/A#include "arch/arm/utility.hh" 502497SN/A#include "arch/arm/vtophys.hh" 5111793Sbrandon.potter@amd.com#include "arch/generic/tlb.hh" 5211793Sbrandon.potter@amd.com#include "base/statistics.hh" 5312334Sgabeblack@google.com#include "mem/request.hh" 542548SN/A#include "params/ArmTLB.hh" 5510405Sandreas.hansson@arm.com#include "sim/probe/pmu.hh" 5610405Sandreas.hansson@arm.com 579524SN/Aclass ThreadContext; 582497SN/A 5910405Sandreas.hansson@arm.comnamespace ArmISA { 6010719SMarco.Balboni@ARM.com 6111334Sandreas.hansson@arm.comclass TableWalker; 6214006Stiago.muck@arm.comclass Stage2LookUp; 6314006Stiago.muck@arm.comclass Stage2MMU; 6412341Snikos.nikoleris@arm.comclass TLB; 6512341Snikos.nikoleris@arm.com 667523SN/Aclass TlbTestInterface 678851SN/A{ 688948SN/A public: 698948SN/A TlbTestInterface() {} 708851SN/A virtual ~TlbTestInterface() {} 719095SN/A 7210405Sandreas.hansson@arm.com /** 738922SN/A * Check if a TLB translation should be forced to fail. 749715SN/A * 759715SN/A * @param req Request requiring a translation. 7613808Sgabeblack@google.com * @param is_priv Access from a privileged mode (i.e., not EL0) 7713808Sgabeblack@google.com * @param mode Access type 788851SN/A * @param domain Domain type 798851SN/A */ 808948SN/A virtual Fault translationCheck(RequestPtr req, bool is_priv, 818948SN/A BaseTLB::Mode mode, 828915SN/A TlbEntry::DomainType domain) = 0; 839031SN/A 849095SN/A /** 8510405Sandreas.hansson@arm.com * Check if a page table walker access should be forced to fail. 8613808Sgabeblack@google.com * 878922SN/A * @param pa Physical address the walker is accessing 889715SN/A * @param size Walker access size 8913808Sgabeblack@google.com * @param va Virtual address that initiated the walk 9010713Sandreas.hansson@arm.com * @param is_secure Access from secure state 9110713Sandreas.hansson@arm.com * @param is_priv Access from a privileged mode (i.e., not EL0) 9210713Sandreas.hansson@arm.com * @param mode Access type 938915SN/A * @param domain Domain type 948915SN/A * @param lookup_level Page table walker level 958948SN/A */ 968851SN/A virtual Fault walkCheck(Addr pa, Addr size, Addr va, bool is_secure, 979095SN/A Addr is_priv, BaseTLB::Mode mode, 9810888Sandreas.hansson@arm.com TlbEntry::DomainType domain, 998922SN/A LookupLevel lookup_level) = 0; 1009715SN/A}; 1019715SN/A 1029716SN/Aclass TLB : public BaseTLB 1038851SN/A{ 1047523SN/A public: 1057523SN/A enum ArmFlags { 10610405Sandreas.hansson@arm.com AlignmentMask = 0x7, 1079715SN/A 10810405Sandreas.hansson@arm.com AlignByte = 0x0, 10910405Sandreas.hansson@arm.com AlignHalfWord = 0x1, 11010405Sandreas.hansson@arm.com AlignWord = 0x2, 11110405Sandreas.hansson@arm.com AlignDoubleWord = 0x3, 11210405Sandreas.hansson@arm.com AlignQuadWord = 0x4, 11310405Sandreas.hansson@arm.com AlignOctWord = 0x5, 11410405Sandreas.hansson@arm.com 11510405Sandreas.hansson@arm.com AllowUnaligned = 0x8, 1169715SN/A // Priv code operating as if it wasn't 1179715SN/A UserMode = 0x10, 1182568SN/A // Because zero otherwise looks like a valid setting and may be used 11910405Sandreas.hansson@arm.com // accidentally, this bit must be non-zero to show it was used on 1202568SN/A // purpose. 12110405Sandreas.hansson@arm.com MustBeOne = 0x40 1229278SN/A }; 1238948SN/A 1248948SN/A enum ArmTranslationType { 12510405Sandreas.hansson@arm.com NormalTran = 0, 1269088SN/A S1CTran = 0x1, 12710405Sandreas.hansson@arm.com HypMode = 0x2, 12814192Sgabeblack@google.com // Secure code operating as if it wasn't (required by some Address 12910405Sandreas.hansson@arm.com // Translate operations) 1308711SN/A S1S2NsTran = 0x4, 1318711SN/A // Address translation instructions (eg AT S1E0R_Xt) need to be handled 1322568SN/A // in special ways during translation because they could need to act 1339036SN/A // like a different EL than the current EL. The following flags are 13410405Sandreas.hansson@arm.com // for these instructions 13511133Sandreas.hansson@arm.com S1E0Tran = 0x8, 13611133Sandreas.hansson@arm.com S1E1Tran = 0x10, 13711133Sandreas.hansson@arm.com S1E2Tran = 0x20, 13811133Sandreas.hansson@arm.com S1E3Tran = 0x40, 13911133Sandreas.hansson@arm.com S12E0Tran = 0x80, 1403244SN/A S12E1Tran = 0x100 1413244SN/A }; 1428948SN/A protected: 14310405Sandreas.hansson@arm.com TlbEntry* table; // the Page Table 1443244SN/A int size; // TLB Size 1458975SN/A bool isStage2; // Indicates this TLB is part of the second stage MMU 1469032SN/A bool stage2Req; // Indicates whether a stage 2 lookup is also required 1473244SN/A uint64_t _attr; // Memory attributes for last accessed TLB entry 1489091SN/A bool directToStage2; // Indicates whether all translation requests should 1499091SN/A // be routed directly to the stage 2 TLB 15011284Sandreas.hansson@arm.com 15110656Sandreas.hansson@arm.com TableWalker *tableWalker; 15211284Sandreas.hansson@arm.com TLB *stage2Tlb; 15311284Sandreas.hansson@arm.com Stage2MMU *stage2Mmu; 1549091SN/A 15512780Snikos.nikoleris@arm.com TlbTestInterface *test; 15613856Sodanrc@yahoo.com.br 1579612SN/A // Access Stats 15810405Sandreas.hansson@arm.com mutable Stats::Scalar instHits; 1599033SN/A mutable Stats::Scalar instMisses; 1609715SN/A mutable Stats::Scalar readHits; 16111744Snikos.nikoleris@arm.com mutable Stats::Scalar readMisses; 16211744Snikos.nikoleris@arm.com mutable Stats::Scalar writeHits; 1633244SN/A mutable Stats::Scalar writeMisses; 1643244SN/A mutable Stats::Scalar inserts; 1653244SN/A mutable Stats::Scalar flushTlb; 16611744Snikos.nikoleris@arm.com mutable Stats::Scalar flushTlbMva; 16711744Snikos.nikoleris@arm.com mutable Stats::Scalar flushTlbMvaAsid; 1685197SN/A mutable Stats::Scalar flushTlbAsid; 1699712SN/A mutable Stats::Scalar flushedEntries; 1709712SN/A mutable Stats::Scalar alignFaults; 1719712SN/A mutable Stats::Scalar prefetchFaults; 1729712SN/A mutable Stats::Scalar domainFaults; 1739712SN/A mutable Stats::Scalar permsFaults; 17410719SMarco.Balboni@ARM.com 17510719SMarco.Balboni@ARM.com Stats::Formula readAccesses; 17610719SMarco.Balboni@ARM.com Stats::Formula writeAccesses; 17710719SMarco.Balboni@ARM.com Stats::Formula instAccesses; 17810719SMarco.Balboni@ARM.com Stats::Formula hits; 17910719SMarco.Balboni@ARM.com Stats::Formula misses; 18010719SMarco.Balboni@ARM.com Stats::Formula accesses; 18110719SMarco.Balboni@ARM.com 18210719SMarco.Balboni@ARM.com /** PMU probe for TLB refills */ 18310719SMarco.Balboni@ARM.com ProbePoints::PMUUPtr ppRefills; 18410719SMarco.Balboni@ARM.com 1854912SN/A int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU 18612346Snikos.nikoleris@arm.com 18712346Snikos.nikoleris@arm.com public: 18812346Snikos.nikoleris@arm.com TLB(const ArmTLBParams *p); 18912346Snikos.nikoleris@arm.com TLB(const Params *p, int _size, TableWalker *_walker); 19012346Snikos.nikoleris@arm.com 19112346Snikos.nikoleris@arm.com /** Lookup an entry in the TLB 19212345Snikos.nikoleris@arm.com * @param vpn virtual address 19312345Snikos.nikoleris@arm.com * @param asn context id/address space id to use 19412345Snikos.nikoleris@arm.com * @param vmid The virtual machine ID used for stage 2 translation 19511127Sandreas.hansson@arm.com * @param secure if the lookup is secure 19611127Sandreas.hansson@arm.com * @param hyp if the lookup is done from hyp mode 19712351Snikos.nikoleris@arm.com * @param functional if the lookup should modify state 19812351Snikos.nikoleris@arm.com * @param ignore_asn if on lookup asn should be ignored 19912351Snikos.nikoleris@arm.com * @return pointer to TLB entry if it exists 20012351Snikos.nikoleris@arm.com */ 20112351Snikos.nikoleris@arm.com TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp, 20212351Snikos.nikoleris@arm.com bool secure, bool functional, 20312351Snikos.nikoleris@arm.com bool ignore_asn, uint8_t target_el); 20412351Snikos.nikoleris@arm.com 20512351Snikos.nikoleris@arm.com virtual ~TLB(); 20612351Snikos.nikoleris@arm.com 20712351Snikos.nikoleris@arm.com void takeOverFrom(BaseTLB *otlb) override; 20812351Snikos.nikoleris@arm.com 20912351Snikos.nikoleris@arm.com /// setup all the back pointers 21012351Snikos.nikoleris@arm.com void init() override; 21112351Snikos.nikoleris@arm.com 21212351Snikos.nikoleris@arm.com void setTestInterface(SimObject *ti); 2138979SN/A 2148979SN/A TableWalker *getTableWalker() { return tableWalker; } 21510402SN/A 21610402SN/A void setMMU(Stage2MMU *m, MasterID master_id); 21710402SN/A 21811126Sandreas.hansson@arm.com int getsize() const { return size; } 21911126Sandreas.hansson@arm.com 22011126Sandreas.hansson@arm.com void insert(Addr vaddr, TlbEntry &pte); 22110719SMarco.Balboni@ARM.com 22211744Snikos.nikoleris@arm.com Fault getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, 22311744Snikos.nikoleris@arm.com Translation *translation, bool timing, bool functional, 22411744Snikos.nikoleris@arm.com bool is_secure, ArmTranslationType tranType); 22511196Sali.jafri@arm.com 22611199Sandreas.hansson@arm.com Fault getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc, 22711196Sali.jafri@arm.com Mode mode, Translation *translation, bool timing, 22811196Sali.jafri@arm.com bool functional, TlbEntry *mergeTe); 22911196Sali.jafri@arm.com 23011196Sali.jafri@arm.com Fault checkPermissions(TlbEntry *te, RequestPtr req, Mode mode); 23111196Sali.jafri@arm.com Fault checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode, 23211196Sali.jafri@arm.com ThreadContext *tc); 23311196Sali.jafri@arm.com 23411196Sali.jafri@arm.com 23511196Sali.jafri@arm.com /** Reset the entire TLB 23611196Sali.jafri@arm.com * @param secure_lookup if the operation affects the secure world 23710402SN/A */ 23810402SN/A void flushAllSecurity(bool secure_lookup, uint8_t target_el, 23910402SN/A bool ignore_el = false); 24011127Sandreas.hansson@arm.com 24111127Sandreas.hansson@arm.com /** Remove all entries in the non secure world, depending on whether they 24211127Sandreas.hansson@arm.com * were allocated in hyp mode or not 24311127Sandreas.hansson@arm.com * @param hyp if the opperation affects hyp mode 2448979SN/A */ 2458948SN/A void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false); 24611334Sandreas.hansson@arm.com 24711334Sandreas.hansson@arm.com 24810883Sali.jafri@arm.com /** Reset the entire TLB. Used for CPU switching to prevent stale 24911284Sandreas.hansson@arm.com * translations after multiple switches 25011284Sandreas.hansson@arm.com */ 25111284Sandreas.hansson@arm.com void flushAll() override 25211284Sandreas.hansson@arm.com { 25311334Sandreas.hansson@arm.com flushAllSecurity(false, 0, true); 2548915SN/A flushAllSecurity(true, 0, true); 25511334Sandreas.hansson@arm.com } 25611334Sandreas.hansson@arm.com 25711334Sandreas.hansson@arm.com /** Remove any entries that match both a va and asn 25811334Sandreas.hansson@arm.com * @param mva virtual address to flush 25911544Snikos.nikoleris@arm.com * @param asn contextid/asn to flush on match 26011544Snikos.nikoleris@arm.com * @param secure_lookup if the operation affects the secure world 26111544Snikos.nikoleris@arm.com */ 26211334Sandreas.hansson@arm.com void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup, 26311744Snikos.nikoleris@arm.com uint8_t target_el); 26411744Snikos.nikoleris@arm.com 26511334Sandreas.hansson@arm.com /** Remove any entries that match the asn 26611334Sandreas.hansson@arm.com * @param asn contextid/asn to flush on match 26711334Sandreas.hansson@arm.com * @param secure_lookup if the operation affects the secure world 26812346Snikos.nikoleris@arm.com */ 26911334Sandreas.hansson@arm.com void flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el); 27011334Sandreas.hansson@arm.com 27111334Sandreas.hansson@arm.com /** Remove all entries that match the va regardless of asn 27211334Sandreas.hansson@arm.com * @param mva address to flush from cache 27311334Sandreas.hansson@arm.com * @param secure_lookup if the operation affects the secure world 27411334Sandreas.hansson@arm.com * @param hyp if the operation affects hyp mode 27511334Sandreas.hansson@arm.com */ 27611334Sandreas.hansson@arm.com void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el); 27711334Sandreas.hansson@arm.com 27812346Snikos.nikoleris@arm.com /** 27912346Snikos.nikoleris@arm.com * Invalidate all entries in the stage 2 TLB that match the given ipa 28012346Snikos.nikoleris@arm.com * and the current VMID 28112346Snikos.nikoleris@arm.com * @param ipa the address to invalidate 28212346Snikos.nikoleris@arm.com * @param secure_lookup if the operation affects the secure world 28312346Snikos.nikoleris@arm.com * @param hyp if the operation affects hyp mode 28412346Snikos.nikoleris@arm.com */ 28511334Sandreas.hansson@arm.com void flushIpaVmid(Addr ipa, bool secure_lookup, bool hyp, uint8_t target_el); 28611334Sandreas.hansson@arm.com 28711334Sandreas.hansson@arm.com Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain); 28811334Sandreas.hansson@arm.com Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec, 28911334Sandreas.hansson@arm.com bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level); 29011334Sandreas.hansson@arm.com 29111334Sandreas.hansson@arm.com void printTlb() const; 29211334Sandreas.hansson@arm.com 29311334Sandreas.hansson@arm.com void demapPage(Addr vaddr, uint64_t asn) override 29411334Sandreas.hansson@arm.com { 29511334Sandreas.hansson@arm.com // needed for x86 only 29611334Sandreas.hansson@arm.com panic("demapPage() is not implemented.\n"); 2978948SN/A } 29812345Snikos.nikoleris@arm.com 29910402SN/A /** 30011605Snikos.nikoleris@arm.com * Do a functional lookup on the TLB (for debugging) 30110402SN/A * and don't modify any internal state 30210402SN/A * @param tc thread context to get the context id from 30310656Sandreas.hansson@arm.com * @param vaddr virtual address to translate 30410656Sandreas.hansson@arm.com * @param pa returned physical address 30511284Sandreas.hansson@arm.com * @return if the translation was successful 30610656Sandreas.hansson@arm.com */ 30710656Sandreas.hansson@arm.com bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr); 30810719SMarco.Balboni@ARM.com 30910719SMarco.Balboni@ARM.com /** 31010656Sandreas.hansson@arm.com * Do a functional lookup on the TLB (for checker cpu) that 31111744Snikos.nikoleris@arm.com * behaves like a normal lookup without modifying any page table state. 31211744Snikos.nikoleris@arm.com */ 31310656Sandreas.hansson@arm.com Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode, 31410656Sandreas.hansson@arm.com ArmTranslationType tranType = NormalTran); 31510656Sandreas.hansson@arm.com 31610719SMarco.Balboni@ARM.com /** Accessor functions for memory attributes for last accessed TLB entry 3179091SN/A */ 31810656Sandreas.hansson@arm.com void 31910656Sandreas.hansson@arm.com setAttr(uint64_t attr) 32010656Sandreas.hansson@arm.com { 32110656Sandreas.hansson@arm.com _attr = attr; 32210656Sandreas.hansson@arm.com } 32310656Sandreas.hansson@arm.com 32410656Sandreas.hansson@arm.com uint64_t 32510656Sandreas.hansson@arm.com getAttr() const 32610656Sandreas.hansson@arm.com { 3278948SN/A return _attr; 32810656Sandreas.hansson@arm.com } 32914006Stiago.muck@arm.com 33014006Stiago.muck@arm.com Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 33114006Stiago.muck@arm.com Translation *translation, bool &delay, 33210656Sandreas.hansson@arm.com bool timing, ArmTranslationType tranType, bool functional = false); 3338948SN/A Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 33410656Sandreas.hansson@arm.com Translation *translation, bool &delay, bool timing); 33510656Sandreas.hansson@arm.com Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode, 33610656Sandreas.hansson@arm.com ArmTranslationType tranType); 33710656Sandreas.hansson@arm.com Fault 3389549SN/A translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) override 33914006Stiago.muck@arm.com { 34014006Stiago.muck@arm.com return translateAtomic(req, tc, mode, NormalTran); 34114006Stiago.muck@arm.com } 34210656Sandreas.hansson@arm.com void translateTiming( 3438948SN/A RequestPtr req, ThreadContext *tc, 34410405Sandreas.hansson@arm.com Translation *translation, Mode mode, 3459715SN/A ArmTranslationType tranType); 3469091SN/A void 3478975SN/A translateTiming(RequestPtr req, ThreadContext *tc, 34810656Sandreas.hansson@arm.com Translation *translation, Mode mode) override 3499712SN/A { 35010405Sandreas.hansson@arm.com translateTiming(req, tc, translation, mode, NormalTran); 3519712SN/A } 35210656Sandreas.hansson@arm.com Fault translateComplete(RequestPtr req, ThreadContext *tc, 35311564Sdavid.guillen@arm.com Translation *translation, Mode mode, ArmTranslationType tranType, 35410656Sandreas.hansson@arm.com bool callFromS2); 35511564Sdavid.guillen@arm.com Fault finalizePhysical( 35611564Sdavid.guillen@arm.com RequestPtr req, ThreadContext *tc, Mode mode) const override; 3579712SN/A 3589712SN/A void drainResume() override; 35911334Sandreas.hansson@arm.com 36011334Sandreas.hansson@arm.com // Checkpointing 36111334Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 36211334Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 36312351Snikos.nikoleris@arm.com 36412351Snikos.nikoleris@arm.com void regStats() override; 36512351Snikos.nikoleris@arm.com 36612351Snikos.nikoleris@arm.com void regProbePoints() override; 36712351Snikos.nikoleris@arm.com 36812351Snikos.nikoleris@arm.com /** 36912351Snikos.nikoleris@arm.com * Get the table walker master port. This is used for migrating 37012351Snikos.nikoleris@arm.com * port connections during a CPU takeOverFrom() call. For 37112351Snikos.nikoleris@arm.com * architectures that do not have a table walker, NULL is 37212351Snikos.nikoleris@arm.com * returned, hence the use of a pointer rather than a 37312351Snikos.nikoleris@arm.com * reference. For ARM this method will always return a valid port 37412351Snikos.nikoleris@arm.com * pointer. 37512351Snikos.nikoleris@arm.com * 37612351Snikos.nikoleris@arm.com * @return A pointer to the walker master port 37712351Snikos.nikoleris@arm.com */ 37812351Snikos.nikoleris@arm.com BaseMasterPort* getMasterPort() override; 37912351Snikos.nikoleris@arm.com 38012351Snikos.nikoleris@arm.com // Caching misc register values here. 38112351Snikos.nikoleris@arm.com // Writing to misc registers needs to invalidate them. 38212351Snikos.nikoleris@arm.com // translateFunctional/translateSe/translateFs checks if they are 38312351Snikos.nikoleris@arm.com // invalid and call updateMiscReg if necessary. 38412351Snikos.nikoleris@arm.comprotected: 38512351Snikos.nikoleris@arm.com CPSR cpsr; 38612351Snikos.nikoleris@arm.com bool aarch64; 38712351Snikos.nikoleris@arm.com ExceptionLevel aarch64EL; 38812351Snikos.nikoleris@arm.com SCTLR sctlr; 38912351Snikos.nikoleris@arm.com SCR scr; 39012351Snikos.nikoleris@arm.com bool isPriv; 39112351Snikos.nikoleris@arm.com bool isSecure; 39212351Snikos.nikoleris@arm.com bool isHyp; 39312351Snikos.nikoleris@arm.com TTBCR ttbcr; 39412351Snikos.nikoleris@arm.com uint16_t asid; 39512351Snikos.nikoleris@arm.com uint8_t vmid; 39612351Snikos.nikoleris@arm.com PRRR prrr; 39712351Snikos.nikoleris@arm.com NMRR nmrr; 39812351Snikos.nikoleris@arm.com HCR hcr; 39912351Snikos.nikoleris@arm.com uint32_t dacr; 40012351Snikos.nikoleris@arm.com bool miscRegValid; 40112351Snikos.nikoleris@arm.com ContextID miscRegContext; 40212351Snikos.nikoleris@arm.com ArmTranslationType curTranType; 40312351Snikos.nikoleris@arm.com 40412351Snikos.nikoleris@arm.com // Cached copies of system-level properties 40512351Snikos.nikoleris@arm.com bool haveLPAE; 40612351Snikos.nikoleris@arm.com bool haveVirtualization; 40714006Stiago.muck@arm.com bool haveLargeAsid64; 40814006Stiago.muck@arm.com 40914006Stiago.muck@arm.com AddrRange m5opRange; 41012351Snikos.nikoleris@arm.com 41112351Snikos.nikoleris@arm.com void updateMiscReg(ThreadContext *tc, 41212351Snikos.nikoleris@arm.com ArmTranslationType tranType = NormalTran); 41312351Snikos.nikoleris@arm.com 41412351Snikos.nikoleris@arm.compublic: 41511334Sandreas.hansson@arm.com const Params * 41612351Snikos.nikoleris@arm.com params() const 41711334Sandreas.hansson@arm.com { 41811334Sandreas.hansson@arm.com return dynamic_cast<const Params *>(_params); 41912351Snikos.nikoleris@arm.com } 42011334Sandreas.hansson@arm.com inline void invalidateMiscReg() { miscRegValid = false; } 42111334Sandreas.hansson@arm.com 42211334Sandreas.hansson@arm.comprivate: 42312351Snikos.nikoleris@arm.com /** Remove any entries that match both a va and asn 42411334Sandreas.hansson@arm.com * @param mva virtual address to flush 42511334Sandreas.hansson@arm.com * @param asn contextid/asn to flush on match 42612351Snikos.nikoleris@arm.com * @param secure_lookup if the operation affects the secure world 42712351Snikos.nikoleris@arm.com * @param hyp if the operation affects hyp mode 42812351Snikos.nikoleris@arm.com * @param ignore_asn if the flush should ignore the asn 42912351Snikos.nikoleris@arm.com */ 43011334Sandreas.hansson@arm.com void _flushMva(Addr mva, uint64_t asn, bool secure_lookup, 43112351Snikos.nikoleris@arm.com bool hyp, bool ignore_asn, uint8_t target_el); 43211334Sandreas.hansson@arm.com 43312351Snikos.nikoleris@arm.com bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el); 43411334Sandreas.hansson@arm.com 43511334Sandreas.hansson@arm.com public: /* Testing */ 4369091SN/A Fault testTranslation(RequestPtr req, Mode mode, 4378975SN/A TlbEntry::DomainType domain); 4388975SN/A Fault testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode, 4398975SN/A TlbEntry::DomainType domain, 44010405Sandreas.hansson@arm.com LookupLevel lookup_level); 4418975SN/A}; 4428975SN/A 4439032SN/A} // namespace ArmISA 4448975SN/A 44510656Sandreas.hansson@arm.com#endif // __ARCH_ARM_TLB_HH__ 44610656Sandreas.hansson@arm.com