tlb.hh revision 12005
16019Shines@cs.fsu.edu/*
211577SDylan.Johnson@ARM.com * Copyright (c) 2010-2013, 2016 ARM Limited
37399SAli.Saidi@ARM.com * All rights reserved
47399SAli.Saidi@ARM.com *
57399SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall
67399SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual
77399SAli.Saidi@ARM.com * property including but not limited to intellectual property relating
87399SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software
97399SAli.Saidi@ARM.com * licensed hereunder.  You may use the software subject to the license
107399SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated
117399SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software,
127399SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form.
137399SAli.Saidi@ARM.com *
146019Shines@cs.fsu.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan
156019Shines@cs.fsu.edu * All rights reserved.
166019Shines@cs.fsu.edu *
176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without
186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are
196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright
206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer;
216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright
226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the
236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution;
246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its
256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from
266019Shines@cs.fsu.edu * this software without specific prior written permission.
276019Shines@cs.fsu.edu *
286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
396019Shines@cs.fsu.edu *
407399SAli.Saidi@ARM.com * Authors: Ali Saidi
416019Shines@cs.fsu.edu */
426019Shines@cs.fsu.edu
436019Shines@cs.fsu.edu#ifndef __ARCH_ARM_TLB_HH__
446019Shines@cs.fsu.edu#define __ARCH_ARM_TLB_HH__
456019Shines@cs.fsu.edu
466019Shines@cs.fsu.edu
476019Shines@cs.fsu.edu#include "arch/arm/isa_traits.hh"
488229Snate@binkert.org#include "arch/arm/pagetable.hh"
496019Shines@cs.fsu.edu#include "arch/arm/utility.hh"
506019Shines@cs.fsu.edu#include "arch/arm/vtophys.hh"
5110687SAndreas.Sandberg@ARM.com#include "arch/generic/tlb.hh"
526019Shines@cs.fsu.edu#include "base/statistics.hh"
536019Shines@cs.fsu.edu#include "mem/request.hh"
546116Snate@binkert.org#include "params/ArmTLB.hh"
5510463SAndreas.Sandberg@ARM.com#include "sim/probe/pmu.hh"
566019Shines@cs.fsu.edu
576019Shines@cs.fsu.educlass ThreadContext;
586019Shines@cs.fsu.edu
596019Shines@cs.fsu.edunamespace ArmISA {
606019Shines@cs.fsu.edu
617404SAli.Saidi@ARM.comclass TableWalker;
6210037SARM gem5 Developersclass Stage2LookUp;
6310037SARM gem5 Developersclass Stage2MMU;
6411395Sandreas.sandberg@arm.comclass TLB;
6511395Sandreas.sandberg@arm.com
6611395Sandreas.sandberg@arm.comclass TlbTestInterface
6711395Sandreas.sandberg@arm.com{
6811395Sandreas.sandberg@arm.com  public:
6911395Sandreas.sandberg@arm.com    TlbTestInterface() {}
7011395Sandreas.sandberg@arm.com    virtual ~TlbTestInterface() {}
7111395Sandreas.sandberg@arm.com
7211395Sandreas.sandberg@arm.com    /**
7311395Sandreas.sandberg@arm.com     * Check if a TLB translation should be forced to fail.
7411395Sandreas.sandberg@arm.com     *
7511395Sandreas.sandberg@arm.com     * @param req Request requiring a translation.
7611395Sandreas.sandberg@arm.com     * @param is_priv Access from a privileged mode (i.e., not EL0)
7711395Sandreas.sandberg@arm.com     * @param mode Access type
7811395Sandreas.sandberg@arm.com     * @param domain Domain type
7911395Sandreas.sandberg@arm.com     */
8011395Sandreas.sandberg@arm.com    virtual Fault translationCheck(RequestPtr req, bool is_priv,
8111395Sandreas.sandberg@arm.com                                   BaseTLB::Mode mode,
8211395Sandreas.sandberg@arm.com                                   TlbEntry::DomainType domain) = 0;
8311395Sandreas.sandberg@arm.com
8411395Sandreas.sandberg@arm.com    /**
8511395Sandreas.sandberg@arm.com     * Check if a page table walker access should be forced to fail.
8611395Sandreas.sandberg@arm.com     *
8711395Sandreas.sandberg@arm.com     * @param pa Physical address the walker is accessing
8811395Sandreas.sandberg@arm.com     * @param size Walker access size
8911395Sandreas.sandberg@arm.com     * @param va Virtual address that initiated the walk
9011395Sandreas.sandberg@arm.com     * @param is_secure Access from secure state
9111395Sandreas.sandberg@arm.com     * @param is_priv Access from a privileged mode (i.e., not EL0)
9211395Sandreas.sandberg@arm.com     * @param mode Access type
9311395Sandreas.sandberg@arm.com     * @param domain Domain type
9411395Sandreas.sandberg@arm.com     * @param lookup_level Page table walker level
9511395Sandreas.sandberg@arm.com     */
9611395Sandreas.sandberg@arm.com    virtual Fault walkCheck(Addr pa, Addr size, Addr va, bool is_secure,
9711395Sandreas.sandberg@arm.com                            Addr is_priv, BaseTLB::Mode mode,
9811395Sandreas.sandberg@arm.com                            TlbEntry::DomainType domain,
9911395Sandreas.sandberg@arm.com                            LookupLevel lookup_level) = 0;
10011395Sandreas.sandberg@arm.com};
1017404SAli.Saidi@ARM.com
1026019Shines@cs.fsu.educlass TLB : public BaseTLB
1036019Shines@cs.fsu.edu{
1047294Sgblack@eecs.umich.edu  public:
1057294Sgblack@eecs.umich.edu    enum ArmFlags {
10610037SARM gem5 Developers        AlignmentMask = 0x7,
1077294Sgblack@eecs.umich.edu
1087294Sgblack@eecs.umich.edu        AlignByte = 0x0,
1097294Sgblack@eecs.umich.edu        AlignHalfWord = 0x1,
11010037SARM gem5 Developers        AlignWord = 0x2,
11110037SARM gem5 Developers        AlignDoubleWord = 0x3,
11210037SARM gem5 Developers        AlignQuadWord = 0x4,
11310037SARM gem5 Developers        AlignOctWord = 0x5,
1147294Sgblack@eecs.umich.edu
11510037SARM gem5 Developers        AllowUnaligned = 0x8,
1167404SAli.Saidi@ARM.com        // Priv code operating as if it wasn't
11710037SARM gem5 Developers        UserMode = 0x10,
1187294Sgblack@eecs.umich.edu        // Because zero otherwise looks like a valid setting and may be used
1197294Sgblack@eecs.umich.edu        // accidentally, this bit must be non-zero to show it was used on
1207294Sgblack@eecs.umich.edu        // purpose.
12110037SARM gem5 Developers        MustBeOne = 0x40
12210037SARM gem5 Developers    };
12310037SARM gem5 Developers
12410037SARM gem5 Developers    enum ArmTranslationType {
12510037SARM gem5 Developers        NormalTran = 0,
12610037SARM gem5 Developers        S1CTran = 0x1,
12710037SARM gem5 Developers        HypMode = 0x2,
12810037SARM gem5 Developers        // Secure code operating as if it wasn't (required by some Address
12910037SARM gem5 Developers        // Translate operations)
13011577SDylan.Johnson@ARM.com        S1S2NsTran = 0x4,
13111577SDylan.Johnson@ARM.com        // Address translation instructions (eg AT S1E0R_Xt) need to be handled
13211577SDylan.Johnson@ARM.com        // in special ways during translation because they could need to act
13311577SDylan.Johnson@ARM.com        // like a different EL than the current EL. The following flags are
13411577SDylan.Johnson@ARM.com        // for these instructions
13511577SDylan.Johnson@ARM.com        S1E0Tran = 0x8,
13611577SDylan.Johnson@ARM.com        S1E1Tran = 0x10,
13711577SDylan.Johnson@ARM.com        S1E2Tran = 0x20,
13811577SDylan.Johnson@ARM.com        S1E3Tran = 0x40,
13911577SDylan.Johnson@ARM.com        S12E0Tran = 0x80,
14011577SDylan.Johnson@ARM.com        S12E1Tran = 0x100
1417294Sgblack@eecs.umich.edu    };
1426019Shines@cs.fsu.edu  protected:
14310037SARM gem5 Developers    TlbEntry* table;     // the Page Table
14410037SARM gem5 Developers    int size;            // TLB Size
14510037SARM gem5 Developers    bool isStage2;       // Indicates this TLB is part of the second stage MMU
14610037SARM gem5 Developers    bool stage2Req;      // Indicates whether a stage 2 lookup is also required
14710037SARM gem5 Developers    uint64_t _attr;      // Memory attributes for last accessed TLB entry
14810037SARM gem5 Developers    bool directToStage2; // Indicates whether all translation requests should
14910037SARM gem5 Developers                         // be routed directly to the stage 2 TLB
1507436Sdam.sunwoo@arm.com
1517404SAli.Saidi@ARM.com    TableWalker *tableWalker;
15210037SARM gem5 Developers    TLB *stage2Tlb;
15310037SARM gem5 Developers    Stage2MMU *stage2Mmu;
1546019Shines@cs.fsu.edu
15511395Sandreas.sandberg@arm.com    TlbTestInterface *test;
15611395Sandreas.sandberg@arm.com
1577399SAli.Saidi@ARM.com    // Access Stats
1587734SAli.Saidi@ARM.com    mutable Stats::Scalar instHits;
1597734SAli.Saidi@ARM.com    mutable Stats::Scalar instMisses;
1607734SAli.Saidi@ARM.com    mutable Stats::Scalar readHits;
1617734SAli.Saidi@ARM.com    mutable Stats::Scalar readMisses;
1627734SAli.Saidi@ARM.com    mutable Stats::Scalar writeHits;
1637734SAli.Saidi@ARM.com    mutable Stats::Scalar writeMisses;
1647734SAli.Saidi@ARM.com    mutable Stats::Scalar inserts;
1657734SAli.Saidi@ARM.com    mutable Stats::Scalar flushTlb;
1667734SAli.Saidi@ARM.com    mutable Stats::Scalar flushTlbMva;
1677734SAli.Saidi@ARM.com    mutable Stats::Scalar flushTlbMvaAsid;
1687734SAli.Saidi@ARM.com    mutable Stats::Scalar flushTlbAsid;
1697734SAli.Saidi@ARM.com    mutable Stats::Scalar flushedEntries;
1707734SAli.Saidi@ARM.com    mutable Stats::Scalar alignFaults;
1717734SAli.Saidi@ARM.com    mutable Stats::Scalar prefetchFaults;
1727734SAli.Saidi@ARM.com    mutable Stats::Scalar domainFaults;
1737734SAli.Saidi@ARM.com    mutable Stats::Scalar permsFaults;
1747734SAli.Saidi@ARM.com
1757734SAli.Saidi@ARM.com    Stats::Formula readAccesses;
1767734SAli.Saidi@ARM.com    Stats::Formula writeAccesses;
1777734SAli.Saidi@ARM.com    Stats::Formula instAccesses;
1786019Shines@cs.fsu.edu    Stats::Formula hits;
1796019Shines@cs.fsu.edu    Stats::Formula misses;
1806019Shines@cs.fsu.edu    Stats::Formula accesses;
1816019Shines@cs.fsu.edu
18210463SAndreas.Sandberg@ARM.com    /** PMU probe for TLB refills */
18310463SAndreas.Sandberg@ARM.com    ProbePoints::PMUUPtr ppRefills;
18410463SAndreas.Sandberg@ARM.com
1857697SAli.Saidi@ARM.com    int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
1867404SAli.Saidi@ARM.com
1876019Shines@cs.fsu.edu  public:
18810037SARM gem5 Developers    TLB(const ArmTLBParams *p);
18910037SARM gem5 Developers    TLB(const Params *p, int _size, TableWalker *_walker);
1906019Shines@cs.fsu.edu
1919535Smrinmoy.ghosh@arm.com    /** Lookup an entry in the TLB
1929535Smrinmoy.ghosh@arm.com     * @param vpn virtual address
1939535Smrinmoy.ghosh@arm.com     * @param asn context id/address space id to use
19410037SARM gem5 Developers     * @param vmid The virtual machine ID used for stage 2 translation
19510037SARM gem5 Developers     * @param secure if the lookup is secure
19610037SARM gem5 Developers     * @param hyp if the lookup is done from hyp mode
1979535Smrinmoy.ghosh@arm.com     * @param functional if the lookup should modify state
19810037SARM gem5 Developers     * @param ignore_asn if on lookup asn should be ignored
19910037SARM gem5 Developers     * @return pointer to TLB entry if it exists
2009535Smrinmoy.ghosh@arm.com     */
20110037SARM gem5 Developers    TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp,
20210037SARM gem5 Developers                     bool secure, bool functional,
20310037SARM gem5 Developers                     bool ignore_asn, uint8_t target_el);
2049535Smrinmoy.ghosh@arm.com
2056019Shines@cs.fsu.edu    virtual ~TLB();
20610037SARM gem5 Developers
20711169Sandreas.hansson@arm.com    void takeOverFrom(BaseTLB *otlb) override;
20810194SGeoffrey.Blake@arm.com
20910037SARM gem5 Developers    /// setup all the back pointers
21011169Sandreas.hansson@arm.com    void init() override;
21110037SARM gem5 Developers
21211395Sandreas.sandberg@arm.com    void setTestInterface(SimObject *ti);
21311395Sandreas.sandberg@arm.com
21410717Sandreas.hansson@arm.com    TableWalker *getTableWalker() { return tableWalker; }
21510717Sandreas.hansson@arm.com
21610717Sandreas.hansson@arm.com    void setMMU(Stage2MMU *m, MasterID master_id);
21710037SARM gem5 Developers
2186019Shines@cs.fsu.edu    int getsize() const { return size; }
2196019Shines@cs.fsu.edu
2207404SAli.Saidi@ARM.com    void insert(Addr vaddr, TlbEntry &pte);
2217404SAli.Saidi@ARM.com
22210037SARM gem5 Developers    Fault getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode,
22310037SARM gem5 Developers                Translation *translation, bool timing, bool functional,
22410037SARM gem5 Developers                bool is_secure, ArmTranslationType tranType);
22510037SARM gem5 Developers
22610037SARM gem5 Developers    Fault getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc,
22710037SARM gem5 Developers                      Mode mode, Translation *translation, bool timing,
22810037SARM gem5 Developers                      bool functional, TlbEntry *mergeTe);
22910037SARM gem5 Developers
23010037SARM gem5 Developers    Fault checkPermissions(TlbEntry *te, RequestPtr req, Mode mode);
23110037SARM gem5 Developers    Fault checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode,
23210037SARM gem5 Developers                             ThreadContext *tc);
23310037SARM gem5 Developers
23410037SARM gem5 Developers
23510037SARM gem5 Developers    /** Reset the entire TLB
23610037SARM gem5 Developers     * @param secure_lookup if the operation affects the secure world
23710037SARM gem5 Developers     */
23810037SARM gem5 Developers    void flushAllSecurity(bool secure_lookup, uint8_t target_el,
23910037SARM gem5 Developers                          bool ignore_el = false);
24010037SARM gem5 Developers
24110037SARM gem5 Developers    /** Remove all entries in the non secure world, depending on whether they
24210037SARM gem5 Developers     *  were allocated in hyp mode or not
24310037SARM gem5 Developers     * @param hyp if the opperation affects hyp mode
24410037SARM gem5 Developers     */
24510037SARM gem5 Developers    void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false);
24610037SARM gem5 Developers
24710037SARM gem5 Developers
24810037SARM gem5 Developers    /** Reset the entire TLB. Used for CPU switching to prevent stale
24910037SARM gem5 Developers     * translations after multiple switches
25010037SARM gem5 Developers     */
25111169Sandreas.hansson@arm.com    void flushAll() override
25210037SARM gem5 Developers    {
25310037SARM gem5 Developers        flushAllSecurity(false, 0, true);
25410037SARM gem5 Developers        flushAllSecurity(true, 0, true);
25510037SARM gem5 Developers    }
2567404SAli.Saidi@ARM.com
2577404SAli.Saidi@ARM.com    /** Remove any entries that match both a va and asn
2587404SAli.Saidi@ARM.com     * @param mva virtual address to flush
2597404SAli.Saidi@ARM.com     * @param asn contextid/asn to flush on match
26010037SARM gem5 Developers     * @param secure_lookup if the operation affects the secure world
2617404SAli.Saidi@ARM.com     */
26210037SARM gem5 Developers    void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup,
26310037SARM gem5 Developers                      uint8_t target_el);
2647404SAli.Saidi@ARM.com
2657404SAli.Saidi@ARM.com    /** Remove any entries that match the asn
2667404SAli.Saidi@ARM.com     * @param asn contextid/asn to flush on match
26710037SARM gem5 Developers     * @param secure_lookup if the operation affects the secure world
2687404SAli.Saidi@ARM.com     */
26910037SARM gem5 Developers    void flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el);
2707404SAli.Saidi@ARM.com
2717404SAli.Saidi@ARM.com    /** Remove all entries that match the va regardless of asn
2727404SAli.Saidi@ARM.com     * @param mva address to flush from cache
27310037SARM gem5 Developers     * @param secure_lookup if the operation affects the secure world
27410037SARM gem5 Developers     * @param hyp if the operation affects hyp mode
2757404SAli.Saidi@ARM.com     */
27610037SARM gem5 Developers    void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el);
2777404SAli.Saidi@ARM.com
27811584SDylan.Johnson@ARM.com    /**
27911584SDylan.Johnson@ARM.com     * Invalidate all entries in the stage 2 TLB that match the given ipa
28011584SDylan.Johnson@ARM.com     * and the current VMID
28111584SDylan.Johnson@ARM.com     * @param ipa the address to invalidate
28211584SDylan.Johnson@ARM.com     * @param secure_lookup if the operation affects the secure world
28311584SDylan.Johnson@ARM.com     * @param hyp if the operation affects hyp mode
28411584SDylan.Johnson@ARM.com     */
28511584SDylan.Johnson@ARM.com    void flushIpaVmid(Addr ipa, bool secure_lookup, bool hyp, uint8_t target_el);
28611584SDylan.Johnson@ARM.com
28711584SDylan.Johnson@ARM.com    Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain);
28811584SDylan.Johnson@ARM.com    Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec,
28911584SDylan.Johnson@ARM.com            bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level);
29011584SDylan.Johnson@ARM.com
29110037SARM gem5 Developers    void printTlb() const;
2927404SAli.Saidi@ARM.com
29311169Sandreas.hansson@arm.com    void demapPage(Addr vaddr, uint64_t asn) override
2946019Shines@cs.fsu.edu    {
29510037SARM gem5 Developers        // needed for x86 only
29610037SARM gem5 Developers        panic("demapPage() is not implemented.\n");
2976019Shines@cs.fsu.edu    }
2986019Shines@cs.fsu.edu
2997694SAli.Saidi@ARM.com    /**
3007694SAli.Saidi@ARM.com     * Do a functional lookup on the TLB (for debugging)
3017694SAli.Saidi@ARM.com     * and don't modify any internal state
3027694SAli.Saidi@ARM.com     * @param tc thread context to get the context id from
3037694SAli.Saidi@ARM.com     * @param vaddr virtual address to translate
3047694SAli.Saidi@ARM.com     * @param pa returned physical address
3057694SAli.Saidi@ARM.com     * @return if the translation was successful
3067694SAli.Saidi@ARM.com     */
3077694SAli.Saidi@ARM.com    bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
3087694SAli.Saidi@ARM.com
3098733Sgeoffrey.blake@arm.com    /**
3108733Sgeoffrey.blake@arm.com     * Do a functional lookup on the TLB (for checker cpu) that
3118733Sgeoffrey.blake@arm.com     * behaves like a normal lookup without modifying any page table state.
3128733Sgeoffrey.blake@arm.com     */
31310037SARM gem5 Developers    Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode,
31410037SARM gem5 Developers            ArmTranslationType tranType = NormalTran);
3158733Sgeoffrey.blake@arm.com
3167436Sdam.sunwoo@arm.com    /** Accessor functions for memory attributes for last accessed TLB entry
3177436Sdam.sunwoo@arm.com     */
3187436Sdam.sunwoo@arm.com    void
31910037SARM gem5 Developers    setAttr(uint64_t attr)
3207436Sdam.sunwoo@arm.com    {
3217436Sdam.sunwoo@arm.com        _attr = attr;
3227436Sdam.sunwoo@arm.com    }
32310037SARM gem5 Developers
32410037SARM gem5 Developers    uint64_t
3257436Sdam.sunwoo@arm.com    getAttr() const
3267436Sdam.sunwoo@arm.com    {
3277436Sdam.sunwoo@arm.com        return _attr;
3287436Sdam.sunwoo@arm.com    }
3297436Sdam.sunwoo@arm.com
3307404SAli.Saidi@ARM.com    Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
3318733Sgeoffrey.blake@arm.com            Translation *translation, bool &delay,
33210037SARM gem5 Developers            bool timing, ArmTranslationType tranType, bool functional = false);
3337404SAli.Saidi@ARM.com    Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
3347404SAli.Saidi@ARM.com            Translation *translation, bool &delay, bool timing);
33510037SARM gem5 Developers    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode,
33610037SARM gem5 Developers            ArmTranslationType tranType = NormalTran);
3377404SAli.Saidi@ARM.com    Fault translateTiming(RequestPtr req, ThreadContext *tc,
33810037SARM gem5 Developers            Translation *translation, Mode mode,
33910037SARM gem5 Developers            ArmTranslationType tranType = NormalTran);
34010037SARM gem5 Developers    Fault translateComplete(RequestPtr req, ThreadContext *tc,
34110037SARM gem5 Developers            Translation *translation, Mode mode, ArmTranslationType tranType,
34210037SARM gem5 Developers            bool callFromS2);
3439738Sandreas@sandberg.pp.se    Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
3446116Snate@binkert.org
34511168Sandreas.hansson@arm.com    void drainResume() override;
3469439SAndreas.Sandberg@ARM.com
3476019Shines@cs.fsu.edu    // Checkpointing
34811168Sandreas.hansson@arm.com    void serialize(CheckpointOut &cp) const override;
34911168Sandreas.hansson@arm.com    void unserialize(CheckpointIn &cp) override;
3506019Shines@cs.fsu.edu
35111169Sandreas.hansson@arm.com    void regStats() override;
3527749SAli.Saidi@ARM.com
35311168Sandreas.hansson@arm.com    void regProbePoints() override;
35410463SAndreas.Sandberg@ARM.com
3558922Swilliam.wang@arm.com    /**
3568922Swilliam.wang@arm.com     * Get the table walker master port. This is used for migrating
3578922Swilliam.wang@arm.com     * port connections during a CPU takeOverFrom() call. For
3588922Swilliam.wang@arm.com     * architectures that do not have a table walker, NULL is
3598922Swilliam.wang@arm.com     * returned, hence the use of a pointer rather than a
3608922Swilliam.wang@arm.com     * reference. For ARM this method will always return a valid port
3618922Swilliam.wang@arm.com     * pointer.
3628922Swilliam.wang@arm.com     *
3638922Swilliam.wang@arm.com     * @return A pointer to the walker master port
3648922Swilliam.wang@arm.com     */
36511169Sandreas.hansson@arm.com    BaseMasterPort* getMasterPort() override;
3667781SAli.Saidi@ARM.com
3677749SAli.Saidi@ARM.com    // Caching misc register values here.
3687749SAli.Saidi@ARM.com    // Writing to misc registers needs to invalidate them.
3697749SAli.Saidi@ARM.com    // translateFunctional/translateSe/translateFs checks if they are
3707749SAli.Saidi@ARM.com    // invalid and call updateMiscReg if necessary.
3717749SAli.Saidi@ARM.comprotected:
37210854SNathanael.Premillieu@arm.com    CPSR cpsr;
37310037SARM gem5 Developers    bool aarch64;
37410037SARM gem5 Developers    ExceptionLevel aarch64EL;
3757749SAli.Saidi@ARM.com    SCTLR sctlr;
37610037SARM gem5 Developers    SCR scr;
3777749SAli.Saidi@ARM.com    bool isPriv;
37810037SARM gem5 Developers    bool isSecure;
37910037SARM gem5 Developers    bool isHyp;
38010037SARM gem5 Developers    TTBCR ttbcr;
38110037SARM gem5 Developers    uint16_t asid;
38210037SARM gem5 Developers    uint8_t vmid;
3837749SAli.Saidi@ARM.com    PRRR prrr;
3847749SAli.Saidi@ARM.com    NMRR nmrr;
38510037SARM gem5 Developers    HCR hcr;
3867749SAli.Saidi@ARM.com    uint32_t dacr;
3877749SAli.Saidi@ARM.com    bool miscRegValid;
38811152Smitch.hayenga@arm.com    ContextID miscRegContext;
38910037SARM gem5 Developers    ArmTranslationType curTranType;
39010037SARM gem5 Developers
39110037SARM gem5 Developers    // Cached copies of system-level properties
39210037SARM gem5 Developers    bool haveLPAE;
39310037SARM gem5 Developers    bool haveVirtualization;
39410037SARM gem5 Developers    bool haveLargeAsid64;
39510037SARM gem5 Developers
39612005Sandreas.sandberg@arm.com    AddrRange m5opRange;
39712005Sandreas.sandberg@arm.com
39810037SARM gem5 Developers    void updateMiscReg(ThreadContext *tc,
39910037SARM gem5 Developers                       ArmTranslationType tranType = NormalTran);
40010037SARM gem5 Developers
4017749SAli.Saidi@ARM.compublic:
4028299Schander.sudanthi@arm.com    const Params *
4038299Schander.sudanthi@arm.com    params() const
4048299Schander.sudanthi@arm.com    {
4058299Schander.sudanthi@arm.com        return dynamic_cast<const Params *>(_params);
4068299Schander.sudanthi@arm.com    }
4077749SAli.Saidi@ARM.com    inline void invalidateMiscReg() { miscRegValid = false; }
40810037SARM gem5 Developers
40910037SARM gem5 Developersprivate:
41010037SARM gem5 Developers    /** Remove any entries that match both a va and asn
41110037SARM gem5 Developers     * @param mva virtual address to flush
41210037SARM gem5 Developers     * @param asn contextid/asn to flush on match
41310037SARM gem5 Developers     * @param secure_lookup if the operation affects the secure world
41410037SARM gem5 Developers     * @param hyp if the operation affects hyp mode
41510037SARM gem5 Developers     * @param ignore_asn if the flush should ignore the asn
41610037SARM gem5 Developers     */
41710037SARM gem5 Developers    void _flushMva(Addr mva, uint64_t asn, bool secure_lookup,
41810037SARM gem5 Developers                   bool hyp, bool ignore_asn, uint8_t target_el);
41910037SARM gem5 Developers
42010037SARM gem5 Developers    bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el);
42111395Sandreas.sandberg@arm.com
42211395Sandreas.sandberg@arm.com  public: /* Testing */
42311395Sandreas.sandberg@arm.com    Fault testTranslation(RequestPtr req, Mode mode,
42411395Sandreas.sandberg@arm.com                          TlbEntry::DomainType domain);
42511395Sandreas.sandberg@arm.com    Fault testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode,
42611395Sandreas.sandberg@arm.com                   TlbEntry::DomainType domain,
42711395Sandreas.sandberg@arm.com                   LookupLevel lookup_level);
4286019Shines@cs.fsu.edu};
4296019Shines@cs.fsu.edu
4307811Ssteve.reinhardt@amd.com} // namespace ArmISA
4316019Shines@cs.fsu.edu
4326019Shines@cs.fsu.edu#endif // __ARCH_ARM_TLB_HH__
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