tlb.hh revision 10717 
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_TLB_HH__
44#define __ARCH_ARM_TLB_HH__
45
46
47#include "arch/arm/isa_traits.hh"
48#include "arch/arm/pagetable.hh"
49#include "arch/arm/utility.hh"
50#include "arch/arm/vtophys.hh"
51#include "arch/generic/tlb.hh"
52#include "base/statistics.hh"
53#include "dev/dma_device.hh"
54#include "mem/request.hh"
55#include "params/ArmTLB.hh"
56#include "sim/probe/pmu.hh"
57
58class ThreadContext;
59
60namespace ArmISA {
61
62class TableWalker;
63class Stage2LookUp;
64class Stage2MMU;
65
66class TLB : public BaseTLB
67{
68  public:
69    enum ArmFlags {
70        AlignmentMask = 0x7,
71
72        AlignByte = 0x0,
73        AlignHalfWord = 0x1,
74        AlignWord = 0x2,
75        AlignDoubleWord = 0x3,
76        AlignQuadWord = 0x4,
77        AlignOctWord = 0x5,
78
79        AllowUnaligned = 0x8,
80        // Priv code operating as if it wasn't
81        UserMode = 0x10,
82        // Because zero otherwise looks like a valid setting and may be used
83        // accidentally, this bit must be non-zero to show it was used on
84        // purpose.
85        MustBeOne = 0x40
86    };
87
88    enum ArmTranslationType {
89        NormalTran = 0,
90        S1CTran = 0x1,
91        HypMode = 0x2,
92        // Secure code operating as if it wasn't (required by some Address
93        // Translate operations)
94        S1S2NsTran = 0x4
95    };
96  protected:
97    TlbEntry* table;     // the Page Table
98    int size;            // TLB Size
99    bool isStage2;       // Indicates this TLB is part of the second stage MMU
100    bool stage2Req;      // Indicates whether a stage 2 lookup is also required
101    uint64_t _attr;      // Memory attributes for last accessed TLB entry
102    bool directToStage2; // Indicates whether all translation requests should
103                         // be routed directly to the stage 2 TLB
104
105    TableWalker *tableWalker;
106    TLB *stage2Tlb;
107    Stage2MMU *stage2Mmu;
108
109    // Access Stats
110    mutable Stats::Scalar instHits;
111    mutable Stats::Scalar instMisses;
112    mutable Stats::Scalar readHits;
113    mutable Stats::Scalar readMisses;
114    mutable Stats::Scalar writeHits;
115    mutable Stats::Scalar writeMisses;
116    mutable Stats::Scalar inserts;
117    mutable Stats::Scalar flushTlb;
118    mutable Stats::Scalar flushTlbMva;
119    mutable Stats::Scalar flushTlbMvaAsid;
120    mutable Stats::Scalar flushTlbAsid;
121    mutable Stats::Scalar flushedEntries;
122    mutable Stats::Scalar alignFaults;
123    mutable Stats::Scalar prefetchFaults;
124    mutable Stats::Scalar domainFaults;
125    mutable Stats::Scalar permsFaults;
126
127    Stats::Formula readAccesses;
128    Stats::Formula writeAccesses;
129    Stats::Formula instAccesses;
130    Stats::Formula hits;
131    Stats::Formula misses;
132    Stats::Formula accesses;
133
134    /** PMU probe for TLB refills */
135    ProbePoints::PMUUPtr ppRefills;
136
137    int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
138
139    bool bootUncacheability;
140
141  public:
142    TLB(const ArmTLBParams *p);
143    TLB(const Params *p, int _size, TableWalker *_walker);
144
145    /** Lookup an entry in the TLB
146     * @param vpn virtual address
147     * @param asn context id/address space id to use
148     * @param vmid The virtual machine ID used for stage 2 translation
149     * @param secure if the lookup is secure
150     * @param hyp if the lookup is done from hyp mode
151     * @param functional if the lookup should modify state
152     * @param ignore_asn if on lookup asn should be ignored
153     * @return pointer to TLB entry if it exists
154     */
155    TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp,
156                     bool secure, bool functional,
157                     bool ignore_asn, uint8_t target_el);
158
159    virtual ~TLB();
160
161    void takeOverFrom(BaseTLB *otlb);
162
163    /// setup all the back pointers
164    virtual void init();
165
166    TableWalker *getTableWalker() { return tableWalker; }
167
168    void setMMU(Stage2MMU *m, MasterID master_id);
169
170    int getsize() const { return size; }
171
172    void insert(Addr vaddr, TlbEntry &pte);
173
174    Fault getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode,
175                Translation *translation, bool timing, bool functional,
176                bool is_secure, ArmTranslationType tranType);
177
178    Fault getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc,
179                      Mode mode, Translation *translation, bool timing,
180                      bool functional, TlbEntry *mergeTe);
181
182    Fault checkPermissions(TlbEntry *te, RequestPtr req, Mode mode);
183    Fault checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode,
184                             ThreadContext *tc);
185
186
187    /** Reset the entire TLB
188     * @param secure_lookup if the operation affects the secure world
189     */
190    void flushAllSecurity(bool secure_lookup, uint8_t target_el,
191                          bool ignore_el = false);
192
193    /** Remove all entries in the non secure world, depending on whether they
194     *  were allocated in hyp mode or not
195     * @param hyp if the opperation affects hyp mode
196     */
197    void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false);
198
199
200    /** Reset the entire TLB. Used for CPU switching to prevent stale
201     * translations after multiple switches
202     */
203    void flushAll()
204    {
205        flushAllSecurity(false, 0, true);
206        flushAllSecurity(true, 0, true);
207    }
208
209    /** Remove any entries that match both a va and asn
210     * @param mva virtual address to flush
211     * @param asn contextid/asn to flush on match
212     * @param secure_lookup if the operation affects the secure world
213     */
214    void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup,
215                      uint8_t target_el);
216
217    /** Remove any entries that match the asn
218     * @param asn contextid/asn to flush on match
219     * @param secure_lookup if the operation affects the secure world
220     */
221    void flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el);
222
223    /** Remove all entries that match the va regardless of asn
224     * @param mva address to flush from cache
225     * @param secure_lookup if the operation affects the secure world
226     * @param hyp if the operation affects hyp mode
227     */
228    void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el);
229
230    Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain);
231    Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec,
232            bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level);
233
234    void printTlb() const;
235
236    void allCpusCaching() { bootUncacheability = true; }
237    void demapPage(Addr vaddr, uint64_t asn)
238    {
239        // needed for x86 only
240        panic("demapPage() is not implemented.\n");
241    }
242
243    static bool validVirtualAddress(Addr vaddr);
244
245    /**
246     * Do a functional lookup on the TLB (for debugging)
247     * and don't modify any internal state
248     * @param tc thread context to get the context id from
249     * @param vaddr virtual address to translate
250     * @param pa returned physical address
251     * @return if the translation was successful
252     */
253    bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
254
255    /**
256     * Do a functional lookup on the TLB (for checker cpu) that
257     * behaves like a normal lookup without modifying any page table state.
258     */
259    Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode,
260            ArmTranslationType tranType = NormalTran);
261
262    /** Accessor functions for memory attributes for last accessed TLB entry
263     */
264    void
265    setAttr(uint64_t attr)
266    {
267        _attr = attr;
268    }
269
270    uint64_t
271    getAttr() const
272    {
273        return _attr;
274    }
275
276    Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
277            Translation *translation, bool &delay,
278            bool timing, ArmTranslationType tranType, bool functional = false);
279    Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
280            Translation *translation, bool &delay, bool timing);
281    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode,
282            ArmTranslationType tranType = NormalTran);
283    Fault translateTiming(RequestPtr req, ThreadContext *tc,
284            Translation *translation, Mode mode,
285            ArmTranslationType tranType = NormalTran);
286    Fault translateComplete(RequestPtr req, ThreadContext *tc,
287            Translation *translation, Mode mode, ArmTranslationType tranType,
288            bool callFromS2);
289    Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
290
291    void drainResume();
292
293    // Checkpointing
294    void serialize(std::ostream &os);
295    void unserialize(Checkpoint *cp, const std::string &section);
296
297    void regStats();
298
299    void regProbePoints() M5_ATTR_OVERRIDE;
300
301    /**
302     * Get the table walker master port. This is used for migrating
303     * port connections during a CPU takeOverFrom() call. For
304     * architectures that do not have a table walker, NULL is
305     * returned, hence the use of a pointer rather than a
306     * reference. For ARM this method will always return a valid port
307     * pointer.
308     *
309     * @return A pointer to the walker master port
310     */
311    virtual BaseMasterPort* getMasterPort();
312
313    // Caching misc register values here.
314    // Writing to misc registers needs to invalidate them.
315    // translateFunctional/translateSe/translateFs checks if they are
316    // invalid and call updateMiscReg if necessary.
317protected:
318    bool aarch64;
319    ExceptionLevel aarch64EL;
320    SCTLR sctlr;
321    SCR scr;
322    bool isPriv;
323    bool isSecure;
324    bool isHyp;
325    TTBCR ttbcr;
326    uint16_t asid;
327    uint8_t vmid;
328    PRRR prrr;
329    NMRR nmrr;
330    HCR hcr;
331    uint32_t dacr;
332    bool miscRegValid;
333    ArmTranslationType curTranType;
334
335    // Cached copies of system-level properties
336    bool haveLPAE;
337    bool haveVirtualization;
338    bool haveLargeAsid64;
339
340    void updateMiscReg(ThreadContext *tc,
341                       ArmTranslationType tranType = NormalTran);
342
343public:
344    const Params *
345    params() const
346    {
347        return dynamic_cast<const Params *>(_params);
348    }
349    inline void invalidateMiscReg() { miscRegValid = false; }
350
351private:
352    /** Remove any entries that match both a va and asn
353     * @param mva virtual address to flush
354     * @param asn contextid/asn to flush on match
355     * @param secure_lookup if the operation affects the secure world
356     * @param hyp if the operation affects hyp mode
357     * @param ignore_asn if the flush should ignore the asn
358     */
359    void _flushMva(Addr mva, uint64_t asn, bool secure_lookup,
360                   bool hyp, bool ignore_asn, uint8_t target_el);
361
362    bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el);
363};
364
365} // namespace ArmISA
366
367#endif // __ARCH_ARM_TLB_HH__
368