tlb.hh revision 10687
16019Shines@cs.fsu.edu/*
210037SARM gem5 Developers * Copyright (c) 2010-2013 ARM Limited
37399SAli.Saidi@ARM.com * All rights reserved
47399SAli.Saidi@ARM.com *
57399SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall
67399SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual
77399SAli.Saidi@ARM.com * property including but not limited to intellectual property relating
87399SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software
97399SAli.Saidi@ARM.com * licensed hereunder.  You may use the software subject to the license
107399SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated
117399SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software,
127399SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form.
137399SAli.Saidi@ARM.com *
146019Shines@cs.fsu.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan
156019Shines@cs.fsu.edu * All rights reserved.
166019Shines@cs.fsu.edu *
176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without
186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are
196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright
206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer;
216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright
226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the
236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution;
246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its
256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from
266019Shines@cs.fsu.edu * this software without specific prior written permission.
276019Shines@cs.fsu.edu *
286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
396019Shines@cs.fsu.edu *
407399SAli.Saidi@ARM.com * Authors: Ali Saidi
416019Shines@cs.fsu.edu */
426019Shines@cs.fsu.edu
436019Shines@cs.fsu.edu#ifndef __ARCH_ARM_TLB_HH__
446019Shines@cs.fsu.edu#define __ARCH_ARM_TLB_HH__
456019Shines@cs.fsu.edu
466019Shines@cs.fsu.edu
476019Shines@cs.fsu.edu#include "arch/arm/isa_traits.hh"
488229Snate@binkert.org#include "arch/arm/pagetable.hh"
496019Shines@cs.fsu.edu#include "arch/arm/utility.hh"
506019Shines@cs.fsu.edu#include "arch/arm/vtophys.hh"
5110687SAndreas.Sandberg@ARM.com#include "arch/generic/tlb.hh"
526019Shines@cs.fsu.edu#include "base/statistics.hh"
5310037SARM gem5 Developers#include "dev/dma_device.hh"
546019Shines@cs.fsu.edu#include "mem/request.hh"
556116Snate@binkert.org#include "params/ArmTLB.hh"
5610463SAndreas.Sandberg@ARM.com#include "sim/probe/pmu.hh"
576019Shines@cs.fsu.edu
586019Shines@cs.fsu.educlass ThreadContext;
596019Shines@cs.fsu.edu
606019Shines@cs.fsu.edunamespace ArmISA {
616019Shines@cs.fsu.edu
627404SAli.Saidi@ARM.comclass TableWalker;
6310037SARM gem5 Developersclass Stage2LookUp;
6410037SARM gem5 Developersclass Stage2MMU;
657404SAli.Saidi@ARM.com
666019Shines@cs.fsu.educlass TLB : public BaseTLB
676019Shines@cs.fsu.edu{
687294Sgblack@eecs.umich.edu  public:
697294Sgblack@eecs.umich.edu    enum ArmFlags {
7010037SARM gem5 Developers        AlignmentMask = 0x7,
717294Sgblack@eecs.umich.edu
727294Sgblack@eecs.umich.edu        AlignByte = 0x0,
737294Sgblack@eecs.umich.edu        AlignHalfWord = 0x1,
7410037SARM gem5 Developers        AlignWord = 0x2,
7510037SARM gem5 Developers        AlignDoubleWord = 0x3,
7610037SARM gem5 Developers        AlignQuadWord = 0x4,
7710037SARM gem5 Developers        AlignOctWord = 0x5,
787294Sgblack@eecs.umich.edu
7910037SARM gem5 Developers        AllowUnaligned = 0x8,
807404SAli.Saidi@ARM.com        // Priv code operating as if it wasn't
8110037SARM gem5 Developers        UserMode = 0x10,
827294Sgblack@eecs.umich.edu        // Because zero otherwise looks like a valid setting and may be used
837294Sgblack@eecs.umich.edu        // accidentally, this bit must be non-zero to show it was used on
847294Sgblack@eecs.umich.edu        // purpose.
8510037SARM gem5 Developers        MustBeOne = 0x40
8610037SARM gem5 Developers    };
8710037SARM gem5 Developers
8810037SARM gem5 Developers    enum ArmTranslationType {
8910037SARM gem5 Developers        NormalTran = 0,
9010037SARM gem5 Developers        S1CTran = 0x1,
9110037SARM gem5 Developers        HypMode = 0x2,
9210037SARM gem5 Developers        // Secure code operating as if it wasn't (required by some Address
9310037SARM gem5 Developers        // Translate operations)
9410037SARM gem5 Developers        S1S2NsTran = 0x4
957294Sgblack@eecs.umich.edu    };
966019Shines@cs.fsu.edu  protected:
9710037SARM gem5 Developers    TlbEntry* table;     // the Page Table
9810037SARM gem5 Developers    int size;            // TLB Size
9910037SARM gem5 Developers    bool isStage2;       // Indicates this TLB is part of the second stage MMU
10010037SARM gem5 Developers    bool stage2Req;      // Indicates whether a stage 2 lookup is also required
10110037SARM gem5 Developers    uint64_t _attr;      // Memory attributes for last accessed TLB entry
10210037SARM gem5 Developers    bool directToStage2; // Indicates whether all translation requests should
10310037SARM gem5 Developers                         // be routed directly to the stage 2 TLB
1047436Sdam.sunwoo@arm.com
1057404SAli.Saidi@ARM.com    TableWalker *tableWalker;
10610037SARM gem5 Developers    TLB *stage2Tlb;
10710037SARM gem5 Developers    Stage2MMU *stage2Mmu;
1086019Shines@cs.fsu.edu
1097399SAli.Saidi@ARM.com    // Access Stats
1107734SAli.Saidi@ARM.com    mutable Stats::Scalar instHits;
1117734SAli.Saidi@ARM.com    mutable Stats::Scalar instMisses;
1127734SAli.Saidi@ARM.com    mutable Stats::Scalar readHits;
1137734SAli.Saidi@ARM.com    mutable Stats::Scalar readMisses;
1147734SAli.Saidi@ARM.com    mutable Stats::Scalar writeHits;
1157734SAli.Saidi@ARM.com    mutable Stats::Scalar writeMisses;
1167734SAli.Saidi@ARM.com    mutable Stats::Scalar inserts;
1177734SAli.Saidi@ARM.com    mutable Stats::Scalar flushTlb;
1187734SAli.Saidi@ARM.com    mutable Stats::Scalar flushTlbMva;
1197734SAli.Saidi@ARM.com    mutable Stats::Scalar flushTlbMvaAsid;
1207734SAli.Saidi@ARM.com    mutable Stats::Scalar flushTlbAsid;
1217734SAli.Saidi@ARM.com    mutable Stats::Scalar flushedEntries;
1227734SAli.Saidi@ARM.com    mutable Stats::Scalar alignFaults;
1237734SAli.Saidi@ARM.com    mutable Stats::Scalar prefetchFaults;
1247734SAli.Saidi@ARM.com    mutable Stats::Scalar domainFaults;
1257734SAli.Saidi@ARM.com    mutable Stats::Scalar permsFaults;
1267734SAli.Saidi@ARM.com
1277734SAli.Saidi@ARM.com    Stats::Formula readAccesses;
1287734SAli.Saidi@ARM.com    Stats::Formula writeAccesses;
1297734SAli.Saidi@ARM.com    Stats::Formula instAccesses;
1306019Shines@cs.fsu.edu    Stats::Formula hits;
1316019Shines@cs.fsu.edu    Stats::Formula misses;
1326019Shines@cs.fsu.edu    Stats::Formula accesses;
1336019Shines@cs.fsu.edu
13410463SAndreas.Sandberg@ARM.com    /** PMU probe for TLB refills */
13510463SAndreas.Sandberg@ARM.com    ProbePoints::PMUUPtr ppRefills;
13610463SAndreas.Sandberg@ARM.com
1377697SAli.Saidi@ARM.com    int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
1387404SAli.Saidi@ARM.com
1398527SAli.Saidi@ARM.com    bool bootUncacheability;
1408527SAli.Saidi@ARM.com
1416019Shines@cs.fsu.edu  public:
14210037SARM gem5 Developers    TLB(const ArmTLBParams *p);
14310037SARM gem5 Developers    TLB(const Params *p, int _size, TableWalker *_walker);
1446019Shines@cs.fsu.edu
1459535Smrinmoy.ghosh@arm.com    /** Lookup an entry in the TLB
1469535Smrinmoy.ghosh@arm.com     * @param vpn virtual address
1479535Smrinmoy.ghosh@arm.com     * @param asn context id/address space id to use
14810037SARM gem5 Developers     * @param vmid The virtual machine ID used for stage 2 translation
14910037SARM gem5 Developers     * @param secure if the lookup is secure
15010037SARM gem5 Developers     * @param hyp if the lookup is done from hyp mode
1519535Smrinmoy.ghosh@arm.com     * @param functional if the lookup should modify state
15210037SARM gem5 Developers     * @param ignore_asn if on lookup asn should be ignored
15310037SARM gem5 Developers     * @return pointer to TLB entry if it exists
1549535Smrinmoy.ghosh@arm.com     */
15510037SARM gem5 Developers    TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp,
15610037SARM gem5 Developers                     bool secure, bool functional,
15710037SARM gem5 Developers                     bool ignore_asn, uint8_t target_el);
1589535Smrinmoy.ghosh@arm.com
1596019Shines@cs.fsu.edu    virtual ~TLB();
16010037SARM gem5 Developers
16110194SGeoffrey.Blake@arm.com    void takeOverFrom(BaseTLB *otlb);
16210194SGeoffrey.Blake@arm.com
16310037SARM gem5 Developers    /// setup all the back pointers
16410037SARM gem5 Developers    virtual void init();
16510037SARM gem5 Developers
16610037SARM gem5 Developers    void setMMU(Stage2MMU *m);
16710037SARM gem5 Developers
1686019Shines@cs.fsu.edu    int getsize() const { return size; }
1696019Shines@cs.fsu.edu
1707404SAli.Saidi@ARM.com    void insert(Addr vaddr, TlbEntry &pte);
1717404SAli.Saidi@ARM.com
17210037SARM gem5 Developers    Fault getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode,
17310037SARM gem5 Developers                Translation *translation, bool timing, bool functional,
17410037SARM gem5 Developers                bool is_secure, ArmTranslationType tranType);
17510037SARM gem5 Developers
17610037SARM gem5 Developers    Fault getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc,
17710037SARM gem5 Developers                      Mode mode, Translation *translation, bool timing,
17810037SARM gem5 Developers                      bool functional, TlbEntry *mergeTe);
17910037SARM gem5 Developers
18010037SARM gem5 Developers    Fault checkPermissions(TlbEntry *te, RequestPtr req, Mode mode);
18110037SARM gem5 Developers    Fault checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode,
18210037SARM gem5 Developers                             ThreadContext *tc);
18310037SARM gem5 Developers
18410037SARM gem5 Developers
18510037SARM gem5 Developers    /** Reset the entire TLB
18610037SARM gem5 Developers     * @param secure_lookup if the operation affects the secure world
18710037SARM gem5 Developers     */
18810037SARM gem5 Developers    void flushAllSecurity(bool secure_lookup, uint8_t target_el,
18910037SARM gem5 Developers                          bool ignore_el = false);
19010037SARM gem5 Developers
19110037SARM gem5 Developers    /** Remove all entries in the non secure world, depending on whether they
19210037SARM gem5 Developers     *  were allocated in hyp mode or not
19310037SARM gem5 Developers     * @param hyp if the opperation affects hyp mode
19410037SARM gem5 Developers     */
19510037SARM gem5 Developers    void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false);
19610037SARM gem5 Developers
19710037SARM gem5 Developers
19810037SARM gem5 Developers    /** Reset the entire TLB. Used for CPU switching to prevent stale
19910037SARM gem5 Developers     * translations after multiple switches
20010037SARM gem5 Developers     */
20110037SARM gem5 Developers    void flushAll()
20210037SARM gem5 Developers    {
20310037SARM gem5 Developers        flushAllSecurity(false, 0, true);
20410037SARM gem5 Developers        flushAllSecurity(true, 0, true);
20510037SARM gem5 Developers    }
2067404SAli.Saidi@ARM.com
2077404SAli.Saidi@ARM.com    /** Remove any entries that match both a va and asn
2087404SAli.Saidi@ARM.com     * @param mva virtual address to flush
2097404SAli.Saidi@ARM.com     * @param asn contextid/asn to flush on match
21010037SARM gem5 Developers     * @param secure_lookup if the operation affects the secure world
2117404SAli.Saidi@ARM.com     */
21210037SARM gem5 Developers    void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup,
21310037SARM gem5 Developers                      uint8_t target_el);
2147404SAli.Saidi@ARM.com
2157404SAli.Saidi@ARM.com    /** Remove any entries that match the asn
2167404SAli.Saidi@ARM.com     * @param asn contextid/asn to flush on match
21710037SARM gem5 Developers     * @param secure_lookup if the operation affects the secure world
2187404SAli.Saidi@ARM.com     */
21910037SARM gem5 Developers    void flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el);
2207404SAli.Saidi@ARM.com
2217404SAli.Saidi@ARM.com    /** Remove all entries that match the va regardless of asn
2227404SAli.Saidi@ARM.com     * @param mva address to flush from cache
22310037SARM gem5 Developers     * @param secure_lookup if the operation affects the secure world
22410037SARM gem5 Developers     * @param hyp if the operation affects hyp mode
2257404SAli.Saidi@ARM.com     */
22610037SARM gem5 Developers    void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el);
2277404SAli.Saidi@ARM.com
22810037SARM gem5 Developers    Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain);
22910037SARM gem5 Developers    Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec,
23010037SARM gem5 Developers            bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level);
2317404SAli.Saidi@ARM.com
23210037SARM gem5 Developers    void printTlb() const;
2337404SAli.Saidi@ARM.com
2348527SAli.Saidi@ARM.com    void allCpusCaching() { bootUncacheability = true; }
2356019Shines@cs.fsu.edu    void demapPage(Addr vaddr, uint64_t asn)
2366019Shines@cs.fsu.edu    {
23710037SARM gem5 Developers        // needed for x86 only
23810037SARM gem5 Developers        panic("demapPage() is not implemented.\n");
2396019Shines@cs.fsu.edu    }
2406019Shines@cs.fsu.edu
2416019Shines@cs.fsu.edu    static bool validVirtualAddress(Addr vaddr);
2426019Shines@cs.fsu.edu
2437694SAli.Saidi@ARM.com    /**
2447694SAli.Saidi@ARM.com     * Do a functional lookup on the TLB (for debugging)
2457694SAli.Saidi@ARM.com     * and don't modify any internal state
2467694SAli.Saidi@ARM.com     * @param tc thread context to get the context id from
2477694SAli.Saidi@ARM.com     * @param vaddr virtual address to translate
2487694SAli.Saidi@ARM.com     * @param pa returned physical address
2497694SAli.Saidi@ARM.com     * @return if the translation was successful
2507694SAli.Saidi@ARM.com     */
2517694SAli.Saidi@ARM.com    bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
2527694SAli.Saidi@ARM.com
2538733Sgeoffrey.blake@arm.com    /**
2548733Sgeoffrey.blake@arm.com     * Do a functional lookup on the TLB (for checker cpu) that
2558733Sgeoffrey.blake@arm.com     * behaves like a normal lookup without modifying any page table state.
2568733Sgeoffrey.blake@arm.com     */
25710037SARM gem5 Developers    Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode,
25810037SARM gem5 Developers            ArmTranslationType tranType = NormalTran);
2598733Sgeoffrey.blake@arm.com
2607436Sdam.sunwoo@arm.com    /** Accessor functions for memory attributes for last accessed TLB entry
2617436Sdam.sunwoo@arm.com     */
2627436Sdam.sunwoo@arm.com    void
26310037SARM gem5 Developers    setAttr(uint64_t attr)
2647436Sdam.sunwoo@arm.com    {
2657436Sdam.sunwoo@arm.com        _attr = attr;
2667436Sdam.sunwoo@arm.com    }
26710037SARM gem5 Developers
26810037SARM gem5 Developers    uint64_t
2697436Sdam.sunwoo@arm.com    getAttr() const
2707436Sdam.sunwoo@arm.com    {
2717436Sdam.sunwoo@arm.com        return _attr;
2727436Sdam.sunwoo@arm.com    }
2737436Sdam.sunwoo@arm.com
2747404SAli.Saidi@ARM.com    Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
2758733Sgeoffrey.blake@arm.com            Translation *translation, bool &delay,
27610037SARM gem5 Developers            bool timing, ArmTranslationType tranType, bool functional = false);
2777404SAli.Saidi@ARM.com    Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
2787404SAli.Saidi@ARM.com            Translation *translation, bool &delay, bool timing);
27910037SARM gem5 Developers    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode,
28010037SARM gem5 Developers            ArmTranslationType tranType = NormalTran);
2817404SAli.Saidi@ARM.com    Fault translateTiming(RequestPtr req, ThreadContext *tc,
28210037SARM gem5 Developers            Translation *translation, Mode mode,
28310037SARM gem5 Developers            ArmTranslationType tranType = NormalTran);
28410037SARM gem5 Developers    Fault translateComplete(RequestPtr req, ThreadContext *tc,
28510037SARM gem5 Developers            Translation *translation, Mode mode, ArmTranslationType tranType,
28610037SARM gem5 Developers            bool callFromS2);
2879738Sandreas@sandberg.pp.se    Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
2886116Snate@binkert.org
2899439SAndreas.Sandberg@ARM.com    void drainResume();
2909439SAndreas.Sandberg@ARM.com
2916019Shines@cs.fsu.edu    // Checkpointing
2926019Shines@cs.fsu.edu    void serialize(std::ostream &os);
2936019Shines@cs.fsu.edu    void unserialize(Checkpoint *cp, const std::string &section);
2946019Shines@cs.fsu.edu
2956019Shines@cs.fsu.edu    void regStats();
2967749SAli.Saidi@ARM.com
29710463SAndreas.Sandberg@ARM.com    void regProbePoints() M5_ATTR_OVERRIDE;
29810463SAndreas.Sandberg@ARM.com
2998922Swilliam.wang@arm.com    /**
3008922Swilliam.wang@arm.com     * Get the table walker master port. This is used for migrating
3018922Swilliam.wang@arm.com     * port connections during a CPU takeOverFrom() call. For
3028922Swilliam.wang@arm.com     * architectures that do not have a table walker, NULL is
3038922Swilliam.wang@arm.com     * returned, hence the use of a pointer rather than a
3048922Swilliam.wang@arm.com     * reference. For ARM this method will always return a valid port
3058922Swilliam.wang@arm.com     * pointer.
3068922Swilliam.wang@arm.com     *
3078922Swilliam.wang@arm.com     * @return A pointer to the walker master port
3088922Swilliam.wang@arm.com     */
3099294Sandreas.hansson@arm.com    virtual BaseMasterPort* getMasterPort();
3107781SAli.Saidi@ARM.com
31110037SARM gem5 Developers    /**
31210037SARM gem5 Developers     * Allow the MMU (overseeing both stage 1 and stage 2 TLBs) to
31310037SARM gem5 Developers     * access the table walker port of this TLB so that it can
31410037SARM gem5 Developers     * orchestrate staged translations.
31510037SARM gem5 Developers     *
31610037SARM gem5 Developers     * @return The table walker DMA port
31710037SARM gem5 Developers     */
31810037SARM gem5 Developers    DmaPort& getWalkerPort();
31910037SARM gem5 Developers
3207749SAli.Saidi@ARM.com    // Caching misc register values here.
3217749SAli.Saidi@ARM.com    // Writing to misc registers needs to invalidate them.
3227749SAli.Saidi@ARM.com    // translateFunctional/translateSe/translateFs checks if they are
3237749SAli.Saidi@ARM.com    // invalid and call updateMiscReg if necessary.
3247749SAli.Saidi@ARM.comprotected:
32510037SARM gem5 Developers    bool aarch64;
32610037SARM gem5 Developers    ExceptionLevel aarch64EL;
3277749SAli.Saidi@ARM.com    SCTLR sctlr;
32810037SARM gem5 Developers    SCR scr;
3297749SAli.Saidi@ARM.com    bool isPriv;
33010037SARM gem5 Developers    bool isSecure;
33110037SARM gem5 Developers    bool isHyp;
33210037SARM gem5 Developers    TTBCR ttbcr;
33310037SARM gem5 Developers    uint16_t asid;
33410037SARM gem5 Developers    uint8_t vmid;
3357749SAli.Saidi@ARM.com    PRRR prrr;
3367749SAli.Saidi@ARM.com    NMRR nmrr;
33710037SARM gem5 Developers    HCR hcr;
3387749SAli.Saidi@ARM.com    uint32_t dacr;
3397749SAli.Saidi@ARM.com    bool miscRegValid;
34010037SARM gem5 Developers    ArmTranslationType curTranType;
34110037SARM gem5 Developers
34210037SARM gem5 Developers    // Cached copies of system-level properties
34310037SARM gem5 Developers    bool haveLPAE;
34410037SARM gem5 Developers    bool haveVirtualization;
34510037SARM gem5 Developers    bool haveLargeAsid64;
34610037SARM gem5 Developers
34710037SARM gem5 Developers    void updateMiscReg(ThreadContext *tc,
34810037SARM gem5 Developers                       ArmTranslationType tranType = NormalTran);
34910037SARM gem5 Developers
3507749SAli.Saidi@ARM.compublic:
3518299Schander.sudanthi@arm.com    const Params *
3528299Schander.sudanthi@arm.com    params() const
3538299Schander.sudanthi@arm.com    {
3548299Schander.sudanthi@arm.com        return dynamic_cast<const Params *>(_params);
3558299Schander.sudanthi@arm.com    }
3567749SAli.Saidi@ARM.com    inline void invalidateMiscReg() { miscRegValid = false; }
35710037SARM gem5 Developers
35810037SARM gem5 Developersprivate:
35910037SARM gem5 Developers    /** Remove any entries that match both a va and asn
36010037SARM gem5 Developers     * @param mva virtual address to flush
36110037SARM gem5 Developers     * @param asn contextid/asn to flush on match
36210037SARM gem5 Developers     * @param secure_lookup if the operation affects the secure world
36310037SARM gem5 Developers     * @param hyp if the operation affects hyp mode
36410037SARM gem5 Developers     * @param ignore_asn if the flush should ignore the asn
36510037SARM gem5 Developers     */
36610037SARM gem5 Developers    void _flushMva(Addr mva, uint64_t asn, bool secure_lookup,
36710037SARM gem5 Developers                   bool hyp, bool ignore_asn, uint8_t target_el);
36810037SARM gem5 Developers
36910037SARM gem5 Developers    bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el);
3706019Shines@cs.fsu.edu};
3716019Shines@cs.fsu.edu
3727811Ssteve.reinhardt@amd.com} // namespace ArmISA
3736019Shines@cs.fsu.edu
3746019Shines@cs.fsu.edu#endif // __ARCH_ARM_TLB_HH__
375