tlb.hh revision 10037
16019Shines@cs.fsu.edu/* 210037SARM gem5 Developers * Copyright (c) 2010-2013 ARM Limited 37399SAli.Saidi@ARM.com * All rights reserved 47399SAli.Saidi@ARM.com * 57399SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67399SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77399SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87399SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97399SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107399SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117399SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127399SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137399SAli.Saidi@ARM.com * 146019Shines@cs.fsu.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * All rights reserved. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 266019Shines@cs.fsu.edu * this software without specific prior written permission. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019Shines@cs.fsu.edu * 407399SAli.Saidi@ARM.com * Authors: Ali Saidi 416019Shines@cs.fsu.edu */ 426019Shines@cs.fsu.edu 436019Shines@cs.fsu.edu#ifndef __ARCH_ARM_TLB_HH__ 446019Shines@cs.fsu.edu#define __ARCH_ARM_TLB_HH__ 456019Shines@cs.fsu.edu 466019Shines@cs.fsu.edu 476019Shines@cs.fsu.edu#include "arch/arm/isa_traits.hh" 488229Snate@binkert.org#include "arch/arm/pagetable.hh" 496019Shines@cs.fsu.edu#include "arch/arm/utility.hh" 506019Shines@cs.fsu.edu#include "arch/arm/vtophys.hh" 516019Shines@cs.fsu.edu#include "base/statistics.hh" 5210037SARM gem5 Developers#include "dev/dma_device.hh" 536019Shines@cs.fsu.edu#include "mem/request.hh" 546116Snate@binkert.org#include "params/ArmTLB.hh" 557878Sgblack@eecs.umich.edu#include "sim/fault_fwd.hh" 566019Shines@cs.fsu.edu#include "sim/tlb.hh" 576019Shines@cs.fsu.edu 586019Shines@cs.fsu.educlass ThreadContext; 596019Shines@cs.fsu.edu 606019Shines@cs.fsu.edunamespace ArmISA { 616019Shines@cs.fsu.edu 627404SAli.Saidi@ARM.comclass TableWalker; 6310037SARM gem5 Developersclass Stage2LookUp; 6410037SARM gem5 Developersclass Stage2MMU; 657404SAli.Saidi@ARM.com 666019Shines@cs.fsu.educlass TLB : public BaseTLB 676019Shines@cs.fsu.edu{ 687294Sgblack@eecs.umich.edu public: 697294Sgblack@eecs.umich.edu enum ArmFlags { 7010037SARM gem5 Developers AlignmentMask = 0x7, 717294Sgblack@eecs.umich.edu 727294Sgblack@eecs.umich.edu AlignByte = 0x0, 737294Sgblack@eecs.umich.edu AlignHalfWord = 0x1, 7410037SARM gem5 Developers AlignWord = 0x2, 7510037SARM gem5 Developers AlignDoubleWord = 0x3, 7610037SARM gem5 Developers AlignQuadWord = 0x4, 7710037SARM gem5 Developers AlignOctWord = 0x5, 787294Sgblack@eecs.umich.edu 7910037SARM gem5 Developers AllowUnaligned = 0x8, 807404SAli.Saidi@ARM.com // Priv code operating as if it wasn't 8110037SARM gem5 Developers UserMode = 0x10, 827294Sgblack@eecs.umich.edu // Because zero otherwise looks like a valid setting and may be used 837294Sgblack@eecs.umich.edu // accidentally, this bit must be non-zero to show it was used on 847294Sgblack@eecs.umich.edu // purpose. 8510037SARM gem5 Developers MustBeOne = 0x40 8610037SARM gem5 Developers }; 8710037SARM gem5 Developers 8810037SARM gem5 Developers enum ArmTranslationType { 8910037SARM gem5 Developers NormalTran = 0, 9010037SARM gem5 Developers S1CTran = 0x1, 9110037SARM gem5 Developers HypMode = 0x2, 9210037SARM gem5 Developers // Secure code operating as if it wasn't (required by some Address 9310037SARM gem5 Developers // Translate operations) 9410037SARM gem5 Developers S1S2NsTran = 0x4 957294Sgblack@eecs.umich.edu }; 966019Shines@cs.fsu.edu protected: 9710037SARM gem5 Developers TlbEntry* table; // the Page Table 9810037SARM gem5 Developers int size; // TLB Size 9910037SARM gem5 Developers bool isStage2; // Indicates this TLB is part of the second stage MMU 10010037SARM gem5 Developers bool stage2Req; // Indicates whether a stage 2 lookup is also required 10110037SARM gem5 Developers uint64_t _attr; // Memory attributes for last accessed TLB entry 10210037SARM gem5 Developers bool directToStage2; // Indicates whether all translation requests should 10310037SARM gem5 Developers // be routed directly to the stage 2 TLB 1047436Sdam.sunwoo@arm.com 1057404SAli.Saidi@ARM.com TableWalker *tableWalker; 10610037SARM gem5 Developers TLB *stage2Tlb; 10710037SARM gem5 Developers Stage2MMU *stage2Mmu; 1086019Shines@cs.fsu.edu 1097399SAli.Saidi@ARM.com // Access Stats 1107734SAli.Saidi@ARM.com mutable Stats::Scalar instHits; 1117734SAli.Saidi@ARM.com mutable Stats::Scalar instMisses; 1127734SAli.Saidi@ARM.com mutable Stats::Scalar readHits; 1137734SAli.Saidi@ARM.com mutable Stats::Scalar readMisses; 1147734SAli.Saidi@ARM.com mutable Stats::Scalar writeHits; 1157734SAli.Saidi@ARM.com mutable Stats::Scalar writeMisses; 1167734SAli.Saidi@ARM.com mutable Stats::Scalar inserts; 1177734SAli.Saidi@ARM.com mutable Stats::Scalar flushTlb; 1187734SAli.Saidi@ARM.com mutable Stats::Scalar flushTlbMva; 1197734SAli.Saidi@ARM.com mutable Stats::Scalar flushTlbMvaAsid; 1207734SAli.Saidi@ARM.com mutable Stats::Scalar flushTlbAsid; 1217734SAli.Saidi@ARM.com mutable Stats::Scalar flushedEntries; 1227734SAli.Saidi@ARM.com mutable Stats::Scalar alignFaults; 1237734SAli.Saidi@ARM.com mutable Stats::Scalar prefetchFaults; 1247734SAli.Saidi@ARM.com mutable Stats::Scalar domainFaults; 1257734SAli.Saidi@ARM.com mutable Stats::Scalar permsFaults; 1267734SAli.Saidi@ARM.com 1277734SAli.Saidi@ARM.com Stats::Formula readAccesses; 1287734SAli.Saidi@ARM.com Stats::Formula writeAccesses; 1297734SAli.Saidi@ARM.com Stats::Formula instAccesses; 1306019Shines@cs.fsu.edu Stats::Formula hits; 1316019Shines@cs.fsu.edu Stats::Formula misses; 1326019Shines@cs.fsu.edu Stats::Formula accesses; 1336019Shines@cs.fsu.edu 1347697SAli.Saidi@ARM.com int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU 1357404SAli.Saidi@ARM.com 1368527SAli.Saidi@ARM.com bool bootUncacheability; 1378527SAli.Saidi@ARM.com 1386019Shines@cs.fsu.edu public: 13910037SARM gem5 Developers TLB(const ArmTLBParams *p); 14010037SARM gem5 Developers TLB(const Params *p, int _size, TableWalker *_walker); 1416019Shines@cs.fsu.edu 1429535Smrinmoy.ghosh@arm.com /** Lookup an entry in the TLB 1439535Smrinmoy.ghosh@arm.com * @param vpn virtual address 1449535Smrinmoy.ghosh@arm.com * @param asn context id/address space id to use 14510037SARM gem5 Developers * @param vmid The virtual machine ID used for stage 2 translation 14610037SARM gem5 Developers * @param secure if the lookup is secure 14710037SARM gem5 Developers * @param hyp if the lookup is done from hyp mode 1489535Smrinmoy.ghosh@arm.com * @param functional if the lookup should modify state 14910037SARM gem5 Developers * @param ignore_asn if on lookup asn should be ignored 15010037SARM gem5 Developers * @return pointer to TLB entry if it exists 1519535Smrinmoy.ghosh@arm.com */ 15210037SARM gem5 Developers TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp, 15310037SARM gem5 Developers bool secure, bool functional, 15410037SARM gem5 Developers bool ignore_asn, uint8_t target_el); 1559535Smrinmoy.ghosh@arm.com 1566019Shines@cs.fsu.edu virtual ~TLB(); 15710037SARM gem5 Developers 15810037SARM gem5 Developers /// setup all the back pointers 15910037SARM gem5 Developers virtual void init(); 16010037SARM gem5 Developers 16110037SARM gem5 Developers void setMMU(Stage2MMU *m); 16210037SARM gem5 Developers 1636019Shines@cs.fsu.edu int getsize() const { return size; } 1646019Shines@cs.fsu.edu 1657404SAli.Saidi@ARM.com void insert(Addr vaddr, TlbEntry &pte); 1667404SAli.Saidi@ARM.com 16710037SARM gem5 Developers Fault getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, 16810037SARM gem5 Developers Translation *translation, bool timing, bool functional, 16910037SARM gem5 Developers bool is_secure, ArmTranslationType tranType); 17010037SARM gem5 Developers 17110037SARM gem5 Developers Fault getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc, 17210037SARM gem5 Developers Mode mode, Translation *translation, bool timing, 17310037SARM gem5 Developers bool functional, TlbEntry *mergeTe); 17410037SARM gem5 Developers 17510037SARM gem5 Developers Fault checkPermissions(TlbEntry *te, RequestPtr req, Mode mode); 17610037SARM gem5 Developers Fault checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode, 17710037SARM gem5 Developers ThreadContext *tc); 17810037SARM gem5 Developers 17910037SARM gem5 Developers 18010037SARM gem5 Developers /** Reset the entire TLB 18110037SARM gem5 Developers * @param secure_lookup if the operation affects the secure world 18210037SARM gem5 Developers */ 18310037SARM gem5 Developers void flushAllSecurity(bool secure_lookup, uint8_t target_el, 18410037SARM gem5 Developers bool ignore_el = false); 18510037SARM gem5 Developers 18610037SARM gem5 Developers /** Remove all entries in the non secure world, depending on whether they 18710037SARM gem5 Developers * were allocated in hyp mode or not 18810037SARM gem5 Developers * @param hyp if the opperation affects hyp mode 18910037SARM gem5 Developers */ 19010037SARM gem5 Developers void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false); 19110037SARM gem5 Developers 19210037SARM gem5 Developers 19310037SARM gem5 Developers /** Reset the entire TLB. Used for CPU switching to prevent stale 19410037SARM gem5 Developers * translations after multiple switches 19510037SARM gem5 Developers */ 19610037SARM gem5 Developers void flushAll() 19710037SARM gem5 Developers { 19810037SARM gem5 Developers flushAllSecurity(false, 0, true); 19910037SARM gem5 Developers flushAllSecurity(true, 0, true); 20010037SARM gem5 Developers } 2017404SAli.Saidi@ARM.com 2027404SAli.Saidi@ARM.com /** Remove any entries that match both a va and asn 2037404SAli.Saidi@ARM.com * @param mva virtual address to flush 2047404SAli.Saidi@ARM.com * @param asn contextid/asn to flush on match 20510037SARM gem5 Developers * @param secure_lookup if the operation affects the secure world 2067404SAli.Saidi@ARM.com */ 20710037SARM gem5 Developers void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup, 20810037SARM gem5 Developers uint8_t target_el); 2097404SAli.Saidi@ARM.com 2107404SAli.Saidi@ARM.com /** Remove any entries that match the asn 2117404SAli.Saidi@ARM.com * @param asn contextid/asn to flush on match 21210037SARM gem5 Developers * @param secure_lookup if the operation affects the secure world 2137404SAli.Saidi@ARM.com */ 21410037SARM gem5 Developers void flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el); 2157404SAli.Saidi@ARM.com 2167404SAli.Saidi@ARM.com /** Remove all entries that match the va regardless of asn 2177404SAli.Saidi@ARM.com * @param mva address to flush from cache 21810037SARM gem5 Developers * @param secure_lookup if the operation affects the secure world 21910037SARM gem5 Developers * @param hyp if the operation affects hyp mode 2207404SAli.Saidi@ARM.com */ 22110037SARM gem5 Developers void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el); 2227404SAli.Saidi@ARM.com 22310037SARM gem5 Developers Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain); 22410037SARM gem5 Developers Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec, 22510037SARM gem5 Developers bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level); 2267404SAli.Saidi@ARM.com 22710037SARM gem5 Developers void printTlb() const; 2287404SAli.Saidi@ARM.com 2298527SAli.Saidi@ARM.com void allCpusCaching() { bootUncacheability = true; } 2306019Shines@cs.fsu.edu void demapPage(Addr vaddr, uint64_t asn) 2316019Shines@cs.fsu.edu { 23210037SARM gem5 Developers // needed for x86 only 23310037SARM gem5 Developers panic("demapPage() is not implemented.\n"); 2346019Shines@cs.fsu.edu } 2356019Shines@cs.fsu.edu 2366019Shines@cs.fsu.edu static bool validVirtualAddress(Addr vaddr); 2376019Shines@cs.fsu.edu 2387694SAli.Saidi@ARM.com /** 2397694SAli.Saidi@ARM.com * Do a functional lookup on the TLB (for debugging) 2407694SAli.Saidi@ARM.com * and don't modify any internal state 2417694SAli.Saidi@ARM.com * @param tc thread context to get the context id from 2427694SAli.Saidi@ARM.com * @param vaddr virtual address to translate 2437694SAli.Saidi@ARM.com * @param pa returned physical address 2447694SAli.Saidi@ARM.com * @return if the translation was successful 2457694SAli.Saidi@ARM.com */ 2467694SAli.Saidi@ARM.com bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr); 2477694SAli.Saidi@ARM.com 2488733Sgeoffrey.blake@arm.com /** 2498733Sgeoffrey.blake@arm.com * Do a functional lookup on the TLB (for checker cpu) that 2508733Sgeoffrey.blake@arm.com * behaves like a normal lookup without modifying any page table state. 2518733Sgeoffrey.blake@arm.com */ 25210037SARM gem5 Developers Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode, 25310037SARM gem5 Developers ArmTranslationType tranType = NormalTran); 2548733Sgeoffrey.blake@arm.com 2557436Sdam.sunwoo@arm.com /** Accessor functions for memory attributes for last accessed TLB entry 2567436Sdam.sunwoo@arm.com */ 2577436Sdam.sunwoo@arm.com void 25810037SARM gem5 Developers setAttr(uint64_t attr) 2597436Sdam.sunwoo@arm.com { 2607436Sdam.sunwoo@arm.com _attr = attr; 2617436Sdam.sunwoo@arm.com } 26210037SARM gem5 Developers 26310037SARM gem5 Developers uint64_t 2647436Sdam.sunwoo@arm.com getAttr() const 2657436Sdam.sunwoo@arm.com { 2667436Sdam.sunwoo@arm.com return _attr; 2677436Sdam.sunwoo@arm.com } 2687436Sdam.sunwoo@arm.com 2697404SAli.Saidi@ARM.com Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 2708733Sgeoffrey.blake@arm.com Translation *translation, bool &delay, 27110037SARM gem5 Developers bool timing, ArmTranslationType tranType, bool functional = false); 2727404SAli.Saidi@ARM.com Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 2737404SAli.Saidi@ARM.com Translation *translation, bool &delay, bool timing); 27410037SARM gem5 Developers Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode, 27510037SARM gem5 Developers ArmTranslationType tranType = NormalTran); 2767404SAli.Saidi@ARM.com Fault translateTiming(RequestPtr req, ThreadContext *tc, 27710037SARM gem5 Developers Translation *translation, Mode mode, 27810037SARM gem5 Developers ArmTranslationType tranType = NormalTran); 27910037SARM gem5 Developers Fault translateComplete(RequestPtr req, ThreadContext *tc, 28010037SARM gem5 Developers Translation *translation, Mode mode, ArmTranslationType tranType, 28110037SARM gem5 Developers bool callFromS2); 2829738Sandreas@sandberg.pp.se Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const; 2836116Snate@binkert.org 2849439SAndreas.Sandberg@ARM.com void drainResume(); 2859439SAndreas.Sandberg@ARM.com 2866019Shines@cs.fsu.edu // Checkpointing 2876019Shines@cs.fsu.edu void serialize(std::ostream &os); 2886019Shines@cs.fsu.edu void unserialize(Checkpoint *cp, const std::string §ion); 2896019Shines@cs.fsu.edu 2906019Shines@cs.fsu.edu void regStats(); 2917749SAli.Saidi@ARM.com 2928922Swilliam.wang@arm.com /** 2938922Swilliam.wang@arm.com * Get the table walker master port. This is used for migrating 2948922Swilliam.wang@arm.com * port connections during a CPU takeOverFrom() call. For 2958922Swilliam.wang@arm.com * architectures that do not have a table walker, NULL is 2968922Swilliam.wang@arm.com * returned, hence the use of a pointer rather than a 2978922Swilliam.wang@arm.com * reference. For ARM this method will always return a valid port 2988922Swilliam.wang@arm.com * pointer. 2998922Swilliam.wang@arm.com * 3008922Swilliam.wang@arm.com * @return A pointer to the walker master port 3018922Swilliam.wang@arm.com */ 3029294Sandreas.hansson@arm.com virtual BaseMasterPort* getMasterPort(); 3037781SAli.Saidi@ARM.com 30410037SARM gem5 Developers /** 30510037SARM gem5 Developers * Allow the MMU (overseeing both stage 1 and stage 2 TLBs) to 30610037SARM gem5 Developers * access the table walker port of this TLB so that it can 30710037SARM gem5 Developers * orchestrate staged translations. 30810037SARM gem5 Developers * 30910037SARM gem5 Developers * @return The table walker DMA port 31010037SARM gem5 Developers */ 31110037SARM gem5 Developers DmaPort& getWalkerPort(); 31210037SARM gem5 Developers 3137749SAli.Saidi@ARM.com // Caching misc register values here. 3147749SAli.Saidi@ARM.com // Writing to misc registers needs to invalidate them. 3157749SAli.Saidi@ARM.com // translateFunctional/translateSe/translateFs checks if they are 3167749SAli.Saidi@ARM.com // invalid and call updateMiscReg if necessary. 3177749SAli.Saidi@ARM.comprotected: 31810037SARM gem5 Developers bool aarch64; 31910037SARM gem5 Developers ExceptionLevel aarch64EL; 3207749SAli.Saidi@ARM.com SCTLR sctlr; 32110037SARM gem5 Developers SCR scr; 3227749SAli.Saidi@ARM.com bool isPriv; 32310037SARM gem5 Developers bool isSecure; 32410037SARM gem5 Developers bool isHyp; 32510037SARM gem5 Developers TTBCR ttbcr; 32610037SARM gem5 Developers uint16_t asid; 32710037SARM gem5 Developers uint8_t vmid; 3287749SAli.Saidi@ARM.com PRRR prrr; 3297749SAli.Saidi@ARM.com NMRR nmrr; 33010037SARM gem5 Developers HCR hcr; 3317749SAli.Saidi@ARM.com uint32_t dacr; 3327749SAli.Saidi@ARM.com bool miscRegValid; 33310037SARM gem5 Developers ArmTranslationType curTranType; 33410037SARM gem5 Developers 33510037SARM gem5 Developers // Cached copies of system-level properties 33610037SARM gem5 Developers bool haveLPAE; 33710037SARM gem5 Developers bool haveVirtualization; 33810037SARM gem5 Developers bool haveLargeAsid64; 33910037SARM gem5 Developers 34010037SARM gem5 Developers void updateMiscReg(ThreadContext *tc, 34110037SARM gem5 Developers ArmTranslationType tranType = NormalTran); 34210037SARM gem5 Developers 3437749SAli.Saidi@ARM.compublic: 3448299Schander.sudanthi@arm.com const Params * 3458299Schander.sudanthi@arm.com params() const 3468299Schander.sudanthi@arm.com { 3478299Schander.sudanthi@arm.com return dynamic_cast<const Params *>(_params); 3488299Schander.sudanthi@arm.com } 3497749SAli.Saidi@ARM.com inline void invalidateMiscReg() { miscRegValid = false; } 35010037SARM gem5 Developers 35110037SARM gem5 Developersprivate: 35210037SARM gem5 Developers /** Remove any entries that match both a va and asn 35310037SARM gem5 Developers * @param mva virtual address to flush 35410037SARM gem5 Developers * @param asn contextid/asn to flush on match 35510037SARM gem5 Developers * @param secure_lookup if the operation affects the secure world 35610037SARM gem5 Developers * @param hyp if the operation affects hyp mode 35710037SARM gem5 Developers * @param ignore_asn if the flush should ignore the asn 35810037SARM gem5 Developers */ 35910037SARM gem5 Developers void _flushMva(Addr mva, uint64_t asn, bool secure_lookup, 36010037SARM gem5 Developers bool hyp, bool ignore_asn, uint8_t target_el); 36110037SARM gem5 Developers 36210037SARM gem5 Developers bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el); 3636019Shines@cs.fsu.edu}; 3646019Shines@cs.fsu.edu 3657811Ssteve.reinhardt@amd.com} // namespace ArmISA 3666019Shines@cs.fsu.edu 3676019Shines@cs.fsu.edu#endif // __ARCH_ARM_TLB_HH__ 368