tlb.cc revision 8782
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 * Nathan Binkert 42 * Steve Reinhardt 43 */ 44 45#include <string> 46#include <vector> 47 48#include "arch/arm/faults.hh" 49#include "arch/arm/pagetable.hh" 50#include "arch/arm/system.hh" 51#include "arch/arm/table_walker.hh" 52#include "arch/arm/tlb.hh" 53#include "arch/arm/utility.hh" 54#include "base/inifile.hh" 55#include "base/str.hh" 56#include "base/trace.hh" 57#include "cpu/thread_context.hh" 58#include "debug/Checkpoint.hh" 59#include "debug/TLB.hh" 60#include "debug/TLBVerbose.hh" 61#include "mem/page_table.hh" 62#include "params/ArmTLB.hh" 63#include "sim/full_system.hh" 64#include "sim/process.hh" 65 66using namespace std; 67using namespace ArmISA; 68 69TLB::TLB(const Params *p) 70 : BaseTLB(p), size(p->size) , tableWalker(p->walker), 71 rangeMRU(1), bootUncacheability(false), miscRegValid(false) 72{ 73 table = new TlbEntry[size]; 74 memset(table, 0, sizeof(TlbEntry) * size); 75 76 tableWalker->setTlb(this); 77} 78 79TLB::~TLB() 80{ 81 if (table) 82 delete [] table; 83} 84 85bool 86TLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa) 87{ 88 if (!miscRegValid) 89 updateMiscReg(tc); 90 TlbEntry *e = lookup(va, contextId, true); 91 if (!e) 92 return false; 93 pa = e->pAddr(va); 94 return true; 95} 96 97TlbEntry* 98TLB::lookup(Addr va, uint8_t cid, bool functional) 99{ 100 101 TlbEntry *retval = NULL; 102 103 // Maitaining LRU array 104 105 int x = 0; 106 while (retval == NULL && x < size) { 107 if (table[x].match(va, cid)) { 108 109 // We only move the hit entry ahead when the position is higher than rangeMRU 110 if (x > rangeMRU) { 111 TlbEntry tmp_entry = table[x]; 112 for(int i = x; i > 0; i--) 113 table[i] = table[i-1]; 114 table[0] = tmp_entry; 115 retval = &table[0]; 116 } else { 117 retval = &table[x]; 118 } 119 break; 120 } 121 x++; 122 } 123 124 DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n", 125 va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0, 126 retval ? retval->size : 0, retval ? retval->pAddr(va) : 0, 127 retval ? retval->ap : 0); 128 ; 129 return retval; 130} 131 132// insert a new TLB entry 133void 134TLB::insert(Addr addr, TlbEntry &entry) 135{ 136 DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x" 137 " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x" 138 " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid, 139 entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp, 140 entry.xn, entry.ap, entry.domain); 141 142 if (table[size-1].valid) 143 DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n", 144 table[size-1].vpn << table[size-1].N, table[size-1].asid, 145 table[size-1].pfn << table[size-1].N, table[size-1].size, 146 table[size-1].ap); 147 148 //inserting to MRU position and evicting the LRU one 149 150 for(int i = size-1; i > 0; i--) 151 table[i] = table[i-1]; 152 table[0] = entry; 153 154 inserts++; 155} 156 157void 158TLB::printTlb() 159{ 160 int x = 0; 161 TlbEntry *te; 162 DPRINTF(TLB, "Current TLB contents:\n"); 163 while (x < size) { 164 te = &table[x]; 165 if (te->valid) 166 DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n", 167 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 168 x++; 169 } 170} 171 172 173void 174TLB::flushAll() 175{ 176 DPRINTF(TLB, "Flushing all TLB entries\n"); 177 int x = 0; 178 TlbEntry *te; 179 while (x < size) { 180 te = &table[x]; 181 if (te->valid) { 182 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 183 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 184 flushedEntries++; 185 } 186 x++; 187 } 188 189 memset(table, 0, sizeof(TlbEntry) * size); 190 191 flushTlb++; 192} 193 194 195void 196TLB::flushMvaAsid(Addr mva, uint64_t asn) 197{ 198 DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn); 199 TlbEntry *te; 200 201 te = lookup(mva, asn); 202 while (te != NULL) { 203 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 204 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 205 te->valid = false; 206 flushedEntries++; 207 te = lookup(mva,asn); 208 } 209 flushTlbMvaAsid++; 210} 211 212void 213TLB::flushAsid(uint64_t asn) 214{ 215 DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn); 216 217 int x = 0; 218 TlbEntry *te; 219 220 while (x < size) { 221 te = &table[x]; 222 if (te->asid == asn) { 223 te->valid = false; 224 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 225 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 226 flushedEntries++; 227 } 228 x++; 229 } 230 flushTlbAsid++; 231} 232 233void 234TLB::flushMva(Addr mva) 235{ 236 DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva); 237 238 int x = 0; 239 TlbEntry *te; 240 241 while (x < size) { 242 te = &table[x]; 243 Addr v = te->vpn << te->N; 244 if (mva >= v && mva < v + te->size) { 245 te->valid = false; 246 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 247 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 248 flushedEntries++; 249 } 250 x++; 251 } 252 flushTlbMva++; 253} 254 255void 256TLB::serialize(ostream &os) 257{ 258 DPRINTF(Checkpoint, "Serializing Arm TLB\n"); 259 260 SERIALIZE_SCALAR(_attr); 261 262 int num_entries = size; 263 SERIALIZE_SCALAR(num_entries); 264 for(int i = 0; i < size; i++){ 265 nameOut(os, csprintf("%s.TlbEntry%d", name(), i)); 266 table[i].serialize(os); 267 } 268} 269 270void 271TLB::unserialize(Checkpoint *cp, const string §ion) 272{ 273 DPRINTF(Checkpoint, "Unserializing Arm TLB\n"); 274 275 UNSERIALIZE_SCALAR(_attr); 276 int num_entries; 277 UNSERIALIZE_SCALAR(num_entries); 278 for(int i = 0; i < min(size, num_entries); i++){ 279 table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i)); 280 } 281 miscRegValid = false; 282} 283 284void 285TLB::regStats() 286{ 287 instHits 288 .name(name() + ".inst_hits") 289 .desc("ITB inst hits") 290 ; 291 292 instMisses 293 .name(name() + ".inst_misses") 294 .desc("ITB inst misses") 295 ; 296 297 instAccesses 298 .name(name() + ".inst_accesses") 299 .desc("ITB inst accesses") 300 ; 301 302 readHits 303 .name(name() + ".read_hits") 304 .desc("DTB read hits") 305 ; 306 307 readMisses 308 .name(name() + ".read_misses") 309 .desc("DTB read misses") 310 ; 311 312 readAccesses 313 .name(name() + ".read_accesses") 314 .desc("DTB read accesses") 315 ; 316 317 writeHits 318 .name(name() + ".write_hits") 319 .desc("DTB write hits") 320 ; 321 322 writeMisses 323 .name(name() + ".write_misses") 324 .desc("DTB write misses") 325 ; 326 327 writeAccesses 328 .name(name() + ".write_accesses") 329 .desc("DTB write accesses") 330 ; 331 332 hits 333 .name(name() + ".hits") 334 .desc("DTB hits") 335 ; 336 337 misses 338 .name(name() + ".misses") 339 .desc("DTB misses") 340 ; 341 342 accesses 343 .name(name() + ".accesses") 344 .desc("DTB accesses") 345 ; 346 347 flushTlb 348 .name(name() + ".flush_tlb") 349 .desc("Number of times complete TLB was flushed") 350 ; 351 352 flushTlbMva 353 .name(name() + ".flush_tlb_mva") 354 .desc("Number of times TLB was flushed by MVA") 355 ; 356 357 flushTlbMvaAsid 358 .name(name() + ".flush_tlb_mva_asid") 359 .desc("Number of times TLB was flushed by MVA & ASID") 360 ; 361 362 flushTlbAsid 363 .name(name() + ".flush_tlb_asid") 364 .desc("Number of times TLB was flushed by ASID") 365 ; 366 367 flushedEntries 368 .name(name() + ".flush_entries") 369 .desc("Number of entries that have been flushed from TLB") 370 ; 371 372 alignFaults 373 .name(name() + ".align_faults") 374 .desc("Number of TLB faults due to alignment restrictions") 375 ; 376 377 prefetchFaults 378 .name(name() + ".prefetch_faults") 379 .desc("Number of TLB faults due to prefetch") 380 ; 381 382 domainFaults 383 .name(name() + ".domain_faults") 384 .desc("Number of TLB faults due to domain restrictions") 385 ; 386 387 permsFaults 388 .name(name() + ".perms_faults") 389 .desc("Number of TLB faults due to permissions restrictions") 390 ; 391 392 instAccesses = instHits + instMisses; 393 readAccesses = readHits + readMisses; 394 writeAccesses = writeHits + writeMisses; 395 hits = readHits + writeHits + instHits; 396 misses = readMisses + writeMisses + instMisses; 397 accesses = readAccesses + writeAccesses + instAccesses; 398} 399 400Fault 401TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 402 Translation *translation, bool &delay, bool timing) 403{ 404 if (!miscRegValid) 405 updateMiscReg(tc); 406 Addr vaddr = req->getVaddr(); 407 uint32_t flags = req->getFlags(); 408 409 bool is_fetch = (mode == Execute); 410 bool is_write = (mode == Write); 411 412 if (!is_fetch) { 413 assert(flags & MustBeOne); 414 if (sctlr.a || !(flags & AllowUnaligned)) { 415 if (vaddr & flags & AlignmentMask) { 416 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 417 } 418 } 419 } 420 421 if (!FullSystem) { 422 Addr paddr; 423 Process *p = tc->getProcessPtr(); 424 425 if (!p->pTable->translate(vaddr, paddr)) 426 return Fault(new GenericPageTableFault(vaddr)); 427 req->setPaddr(paddr); 428 } 429 430 return NoFault; 431} 432 433Fault 434TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp) 435{ 436 return NoFault; 437} 438 439Fault 440TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec, 441 bool is_write, uint8_t domain, bool sNp) 442{ 443 return NoFault; 444} 445 446Fault 447TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 448 Translation *translation, bool &delay, bool timing) 449{ 450 if (!miscRegValid) { 451 updateMiscReg(tc); 452 DPRINTF(TLBVerbose, "TLB variables changed!\n"); 453 } 454 455 Addr vaddr = req->getVaddr(); 456 uint32_t flags = req->getFlags(); 457 458 bool is_fetch = (mode == Execute); 459 bool is_write = (mode == Write); 460 bool is_priv = isPriv && !(flags & UserMode); 461 462 req->setAsid(contextId.asid); 463 464 DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n", 465 isPriv, flags & UserMode); 466 // If this is a clrex instruction, provide a PA of 0 with no fault 467 // This will force the monitor to set the tracked address to 0 468 // a bit of a hack but this effectively clrears this processors monitor 469 if (flags & Request::CLEAR_LL){ 470 req->setPaddr(0); 471 req->setFlags(Request::UNCACHEABLE); 472 req->setFlags(Request::CLEAR_LL); 473 return NoFault; 474 } 475 if ((req->isInstFetch() && (!sctlr.i)) || 476 ((!req->isInstFetch()) && (!sctlr.c))){ 477 req->setFlags(Request::UNCACHEABLE); 478 } 479 if (!is_fetch) { 480 assert(flags & MustBeOne); 481 if (sctlr.a || !(flags & AllowUnaligned)) { 482 if (vaddr & flags & AlignmentMask) { 483 alignFaults++; 484 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 485 } 486 } 487 } 488 489 Fault fault; 490 491 if (!sctlr.m) { 492 req->setPaddr(vaddr); 493 if (sctlr.tre == 0) { 494 req->setFlags(Request::UNCACHEABLE); 495 } else { 496 if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 497 req->setFlags(Request::UNCACHEABLE); 498 } 499 500 // Set memory attributes 501 TlbEntry temp_te; 502 tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1); 503 temp_te.shareable = true; 504 DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\ 505 %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable, 506 temp_te.innerAttrs, temp_te.outerAttrs); 507 setAttr(temp_te.attributes); 508 509 return trickBoxCheck(req, mode, 0, false); 510 } 511 512 DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, contextId); 513 // Translation enabled 514 515 TlbEntry *te = lookup(vaddr, contextId); 516 if (te == NULL) { 517 if (req->isPrefetch()){ 518 //if the request is a prefetch don't attempt to fill the TLB 519 //or go any further with the memory access 520 prefetchFaults++; 521 return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss); 522 } 523 524 if (is_fetch) 525 instMisses++; 526 else if (is_write) 527 writeMisses++; 528 else 529 readMisses++; 530 531 // start translation table walk, pass variables rather than 532 // re-retreaving in table walker for speed 533 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n", 534 vaddr, contextId); 535 fault = tableWalker->walk(req, tc, contextId, mode, translation, 536 timing); 537 if (timing && fault == NoFault) { 538 delay = true; 539 // for timing mode, return and wait for table walk 540 return fault; 541 } 542 if (fault) 543 return fault; 544 545 te = lookup(vaddr, contextId); 546 if (!te) 547 printTlb(); 548 assert(te); 549 } else { 550 if (is_fetch) 551 instHits++; 552 else if (is_write) 553 writeHits++; 554 else 555 readHits++; 556 } 557 558 // Set memory attributes 559 DPRINTF(TLBVerbose, 560 "Setting memory attributes: shareable: %d, innerAttrs: %d, \ 561 outerAttrs: %d\n", 562 te->shareable, te->innerAttrs, te->outerAttrs); 563 setAttr(te->attributes); 564 if (te->nonCacheable) { 565 req->setFlags(Request::UNCACHEABLE); 566 567 // Prevent prefetching from I/O devices. 568 if (req->isPrefetch()) { 569 return new PrefetchAbort(vaddr, ArmFault::PrefetchUncacheable); 570 } 571 } 572 573 if (FullSystem) { 574 if (!bootUncacheability && 575 ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr)) 576 req->setFlags(Request::UNCACHEABLE); 577 } 578 579 switch ( (dacr >> (te->domain * 2)) & 0x3) { 580 case 0: 581 domainFaults++; 582 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x" 583 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp); 584 if (is_fetch) 585 return new PrefetchAbort(vaddr, 586 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 587 else 588 return new DataAbort(vaddr, te->domain, is_write, 589 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 590 case 1: 591 // Continue with permissions check 592 break; 593 case 2: 594 panic("UNPRED domain\n"); 595 case 3: 596 req->setPaddr(te->pAddr(vaddr)); 597 fault = trickBoxCheck(req, mode, te->domain, te->sNp); 598 if (fault) 599 return fault; 600 return NoFault; 601 } 602 603 uint8_t ap = te->ap; 604 605 if (sctlr.afe == 1) 606 ap |= 1; 607 608 bool abt; 609 610 /* if (!sctlr.xp) 611 ap &= 0x3; 612*/ 613 switch (ap) { 614 case 0: 615 DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs); 616 if (!sctlr.xp) { 617 switch ((int)sctlr.rs) { 618 case 2: 619 abt = is_write; 620 break; 621 case 1: 622 abt = is_write || !is_priv; 623 break; 624 case 0: 625 case 3: 626 default: 627 abt = true; 628 break; 629 } 630 } else { 631 abt = true; 632 } 633 break; 634 case 1: 635 abt = !is_priv; 636 break; 637 case 2: 638 abt = !is_priv && is_write; 639 break; 640 case 3: 641 abt = false; 642 break; 643 case 4: 644 panic("UNPRED premissions\n"); 645 case 5: 646 abt = !is_priv || is_write; 647 break; 648 case 6: 649 case 7: 650 abt = is_write; 651 break; 652 default: 653 panic("Unknown permissions\n"); 654 } 655 if ((is_fetch) && (abt || te->xn)) { 656 permsFaults++; 657 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d" 658 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 659 return new PrefetchAbort(vaddr, 660 (te->sNp ? ArmFault::Permission0 : 661 ArmFault::Permission1)); 662 } else if (abt) { 663 permsFaults++; 664 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 665 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 666 return new DataAbort(vaddr, te->domain, is_write, 667 (te->sNp ? ArmFault::Permission0 : 668 ArmFault::Permission1)); 669 } 670 671 req->setPaddr(te->pAddr(vaddr)); 672 // Check for a trickbox generated address fault 673 fault = trickBoxCheck(req, mode, te->domain, te->sNp); 674 if (fault) 675 return fault; 676 677 return NoFault; 678} 679 680Fault 681TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 682{ 683 bool delay = false; 684 Fault fault; 685 if (FullSystem) 686 fault = translateFs(req, tc, mode, NULL, delay, false); 687 else 688 fault = translateSe(req, tc, mode, NULL, delay, false); 689 assert(!delay); 690 return fault; 691} 692 693Fault 694TLB::translateTiming(RequestPtr req, ThreadContext *tc, 695 Translation *translation, Mode mode) 696{ 697 assert(translation); 698 bool delay = false; 699 Fault fault; 700 if (FullSystem) 701 fault = translateFs(req, tc, mode, translation, delay, true); 702 else 703 fault = translateSe(req, tc, mode, translation, delay, true); 704 DPRINTF(TLBVerbose, "Translation returning delay=%d fault=%d\n", delay, fault != 705 NoFault); 706 if (!delay) 707 translation->finish(fault, req, tc, mode); 708 else 709 translation->markDelayed(); 710 return fault; 711} 712 713Port* 714TLB::getPort() 715{ 716 return tableWalker->getPort("port"); 717} 718 719 720 721ArmISA::TLB * 722ArmTLBParams::create() 723{ 724 return new ArmISA::TLB(this); 725} 726