tlb.cc revision 7733
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 * Nathan Binkert 42 * Steve Reinhardt 43 */ 44 45#include <string> 46#include <vector> 47 48#include "arch/arm/faults.hh" 49#include "arch/arm/pagetable.hh" 50#include "arch/arm/tlb.hh" 51#include "arch/arm/utility.hh" 52#include "base/inifile.hh" 53#include "base/str.hh" 54#include "base/trace.hh" 55#include "cpu/thread_context.hh" 56#include "mem/page_table.hh" 57#include "params/ArmTLB.hh" 58#include "sim/process.hh" 59 60#if FULL_SYSTEM 61#include "arch/arm/table_walker.hh" 62#endif 63 64using namespace std; 65using namespace ArmISA; 66 67TLB::TLB(const Params *p) 68 : BaseTLB(p), size(p->size) 69#if FULL_SYSTEM 70 , tableWalker(p->walker) 71#endif 72 , rangeMRU(1) 73{ 74 table = new TlbEntry[size]; 75 memset(table, 0, sizeof(TlbEntry[size])); 76 77#if FULL_SYSTEM 78 tableWalker->setTlb(this); 79#endif 80} 81 82TLB::~TLB() 83{ 84 if (table) 85 delete [] table; 86} 87 88bool 89TLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa) 90{ 91 uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR); 92 TlbEntry *e = lookup(va, context_id, true); 93 if (!e) 94 return false; 95 pa = e->pAddr(va); 96 return true; 97} 98 99TlbEntry* 100TLB::lookup(Addr va, uint8_t cid, bool functional) 101{ 102 103 TlbEntry *retval = NULL; 104 105 // Maitaining LRU array 106 107 int x = 0; 108 while (retval == NULL && x < size) { 109 if (table[x].match(va, cid)) { 110 111 // We only move the hit entry ahead when the position is higher than rangeMRU 112 if (x > rangeMRU) { 113 TlbEntry tmp_entry = table[x]; 114 for(int i = x; i > 0; i--) 115 table[i] = table[i-1]; 116 table[0] = tmp_entry; 117 retval = &table[0]; 118 } else { 119 retval = &table[x]; 120 } 121 break; 122 } 123 x++; 124 } 125 126 DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n", 127 va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0, 128 retval ? retval->size : 0, retval ? retval->pAddr(va) : 0, 129 retval ? retval->ap : 0); 130 ; 131 return retval; 132} 133 134// insert a new TLB entry 135void 136TLB::insert(Addr addr, TlbEntry &entry) 137{ 138 DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x" 139 " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x" 140 " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid, 141 entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp, 142 entry.xn, entry.ap, entry.domain); 143 144 if (table[size-1].valid) 145 DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n", 146 table[size-1].vpn << table[size-1].N, table[size-1].asid, 147 table[size-1].pfn << table[size-1].N, table[size-1].size, 148 table[size-1].ap); 149 150 //inserting to MRU position and evicting the LRU one 151 152 for(int i = size-1; i > 0; i--) 153 table[i] = table[i-1]; 154 table[0] = entry; 155} 156 157void 158TLB::printTlb() 159{ 160 int x = 0; 161 TlbEntry *te; 162 DPRINTF(TLB, "Current TLB contents:\n"); 163 while (x < size) { 164 te = &table[x]; 165 if (te->valid) 166 DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n", 167 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 168 x++; 169 } 170} 171 172 173void 174TLB::flushAll() 175{ 176 DPRINTF(TLB, "Flushing all TLB entries\n"); 177 int x = 0; 178 TlbEntry *te; 179 while (x < size) { 180 te = &table[x]; 181 if (te->valid) 182 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 183 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 184 x++; 185 } 186 187 memset(table, 0, sizeof(TlbEntry[size])); 188} 189 190 191void 192TLB::flushMvaAsid(Addr mva, uint64_t asn) 193{ 194 DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn); 195 TlbEntry *te; 196 197 te = lookup(mva, asn); 198 while (te != NULL) { 199 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 200 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 201 te->valid = false; 202 te = lookup(mva,asn); 203 } 204} 205 206void 207TLB::flushAsid(uint64_t asn) 208{ 209 DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn); 210 211 int x = 0; 212 TlbEntry *te; 213 214 while (x < size) { 215 te = &table[x]; 216 if (te->asid == asn) { 217 te->valid = false; 218 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 219 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 220 } 221 x++; 222 } 223} 224 225void 226TLB::flushMva(Addr mva) 227{ 228 DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva); 229 230 int x = 0; 231 TlbEntry *te; 232 233 while (x < size) { 234 te = &table[x]; 235 Addr v = te->vpn << te->N; 236 if (mva >= v && mva < v + te->size) { 237 te->valid = false; 238 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 239 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 240 } 241 x++; 242 } 243} 244 245void 246TLB::serialize(ostream &os) 247{ 248 DPRINTF(Checkpoint, "Serializing Arm TLB\n"); 249 250 SERIALIZE_SCALAR(_attr); 251 for(int i = 0; i < size; i++){ 252 nameOut(os, csprintf("%s.TlbEntry%d", name(), i)); 253 table[i].serialize(os); 254 } 255} 256 257void 258TLB::unserialize(Checkpoint *cp, const string §ion) 259{ 260 DPRINTF(Checkpoint, "Unserializing Arm TLB\n"); 261 262 UNSERIALIZE_SCALAR(_attr); 263 for(int i = 0; i < size; i++){ 264 table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i)); 265 } 266} 267 268void 269TLB::regStats() 270{ 271 read_hits 272 .name(name() + ".read_hits") 273 .desc("DTB read hits") 274 ; 275 276 read_misses 277 .name(name() + ".read_misses") 278 .desc("DTB read misses") 279 ; 280 281 282 read_accesses 283 .name(name() + ".read_accesses") 284 .desc("DTB read accesses") 285 ; 286 287 write_hits 288 .name(name() + ".write_hits") 289 .desc("DTB write hits") 290 ; 291 292 write_misses 293 .name(name() + ".write_misses") 294 .desc("DTB write misses") 295 ; 296 297 298 write_accesses 299 .name(name() + ".write_accesses") 300 .desc("DTB write accesses") 301 ; 302 303 hits 304 .name(name() + ".hits") 305 .desc("DTB hits") 306 ; 307 308 misses 309 .name(name() + ".misses") 310 .desc("DTB misses") 311 ; 312 313 accesses 314 .name(name() + ".accesses") 315 .desc("DTB accesses") 316 ; 317 318 hits = read_hits + write_hits; 319 misses = read_misses + write_misses; 320 accesses = read_accesses + write_accesses; 321} 322 323#if !FULL_SYSTEM 324Fault 325TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 326 Translation *translation, bool &delay, bool timing) 327{ 328 // XXX Cache misc registers and have miscreg write function inv cache 329 Addr vaddr = req->getVaddr(); 330 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 331 uint32_t flags = req->getFlags(); 332 333 bool is_fetch = (mode == Execute); 334 bool is_write = (mode == Write); 335 336 if (!is_fetch) { 337 assert(flags & MustBeOne); 338 if (sctlr.a || !(flags & AllowUnaligned)) { 339 if (vaddr & flags & AlignmentMask) { 340 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 341 } 342 } 343 } 344 345 Addr paddr; 346 Process *p = tc->getProcessPtr(); 347 348 if (!p->pTable->translate(vaddr, paddr)) 349 return Fault(new GenericPageTableFault(vaddr)); 350 req->setPaddr(paddr); 351 352 return NoFault; 353} 354 355#else // FULL_SYSTEM 356 357Fault 358TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp) 359{ 360 return NoFault; 361} 362 363Fault 364TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec, 365 bool is_write, uint8_t domain, bool sNp) 366{ 367 return NoFault; 368} 369 370Fault 371TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 372 Translation *translation, bool &delay, bool timing) 373{ 374 // XXX Cache misc registers and have miscreg write function inv cache 375 Addr vaddr = req->getVaddr(); 376 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 377 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 378 uint32_t flags = req->getFlags(); 379 380 bool is_fetch = (mode == Execute); 381 bool is_write = (mode == Write); 382 bool is_priv = (cpsr.mode != MODE_USER) && !(flags & UserMode); 383 384 DPRINTF(TLBVerbose, "CPSR is user:%d UserMode:%d\n", cpsr.mode == MODE_USER, flags 385 & UserMode); 386 // If this is a clrex instruction, provide a PA of 0 with no fault 387 // This will force the monitor to set the tracked address to 0 388 // a bit of a hack but this effectively clrears this processors monitor 389 if (flags & Request::CLEAR_LL){ 390 req->setPaddr(0); 391 req->setFlags(Request::UNCACHEABLE); 392 req->setFlags(Request::CLEAR_LL); 393 return NoFault; 394 } 395 if ((req->isInstFetch() && (!sctlr.i)) || 396 ((!req->isInstFetch()) && (!sctlr.c))){ 397 req->setFlags(Request::UNCACHEABLE); 398 } 399 if (!is_fetch) { 400 assert(flags & MustBeOne); 401 if (sctlr.a || !(flags & AllowUnaligned)) { 402 if (vaddr & flags & AlignmentMask) { 403 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 404 } 405 } 406 } 407 408 uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR); 409 Fault fault; 410 411 412 if (!sctlr.m) { 413 req->setPaddr(vaddr); 414 if (sctlr.tre == 0) { 415 req->setFlags(Request::UNCACHEABLE); 416 } else { 417 PRRR prrr = tc->readMiscReg(MISCREG_PRRR); 418 NMRR nmrr = tc->readMiscReg(MISCREG_NMRR); 419 420 if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 421 req->setFlags(Request::UNCACHEABLE); 422 } 423 424 // Set memory attributes 425 TlbEntry temp_te; 426 tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1); 427 temp_te.shareable = true; 428 DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\ 429 %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable, 430 temp_te.innerAttrs, temp_te.outerAttrs); 431 setAttr(temp_te.attributes); 432 433 return trickBoxCheck(req, mode, 0, false); 434 } 435 436 DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, context_id); 437 // Translation enabled 438 439 TlbEntry *te = lookup(vaddr, context_id); 440 if (te == NULL) { 441 if (req->isPrefetch()){ 442 //if the request is a prefetch don't attempt to fill the TLB 443 //or go any further with the memory access 444 return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss); 445 } 446 // start translation table walk, pass variables rather than 447 // re-retreaving in table walker for speed 448 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n", 449 vaddr, context_id); 450 fault = tableWalker->walk(req, tc, context_id, mode, translation, 451 timing); 452 if (timing) { 453 delay = true; 454 // for timing mode, return and wait for table walk 455 return fault; 456 } 457 if (fault) 458 return fault; 459 460 te = lookup(vaddr, context_id); 461 if (!te) 462 printTlb(); 463 assert(te); 464 } 465 466 // Set memory attributes 467 DPRINTF(TLBVerbose, 468 "Setting memory attributes: shareable: %d, innerAttrs: %d, \ 469 outerAttrs: %d\n", 470 te->shareable, te->innerAttrs, te->outerAttrs); 471 setAttr(te->attributes); 472 if (te->nonCacheable) 473 req->setFlags(Request::UNCACHEABLE); 474 uint32_t dacr = tc->readMiscReg(MISCREG_DACR); 475 switch ( (dacr >> (te->domain * 2)) & 0x3) { 476 case 0: 477 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x" 478 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp); 479 if (is_fetch) 480 return new PrefetchAbort(vaddr, 481 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 482 else 483 return new DataAbort(vaddr, te->domain, is_write, 484 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 485 case 1: 486 // Continue with permissions check 487 break; 488 case 2: 489 panic("UNPRED domain\n"); 490 case 3: 491 req->setPaddr(te->pAddr(vaddr)); 492 fault = trickBoxCheck(req, mode, te->domain, te->sNp); 493 if (fault) 494 return fault; 495 return NoFault; 496 } 497 498 uint8_t ap = te->ap; 499 500 if (sctlr.afe == 1) 501 ap |= 1; 502 503 bool abt; 504 505 /* if (!sctlr.xp) 506 ap &= 0x3; 507*/ 508 switch (ap) { 509 case 0: 510 DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs); 511 if (!sctlr.xp) { 512 switch ((int)sctlr.rs) { 513 case 2: 514 abt = is_write; 515 break; 516 case 1: 517 abt = is_write || !is_priv; 518 break; 519 case 0: 520 case 3: 521 default: 522 abt = true; 523 break; 524 } 525 } else { 526 abt = true; 527 } 528 break; 529 case 1: 530 abt = !is_priv; 531 break; 532 case 2: 533 abt = !is_priv && is_write; 534 break; 535 case 3: 536 abt = false; 537 break; 538 case 4: 539 panic("UNPRED premissions\n"); 540 case 5: 541 abt = !is_priv || is_write; 542 break; 543 case 6: 544 case 7: 545 abt = is_write; 546 break; 547 default: 548 panic("Unknown permissions\n"); 549 } 550 if ((is_fetch) && (abt || te->xn)) { 551 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d" 552 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 553 return new PrefetchAbort(vaddr, 554 (te->sNp ? ArmFault::Permission0 : 555 ArmFault::Permission1)); 556 } else if (abt) { 557 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 558 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 559 return new DataAbort(vaddr, te->domain, is_write, 560 (te->sNp ? ArmFault::Permission0 : 561 ArmFault::Permission1)); 562 } 563 564 req->setPaddr(te->pAddr(vaddr)); 565 // Check for a trickbox generated address fault 566 fault = trickBoxCheck(req, mode, te->domain, te->sNp); 567 if (fault) 568 return fault; 569 570 return NoFault; 571} 572 573#endif 574 575Fault 576TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 577{ 578 bool delay = false; 579 Fault fault; 580#if FULL_SYSTEM 581 fault = translateFs(req, tc, mode, NULL, delay, false); 582#else 583 fault = translateSe(req, tc, mode, NULL, delay, false); 584#endif 585 assert(!delay); 586 return fault; 587} 588 589Fault 590TLB::translateTiming(RequestPtr req, ThreadContext *tc, 591 Translation *translation, Mode mode) 592{ 593 assert(translation); 594 bool delay = false; 595 Fault fault; 596#if FULL_SYSTEM 597 fault = translateFs(req, tc, mode, translation, delay, true); 598#else 599 fault = translateSe(req, tc, mode, translation, delay, true); 600#endif 601 if (!delay) 602 translation->finish(fault, req, tc, mode); 603 return fault; 604} 605 606ArmISA::TLB * 607ArmTLBParams::create() 608{ 609 return new ArmISA::TLB(this); 610} 611