tlb.cc revision 7697:05b1a077977b
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 *          Nathan Binkert
42 *          Steve Reinhardt
43 */
44
45#include <string>
46#include <vector>
47
48#include "arch/arm/faults.hh"
49#include "arch/arm/pagetable.hh"
50#include "arch/arm/tlb.hh"
51#include "arch/arm/utility.hh"
52#include "base/inifile.hh"
53#include "base/str.hh"
54#include "base/trace.hh"
55#include "cpu/thread_context.hh"
56#include "mem/page_table.hh"
57#include "params/ArmTLB.hh"
58#include "sim/process.hh"
59
60#if FULL_SYSTEM
61#include "arch/arm/table_walker.hh"
62#endif
63
64using namespace std;
65using namespace ArmISA;
66
67TLB::TLB(const Params *p)
68    : BaseTLB(p), size(p->size)
69#if FULL_SYSTEM
70      , tableWalker(p->walker)
71#endif
72    , rangeMRU(1)
73{
74    table = new TlbEntry[size];
75    memset(table, 0, sizeof(TlbEntry[size]));
76
77#if FULL_SYSTEM
78    tableWalker->setTlb(this);
79#endif
80}
81
82TLB::~TLB()
83{
84    if (table)
85        delete [] table;
86}
87
88bool
89TLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa)
90{
91    uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR);
92    TlbEntry *e = lookup(va, context_id, true);
93    if (!e)
94        return false;
95    pa = e->pAddr(va);
96    return true;
97}
98
99TlbEntry*
100TLB::lookup(Addr va, uint8_t cid, bool functional)
101{
102
103    TlbEntry *retval = NULL;
104
105    // Maitaining LRU array
106
107    int x = 0;
108    while (retval == NULL && x < size) {
109        if (table[x].match(va, cid)) {
110
111            // We only move the hit entry ahead when the position is higher than rangeMRU
112            if (x > rangeMRU) {
113                TlbEntry tmp_entry = table[x];
114                for(int i = x; i > 0; i--)
115                    table[i] = table[i-1];
116                table[0] = tmp_entry;
117                retval = &table[0];
118            } else {
119                retval = &table[x];
120            }
121            break;
122        }
123        x++;
124    }
125
126    DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n",
127            va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0,
128            retval ? retval->size : 0, retval ? retval->pAddr(va) : 0,
129            retval ? retval->ap : 0);
130    ;
131    return retval;
132}
133
134// insert a new TLB entry
135void
136TLB::insert(Addr addr, TlbEntry &entry)
137{
138    DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x"
139            " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x"
140            " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid,
141            entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp,
142            entry.xn, entry.ap, entry.domain);
143
144    if (table[size-1].valid)
145        DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n",
146                table[size-1].vpn << table[size-1].N, table[size-1].asid,
147                table[size-1].pfn << table[size-1].N, table[size-1].size,
148                table[size-1].ap);
149
150    //inserting to MRU position and evicting the LRU one
151
152    for(int i = size-1; i > 0; i--)
153      table[i] = table[i-1];
154    table[0] = entry;
155}
156
157void
158TLB::printTlb()
159{
160    int x = 0;
161    TlbEntry *te;
162    DPRINTF(TLB, "Current TLB contents:\n");
163    while (x < size) {
164       te = &table[x];
165       if (te->valid)
166           DPRINTF(TLB, " *  %#x, asn %d ppn %#x size: %#x ap:%d\n",
167                te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
168       x++;
169    }
170}
171
172
173void
174TLB::flushAll()
175{
176    DPRINTF(TLB, "Flushing all TLB entries\n");
177    int x = 0;
178    TlbEntry *te;
179    while (x < size) {
180       te = &table[x];
181       if (te->valid)
182           DPRINTF(TLB, " -  %#x, asn %d ppn %#x size: %#x ap:%d\n",
183                te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
184       x++;
185    }
186
187    memset(table, 0, sizeof(TlbEntry[size]));
188}
189
190
191void
192TLB::flushMvaAsid(Addr mva, uint64_t asn)
193{
194    DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn);
195    TlbEntry *te;
196
197    te = lookup(mva, asn);
198    while (te != NULL) {
199     DPRINTF(TLB, " -  %#x, asn %d ppn %#x size: %#x ap:%d\n",
200            te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
201        te->valid = false;
202        te = lookup(mva,asn);
203    }
204}
205
206void
207TLB::flushAsid(uint64_t asn)
208{
209    DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn);
210
211    int x = 0;
212    TlbEntry *te;
213
214    while (x < size) {
215        te = &table[x];
216        if (te->asid == asn) {
217            te->valid = false;
218            DPRINTF(TLB, " -  %#x, asn %d ppn %#x size: %#x ap:%d\n",
219                te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
220        }
221        x++;
222    }
223}
224
225void
226TLB::flushMva(Addr mva)
227{
228    DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva);
229
230    int x = 0;
231    TlbEntry *te;
232
233    while (x < size) {
234        te = &table[x];
235        Addr v = te->vpn << te->N;
236        if (mva >= v && mva < v + te->size) {
237            te->valid = false;
238            DPRINTF(TLB, " -  %#x, asn %d ppn %#x size: %#x ap:%d\n",
239                te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
240        }
241        x++;
242    }
243}
244
245void
246TLB::serialize(ostream &os)
247{
248    panic("Implement Serialize\n");
249}
250
251void
252TLB::unserialize(Checkpoint *cp, const string &section)
253{
254
255    panic("Need to properly unserialize TLB\n");
256}
257
258void
259TLB::regStats()
260{
261    read_hits
262        .name(name() + ".read_hits")
263        .desc("DTB read hits")
264        ;
265
266    read_misses
267        .name(name() + ".read_misses")
268        .desc("DTB read misses")
269        ;
270
271
272    read_accesses
273        .name(name() + ".read_accesses")
274        .desc("DTB read accesses")
275        ;
276
277    write_hits
278        .name(name() + ".write_hits")
279        .desc("DTB write hits")
280        ;
281
282    write_misses
283        .name(name() + ".write_misses")
284        .desc("DTB write misses")
285        ;
286
287
288    write_accesses
289        .name(name() + ".write_accesses")
290        .desc("DTB write accesses")
291        ;
292
293    hits
294        .name(name() + ".hits")
295        .desc("DTB hits")
296        ;
297
298    misses
299        .name(name() + ".misses")
300        .desc("DTB misses")
301        ;
302
303    accesses
304        .name(name() + ".accesses")
305        .desc("DTB accesses")
306        ;
307
308    hits = read_hits + write_hits;
309    misses = read_misses + write_misses;
310    accesses = read_accesses + write_accesses;
311}
312
313#if !FULL_SYSTEM
314Fault
315TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
316        Translation *translation, bool &delay, bool timing)
317{
318    // XXX Cache misc registers and have miscreg write function inv cache
319    Addr vaddr = req->getVaddr() & ~PcModeMask;
320    SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
321    uint32_t flags = req->getFlags();
322
323    bool is_fetch = (mode == Execute);
324    bool is_write = (mode == Write);
325
326    if (!is_fetch) {
327        assert(flags & MustBeOne);
328        if (sctlr.a || !(flags & AllowUnaligned)) {
329            if (vaddr & flags & AlignmentMask) {
330                return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
331            }
332        }
333    }
334
335    Addr paddr;
336    Process *p = tc->getProcessPtr();
337
338    if (!p->pTable->translate(vaddr, paddr))
339        return Fault(new GenericPageTableFault(vaddr));
340    req->setPaddr(paddr);
341
342    return NoFault;
343}
344
345#else // FULL_SYSTEM
346
347Fault
348TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp)
349{
350    return NoFault;
351}
352
353Fault
354TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
355        bool is_write, uint8_t domain, bool sNp)
356{
357    return NoFault;
358}
359
360Fault
361TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
362        Translation *translation, bool &delay, bool timing)
363{
364    // XXX Cache misc registers and have miscreg write function inv cache
365    Addr vaddr = req->getVaddr() & ~PcModeMask;
366    SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
367    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
368    uint32_t flags = req->getFlags();
369
370    bool is_fetch = (mode == Execute);
371    bool is_write = (mode == Write);
372    bool is_priv = (cpsr.mode != MODE_USER) && !(flags & UserMode);
373
374    DPRINTF(TLBVerbose, "CPSR is user:%d UserMode:%d\n", cpsr.mode == MODE_USER, flags
375            & UserMode);
376    // If this is a clrex instruction, provide a PA of 0 with no fault
377    // This will force the monitor to set the tracked address to 0
378    // a bit of a hack but this effectively clrears this processors monitor
379    if (flags & Request::CLREX){
380       req->setPaddr(0);
381       req->setFlags(Request::UNCACHEABLE);
382       req->setFlags(Request::CLREX);
383       return NoFault;
384    }
385    if ((req->isInstFetch() && (!sctlr.i)) ||
386        ((!req->isInstFetch()) && (!sctlr.c))){
387       req->setFlags(Request::UNCACHEABLE);
388    }
389    if (!is_fetch) {
390        assert(flags & MustBeOne);
391        if (sctlr.a || !(flags & AllowUnaligned)) {
392            if (vaddr & flags & AlignmentMask) {
393                return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
394            }
395        }
396    }
397
398    uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR);
399    Fault fault;
400
401
402    if (!sctlr.m) {
403        req->setPaddr(vaddr);
404        if (sctlr.tre == 0) {
405            req->setFlags(Request::UNCACHEABLE);
406        } else {
407            PRRR prrr = tc->readMiscReg(MISCREG_PRRR);
408            NMRR nmrr = tc->readMiscReg(MISCREG_NMRR);
409
410            if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2)
411               req->setFlags(Request::UNCACHEABLE);
412        }
413
414        // Set memory attributes
415        TlbEntry temp_te;
416        tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1);
417        temp_te.shareable = true;
418        DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\
419                %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable,
420                temp_te.innerAttrs, temp_te.outerAttrs);
421        setAttr(temp_te.attributes);
422
423        return trickBoxCheck(req, mode, 0, false);
424    }
425
426    DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, context_id);
427    // Translation enabled
428
429    TlbEntry *te = lookup(vaddr, context_id);
430    if (te == NULL) {
431        if (req->isPrefetch()){
432           //if the request is a prefetch don't attempt to fill the TLB
433           //or go any further with the memory access
434           return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss);
435        }
436        // start translation table walk, pass variables rather than
437        // re-retreaving in table walker for speed
438        DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n",
439                vaddr, context_id);
440        fault = tableWalker->walk(req, tc, context_id, mode, translation,
441                timing);
442        if (timing) {
443            delay = true;
444            // for timing mode, return and wait for table walk
445            return fault;
446        }
447        if (fault)
448            return fault;
449
450        te = lookup(vaddr, context_id);
451        if (!te)
452            printTlb();
453        assert(te);
454    }
455
456    // Set memory attributes
457    DPRINTF(TLBVerbose,
458            "Setting memory attributes: shareable: %d, innerAttrs: %d, \
459            outerAttrs: %d\n",
460            te->shareable, te->innerAttrs, te->outerAttrs);
461    setAttr(te->attributes);
462    if (te->nonCacheable)
463        req->setFlags(Request::UNCACHEABLE);
464    uint32_t dacr = tc->readMiscReg(MISCREG_DACR);
465    switch ( (dacr >> (te->domain * 2)) & 0x3) {
466      case 0:
467        DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x"
468               " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp);
469        if (is_fetch)
470            return new PrefetchAbort(vaddr,
471                (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
472        else
473            return new DataAbort(vaddr, te->domain, is_write,
474                (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
475      case 1:
476        // Continue with permissions check
477        break;
478      case 2:
479        panic("UNPRED domain\n");
480      case 3:
481        req->setPaddr(te->pAddr(vaddr));
482        fault = trickBoxCheck(req, mode, te->domain, te->sNp);
483        if (fault)
484            return fault;
485        return NoFault;
486    }
487
488    uint8_t ap = te->ap;
489
490    if (sctlr.afe == 1)
491        ap |= 1;
492
493    bool abt;
494
495   /* if (!sctlr.xp)
496        ap &= 0x3;
497*/
498    switch (ap) {
499      case 0:
500        DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs);
501        if (!sctlr.xp) {
502            switch ((int)sctlr.rs) {
503              case 2:
504                abt = is_write;
505                break;
506              case 1:
507                abt = is_write || !is_priv;
508                break;
509              case 0:
510              case 3:
511              default:
512                abt = true;
513                break;
514            }
515        } else {
516            abt = true;
517        }
518        break;
519      case 1:
520        abt = !is_priv;
521        break;
522      case 2:
523        abt = !is_priv && is_write;
524        break;
525      case 3:
526        abt = false;
527        break;
528      case 4:
529        panic("UNPRED premissions\n");
530      case 5:
531        abt = !is_priv || is_write;
532        break;
533      case 6:
534      case 7:
535        abt = is_write;
536        break;
537      default:
538        panic("Unknown permissions\n");
539    }
540    if ((is_fetch) && (abt || te->xn)) {
541        DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d"
542               " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
543        return new PrefetchAbort(vaddr,
544                (te->sNp ? ArmFault::Permission0 :
545                 ArmFault::Permission1));
546    } else if (abt) {
547        DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d"
548               " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
549        return new DataAbort(vaddr, te->domain, is_write,
550                (te->sNp ? ArmFault::Permission0 :
551                 ArmFault::Permission1));
552    }
553
554    req->setPaddr(te->pAddr(vaddr));
555    // Check for a trickbox generated address fault
556    fault = trickBoxCheck(req, mode, te->domain, te->sNp);
557    if (fault)
558        return fault;
559
560    return NoFault;
561}
562
563#endif
564
565Fault
566TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
567{
568    bool delay = false;
569    Fault fault;
570#if FULL_SYSTEM
571    fault = translateFs(req, tc, mode, NULL, delay, false);
572#else
573    fault = translateSe(req, tc, mode, NULL, delay, false);
574#endif
575    assert(!delay);
576    return fault;
577}
578
579Fault
580TLB::translateTiming(RequestPtr req, ThreadContext *tc,
581        Translation *translation, Mode mode)
582{
583    assert(translation);
584    bool delay = false;
585    Fault fault;
586#if FULL_SYSTEM
587    fault = translateFs(req, tc, mode, translation, delay, true);
588#else
589    fault = translateSe(req, tc, mode, translation, delay, true);
590#endif
591    if (!delay)
592        translation->finish(fault, req, tc, mode);
593    return fault;
594}
595
596ArmISA::TLB *
597ArmTLBParams::create()
598{
599    return new ArmISA::TLB(this);
600}
601