tlb.cc revision 10024:fc10e1f9f124
1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 * Nathan Binkert 42 * Steve Reinhardt 43 */ 44 45#include <string> 46#include <vector> 47 48#include "arch/arm/faults.hh" 49#include "arch/arm/pagetable.hh" 50#include "arch/arm/system.hh" 51#include "arch/arm/table_walker.hh" 52#include "arch/arm/tlb.hh" 53#include "arch/arm/utility.hh" 54#include "base/inifile.hh" 55#include "base/str.hh" 56#include "base/trace.hh" 57#include "cpu/base.hh" 58#include "cpu/thread_context.hh" 59#include "debug/Checkpoint.hh" 60#include "debug/TLB.hh" 61#include "debug/TLBVerbose.hh" 62#include "mem/page_table.hh" 63#include "params/ArmTLB.hh" 64#include "sim/full_system.hh" 65#include "sim/process.hh" 66 67using namespace std; 68using namespace ArmISA; 69 70TLB::TLB(const Params *p) 71 : BaseTLB(p), size(p->size) , tableWalker(p->walker), 72 rangeMRU(1), bootUncacheability(false), miscRegValid(false) 73{ 74 table = new TlbEntry[size]; 75 memset(table, 0, sizeof(TlbEntry) * size); 76 77 tableWalker->setTlb(this); 78} 79 80TLB::~TLB() 81{ 82 if (table) 83 delete [] table; 84} 85 86bool 87TLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa) 88{ 89 if (!miscRegValid) 90 updateMiscReg(tc); 91 TlbEntry *e = lookup(va, contextId, true); 92 if (!e) 93 return false; 94 pa = e->pAddr(va); 95 return true; 96} 97 98Fault 99TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const 100{ 101 return NoFault; 102} 103 104TlbEntry* 105TLB::lookup(Addr va, uint8_t cid, bool functional) 106{ 107 108 TlbEntry *retval = NULL; 109 110 // Maitaining LRU array 111 112 int x = 0; 113 while (retval == NULL && x < size) { 114 if (table[x].match(va, cid)) { 115 116 // We only move the hit entry ahead when the position is higher than rangeMRU 117 if (x > rangeMRU && !functional) { 118 TlbEntry tmp_entry = table[x]; 119 for(int i = x; i > 0; i--) 120 table[i] = table[i-1]; 121 table[0] = tmp_entry; 122 retval = &table[0]; 123 } else { 124 retval = &table[x]; 125 } 126 break; 127 } 128 x++; 129 } 130 131 DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n", 132 va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0, 133 retval ? retval->size : 0, retval ? retval->pAddr(va) : 0, 134 retval ? retval->ap : 0); 135 ; 136 return retval; 137} 138 139// insert a new TLB entry 140void 141TLB::insert(Addr addr, TlbEntry &entry) 142{ 143 DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x" 144 " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x" 145 " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid, 146 entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp, 147 entry.xn, entry.ap, entry.domain); 148 149 if (table[size-1].valid) 150 DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n", 151 table[size-1].vpn << table[size-1].N, table[size-1].asid, 152 table[size-1].pfn << table[size-1].N, table[size-1].size, 153 table[size-1].ap); 154 155 //inserting to MRU position and evicting the LRU one 156 157 for(int i = size-1; i > 0; i--) 158 table[i] = table[i-1]; 159 table[0] = entry; 160 161 inserts++; 162} 163 164void 165TLB::printTlb() 166{ 167 int x = 0; 168 TlbEntry *te; 169 DPRINTF(TLB, "Current TLB contents:\n"); 170 while (x < size) { 171 te = &table[x]; 172 if (te->valid) 173 DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n", 174 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 175 x++; 176 } 177} 178 179 180void 181TLB::flushAll() 182{ 183 DPRINTF(TLB, "Flushing all TLB entries\n"); 184 int x = 0; 185 TlbEntry *te; 186 while (x < size) { 187 te = &table[x]; 188 if (te->valid) { 189 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 190 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 191 flushedEntries++; 192 } 193 x++; 194 } 195 196 memset(table, 0, sizeof(TlbEntry) * size); 197 198 flushTlb++; 199} 200 201 202void 203TLB::flushMvaAsid(Addr mva, uint64_t asn) 204{ 205 DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn); 206 TlbEntry *te; 207 208 te = lookup(mva, asn); 209 while (te != NULL) { 210 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 211 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 212 te->valid = false; 213 flushedEntries++; 214 te = lookup(mva,asn); 215 } 216 flushTlbMvaAsid++; 217} 218 219void 220TLB::flushAsid(uint64_t asn) 221{ 222 DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn); 223 224 int x = 0; 225 TlbEntry *te; 226 227 while (x < size) { 228 te = &table[x]; 229 if (te->asid == asn) { 230 te->valid = false; 231 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 232 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 233 flushedEntries++; 234 } 235 x++; 236 } 237 flushTlbAsid++; 238} 239 240void 241TLB::flushMva(Addr mva) 242{ 243 DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva); 244 245 int x = 0; 246 TlbEntry *te; 247 248 while (x < size) { 249 te = &table[x]; 250 Addr v = te->vpn << te->N; 251 if (mva >= v && mva < v + te->size) { 252 te->valid = false; 253 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 254 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 255 flushedEntries++; 256 } 257 x++; 258 } 259 flushTlbMva++; 260} 261 262void 263TLB::drainResume() 264{ 265 // We might have unserialized something or switched CPUs, so make 266 // sure to re-read the misc regs. 267 miscRegValid = false; 268} 269 270void 271TLB::serialize(ostream &os) 272{ 273 DPRINTF(Checkpoint, "Serializing Arm TLB\n"); 274 275 SERIALIZE_SCALAR(_attr); 276 277 int num_entries = size; 278 SERIALIZE_SCALAR(num_entries); 279 for(int i = 0; i < size; i++){ 280 nameOut(os, csprintf("%s.TlbEntry%d", name(), i)); 281 table[i].serialize(os); 282 } 283} 284 285void 286TLB::unserialize(Checkpoint *cp, const string §ion) 287{ 288 DPRINTF(Checkpoint, "Unserializing Arm TLB\n"); 289 290 UNSERIALIZE_SCALAR(_attr); 291 int num_entries; 292 UNSERIALIZE_SCALAR(num_entries); 293 for(int i = 0; i < min(size, num_entries); i++){ 294 table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i)); 295 } 296} 297 298void 299TLB::regStats() 300{ 301 instHits 302 .name(name() + ".inst_hits") 303 .desc("ITB inst hits") 304 ; 305 306 instMisses 307 .name(name() + ".inst_misses") 308 .desc("ITB inst misses") 309 ; 310 311 instAccesses 312 .name(name() + ".inst_accesses") 313 .desc("ITB inst accesses") 314 ; 315 316 readHits 317 .name(name() + ".read_hits") 318 .desc("DTB read hits") 319 ; 320 321 readMisses 322 .name(name() + ".read_misses") 323 .desc("DTB read misses") 324 ; 325 326 readAccesses 327 .name(name() + ".read_accesses") 328 .desc("DTB read accesses") 329 ; 330 331 writeHits 332 .name(name() + ".write_hits") 333 .desc("DTB write hits") 334 ; 335 336 writeMisses 337 .name(name() + ".write_misses") 338 .desc("DTB write misses") 339 ; 340 341 writeAccesses 342 .name(name() + ".write_accesses") 343 .desc("DTB write accesses") 344 ; 345 346 hits 347 .name(name() + ".hits") 348 .desc("DTB hits") 349 ; 350 351 misses 352 .name(name() + ".misses") 353 .desc("DTB misses") 354 ; 355 356 accesses 357 .name(name() + ".accesses") 358 .desc("DTB accesses") 359 ; 360 361 flushTlb 362 .name(name() + ".flush_tlb") 363 .desc("Number of times complete TLB was flushed") 364 ; 365 366 flushTlbMva 367 .name(name() + ".flush_tlb_mva") 368 .desc("Number of times TLB was flushed by MVA") 369 ; 370 371 flushTlbMvaAsid 372 .name(name() + ".flush_tlb_mva_asid") 373 .desc("Number of times TLB was flushed by MVA & ASID") 374 ; 375 376 flushTlbAsid 377 .name(name() + ".flush_tlb_asid") 378 .desc("Number of times TLB was flushed by ASID") 379 ; 380 381 flushedEntries 382 .name(name() + ".flush_entries") 383 .desc("Number of entries that have been flushed from TLB") 384 ; 385 386 alignFaults 387 .name(name() + ".align_faults") 388 .desc("Number of TLB faults due to alignment restrictions") 389 ; 390 391 prefetchFaults 392 .name(name() + ".prefetch_faults") 393 .desc("Number of TLB faults due to prefetch") 394 ; 395 396 domainFaults 397 .name(name() + ".domain_faults") 398 .desc("Number of TLB faults due to domain restrictions") 399 ; 400 401 permsFaults 402 .name(name() + ".perms_faults") 403 .desc("Number of TLB faults due to permissions restrictions") 404 ; 405 406 instAccesses = instHits + instMisses; 407 readAccesses = readHits + readMisses; 408 writeAccesses = writeHits + writeMisses; 409 hits = readHits + writeHits + instHits; 410 misses = readMisses + writeMisses + instMisses; 411 accesses = readAccesses + writeAccesses + instAccesses; 412} 413 414Fault 415TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 416 Translation *translation, bool &delay, bool timing) 417{ 418 if (!miscRegValid) 419 updateMiscReg(tc); 420 Addr vaddr = req->getVaddr(); 421 uint32_t flags = req->getFlags(); 422 423 bool is_fetch = (mode == Execute); 424 bool is_write = (mode == Write); 425 426 if (!is_fetch) { 427 assert(flags & MustBeOne); 428 if (sctlr.a || !(flags & AllowUnaligned)) { 429 if (vaddr & flags & AlignmentMask) { 430 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 431 } 432 } 433 } 434 435 Addr paddr; 436 Process *p = tc->getProcessPtr(); 437 438 if (!p->pTable->translate(vaddr, paddr)) 439 return Fault(new GenericPageTableFault(vaddr)); 440 req->setPaddr(paddr); 441 442 return NoFault; 443} 444 445Fault 446TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp) 447{ 448 return NoFault; 449} 450 451Fault 452TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec, 453 bool is_write, uint8_t domain, bool sNp) 454{ 455 return NoFault; 456} 457 458Fault 459TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 460 Translation *translation, bool &delay, bool timing, bool functional) 461{ 462 // No such thing as a functional timing access 463 assert(!(timing && functional)); 464 465 if (!miscRegValid) { 466 updateMiscReg(tc); 467 DPRINTF(TLBVerbose, "TLB variables changed!\n"); 468 } 469 470 Addr vaddr = req->getVaddr(); 471 uint32_t flags = req->getFlags(); 472 473 bool is_fetch = (mode == Execute); 474 bool is_write = (mode == Write); 475 bool is_priv = isPriv && !(flags & UserMode); 476 477 req->setAsid(contextId.asid); 478 if (is_priv) 479 req->setFlags(Request::PRIVILEGED); 480 481 req->taskId(tc->getCpuPtr()->taskId()); 482 483 DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n", 484 isPriv, flags & UserMode); 485 // If this is a clrex instruction, provide a PA of 0 with no fault 486 // This will force the monitor to set the tracked address to 0 487 // a bit of a hack but this effectively clrears this processors monitor 488 if (flags & Request::CLEAR_LL){ 489 req->setPaddr(0); 490 req->setFlags(Request::UNCACHEABLE); 491 req->setFlags(Request::CLEAR_LL); 492 return NoFault; 493 } 494 if ((req->isInstFetch() && (!sctlr.i)) || 495 ((!req->isInstFetch()) && (!sctlr.c))){ 496 req->setFlags(Request::UNCACHEABLE); 497 } 498 if (!is_fetch) { 499 assert(flags & MustBeOne); 500 if (sctlr.a || !(flags & AllowUnaligned)) { 501 if (vaddr & flags & AlignmentMask) { 502 alignFaults++; 503 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 504 } 505 } 506 } 507 508 Fault fault; 509 510 if (!sctlr.m) { 511 req->setPaddr(vaddr); 512 if (sctlr.tre == 0) { 513 req->setFlags(Request::UNCACHEABLE); 514 } else { 515 if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 516 req->setFlags(Request::UNCACHEABLE); 517 } 518 519 // Set memory attributes 520 TlbEntry temp_te; 521 tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1); 522 temp_te.shareable = true; 523 DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\ 524 %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable, 525 temp_te.innerAttrs, temp_te.outerAttrs); 526 setAttr(temp_te.attributes); 527 528 return trickBoxCheck(req, mode, 0, false); 529 } 530 531 DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, contextId); 532 // Translation enabled 533 534 TlbEntry *te = lookup(vaddr, contextId); 535 if (te == NULL) { 536 if (req->isPrefetch()){ 537 //if the request is a prefetch don't attempt to fill the TLB 538 //or go any further with the memory access 539 prefetchFaults++; 540 return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss); 541 } 542 543 if (is_fetch) 544 instMisses++; 545 else if (is_write) 546 writeMisses++; 547 else 548 readMisses++; 549 550 // start translation table walk, pass variables rather than 551 // re-retreaving in table walker for speed 552 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n", 553 vaddr, contextId); 554 fault = tableWalker->walk(req, tc, contextId, mode, translation, 555 timing, functional); 556 if (timing && fault == NoFault) { 557 delay = true; 558 // for timing mode, return and wait for table walk 559 return fault; 560 } 561 if (fault) 562 return fault; 563 564 te = lookup(vaddr, contextId); 565 if (!te) 566 printTlb(); 567 assert(te); 568 } else { 569 if (is_fetch) 570 instHits++; 571 else if (is_write) 572 writeHits++; 573 else 574 readHits++; 575 } 576 577 // Set memory attributes 578 DPRINTF(TLBVerbose, 579 "Setting memory attributes: shareable: %d, innerAttrs: %d, \ 580 outerAttrs: %d\n", 581 te->shareable, te->innerAttrs, te->outerAttrs); 582 setAttr(te->attributes); 583 if (te->nonCacheable) { 584 req->setFlags(Request::UNCACHEABLE); 585 586 // Prevent prefetching from I/O devices. 587 if (req->isPrefetch()) { 588 return new PrefetchAbort(vaddr, ArmFault::PrefetchUncacheable); 589 } 590 } 591 592 if (!bootUncacheability && 593 ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr)) 594 req->setFlags(Request::UNCACHEABLE); 595 596 switch ( (dacr >> (te->domain * 2)) & 0x3) { 597 case 0: 598 domainFaults++; 599 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x" 600 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp); 601 if (is_fetch) 602 return new PrefetchAbort(vaddr, 603 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 604 else 605 return new DataAbort(vaddr, te->domain, is_write, 606 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 607 case 1: 608 // Continue with permissions check 609 break; 610 case 2: 611 panic("UNPRED domain\n"); 612 case 3: 613 req->setPaddr(te->pAddr(vaddr)); 614 fault = trickBoxCheck(req, mode, te->domain, te->sNp); 615 if (fault) 616 return fault; 617 return NoFault; 618 } 619 620 uint8_t ap = te->ap; 621 622 if (sctlr.afe == 1) 623 ap |= 1; 624 625 bool abt; 626 627 /* if (!sctlr.xp) 628 ap &= 0x3; 629*/ 630 switch (ap) { 631 case 0: 632 DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs); 633 if (!sctlr.xp) { 634 switch ((int)sctlr.rs) { 635 case 2: 636 abt = is_write; 637 break; 638 case 1: 639 abt = is_write || !is_priv; 640 break; 641 case 0: 642 case 3: 643 default: 644 abt = true; 645 break; 646 } 647 } else { 648 abt = true; 649 } 650 break; 651 case 1: 652 abt = !is_priv; 653 break; 654 case 2: 655 abt = !is_priv && is_write; 656 break; 657 case 3: 658 abt = false; 659 break; 660 case 4: 661 panic("UNPRED premissions\n"); 662 case 5: 663 abt = !is_priv || is_write; 664 break; 665 case 6: 666 case 7: 667 abt = is_write; 668 break; 669 default: 670 panic("Unknown permissions\n"); 671 } 672 if ((is_fetch) && (abt || te->xn)) { 673 permsFaults++; 674 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d" 675 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 676 return new PrefetchAbort(vaddr, 677 (te->sNp ? ArmFault::Permission0 : 678 ArmFault::Permission1)); 679 } else if (abt) { 680 permsFaults++; 681 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 682 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 683 return new DataAbort(vaddr, te->domain, is_write, 684 (te->sNp ? ArmFault::Permission0 : 685 ArmFault::Permission1)); 686 } 687 688 req->setPaddr(te->pAddr(vaddr)); 689 // Check for a trickbox generated address fault 690 fault = trickBoxCheck(req, mode, te->domain, te->sNp); 691 if (fault) 692 return fault; 693 694 return NoFault; 695} 696 697Fault 698TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 699{ 700 bool delay = false; 701 Fault fault; 702 if (FullSystem) 703 fault = translateFs(req, tc, mode, NULL, delay, false); 704 else 705 fault = translateSe(req, tc, mode, NULL, delay, false); 706 assert(!delay); 707 return fault; 708} 709 710Fault 711TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) 712{ 713 bool delay = false; 714 Fault fault; 715 if (FullSystem) 716 fault = translateFs(req, tc, mode, NULL, delay, false, true); 717 else 718 fault = translateSe(req, tc, mode, NULL, delay, false); 719 assert(!delay); 720 return fault; 721} 722 723Fault 724TLB::translateTiming(RequestPtr req, ThreadContext *tc, 725 Translation *translation, Mode mode) 726{ 727 assert(translation); 728 bool delay = false; 729 Fault fault; 730 if (FullSystem) 731 fault = translateFs(req, tc, mode, translation, delay, true); 732 else 733 fault = translateSe(req, tc, mode, translation, delay, true); 734 DPRINTF(TLBVerbose, "Translation returning delay=%d fault=%d\n", delay, fault != 735 NoFault); 736 if (!delay) 737 translation->finish(fault, req, tc, mode); 738 else 739 translation->markDelayed(); 740 return fault; 741} 742 743BaseMasterPort* 744TLB::getMasterPort() 745{ 746 return &tableWalker->getMasterPort("port"); 747} 748 749 750 751ArmISA::TLB * 752ArmTLBParams::create() 753{ 754 return new ArmISA::TLB(this); 755} 756