tlb.cc revision 8733
16019Shines@cs.fsu.edu/* 27093Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * All rights reserved. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 266019Shines@cs.fsu.edu * this software without specific prior written permission. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019Shines@cs.fsu.edu * 407399SAli.Saidi@ARM.com * Authors: Ali Saidi 417399SAli.Saidi@ARM.com * Nathan Binkert 426019Shines@cs.fsu.edu * Steve Reinhardt 436019Shines@cs.fsu.edu */ 446019Shines@cs.fsu.edu 456019Shines@cs.fsu.edu#include <string> 466019Shines@cs.fsu.edu#include <vector> 476019Shines@cs.fsu.edu 486116Snate@binkert.org#include "arch/arm/faults.hh" 496019Shines@cs.fsu.edu#include "arch/arm/pagetable.hh" 506019Shines@cs.fsu.edu#include "arch/arm/tlb.hh" 516019Shines@cs.fsu.edu#include "arch/arm/utility.hh" 526019Shines@cs.fsu.edu#include "base/inifile.hh" 536019Shines@cs.fsu.edu#include "base/str.hh" 546019Shines@cs.fsu.edu#include "base/trace.hh" 556019Shines@cs.fsu.edu#include "cpu/thread_context.hh" 568232Snate@binkert.org#include "debug/Checkpoint.hh" 578232Snate@binkert.org#include "debug/TLB.hh" 588232Snate@binkert.org#include "debug/TLBVerbose.hh" 596116Snate@binkert.org#include "mem/page_table.hh" 606116Snate@binkert.org#include "params/ArmTLB.hh" 616019Shines@cs.fsu.edu#include "sim/process.hh" 626019Shines@cs.fsu.edu 637406SAli.Saidi@ARM.com#if FULL_SYSTEM 648527SAli.Saidi@ARM.com#include "arch/arm/system.hh" 657406SAli.Saidi@ARM.com#include "arch/arm/table_walker.hh" 667406SAli.Saidi@ARM.com#endif 677406SAli.Saidi@ARM.com 686019Shines@cs.fsu.eduusing namespace std; 696019Shines@cs.fsu.eduusing namespace ArmISA; 706019Shines@cs.fsu.edu 716019Shines@cs.fsu.eduTLB::TLB(const Params *p) 727697SAli.Saidi@ARM.com : BaseTLB(p), size(p->size) 737404SAli.Saidi@ARM.com#if FULL_SYSTEM 747404SAli.Saidi@ARM.com , tableWalker(p->walker) 757404SAli.Saidi@ARM.com#endif 768527SAli.Saidi@ARM.com , rangeMRU(1), bootUncacheability(false), miscRegValid(false) 776019Shines@cs.fsu.edu{ 787404SAli.Saidi@ARM.com table = new TlbEntry[size]; 798352SChander.Sudanthi@ARM.com memset(table, 0, sizeof(TlbEntry) * size); 807399SAli.Saidi@ARM.com 817406SAli.Saidi@ARM.com#if FULL_SYSTEM 827404SAli.Saidi@ARM.com tableWalker->setTlb(this); 837406SAli.Saidi@ARM.com#endif 846019Shines@cs.fsu.edu} 856019Shines@cs.fsu.edu 866019Shines@cs.fsu.eduTLB::~TLB() 876019Shines@cs.fsu.edu{ 886019Shines@cs.fsu.edu if (table) 896019Shines@cs.fsu.edu delete [] table; 906019Shines@cs.fsu.edu} 916019Shines@cs.fsu.edu 927694SAli.Saidi@ARM.combool 937694SAli.Saidi@ARM.comTLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa) 947694SAli.Saidi@ARM.com{ 957749SAli.Saidi@ARM.com if (!miscRegValid) 967749SAli.Saidi@ARM.com updateMiscReg(tc); 977749SAli.Saidi@ARM.com TlbEntry *e = lookup(va, contextId, true); 987694SAli.Saidi@ARM.com if (!e) 997694SAli.Saidi@ARM.com return false; 1007694SAli.Saidi@ARM.com pa = e->pAddr(va); 1017694SAli.Saidi@ARM.com return true; 1027694SAli.Saidi@ARM.com} 1037694SAli.Saidi@ARM.com 1047404SAli.Saidi@ARM.comTlbEntry* 1057694SAli.Saidi@ARM.comTLB::lookup(Addr va, uint8_t cid, bool functional) 1066019Shines@cs.fsu.edu{ 1077404SAli.Saidi@ARM.com 1087404SAli.Saidi@ARM.com TlbEntry *retval = NULL; 1097404SAli.Saidi@ARM.com 1107697SAli.Saidi@ARM.com // Maitaining LRU array 1117404SAli.Saidi@ARM.com 1127404SAli.Saidi@ARM.com int x = 0; 1137404SAli.Saidi@ARM.com while (retval == NULL && x < size) { 1147404SAli.Saidi@ARM.com if (table[x].match(va, cid)) { 1157404SAli.Saidi@ARM.com 1167697SAli.Saidi@ARM.com // We only move the hit entry ahead when the position is higher than rangeMRU 1177697SAli.Saidi@ARM.com if (x > rangeMRU) { 1187697SAli.Saidi@ARM.com TlbEntry tmp_entry = table[x]; 1197697SAli.Saidi@ARM.com for(int i = x; i > 0; i--) 1207697SAli.Saidi@ARM.com table[i] = table[i-1]; 1217697SAli.Saidi@ARM.com table[0] = tmp_entry; 1227697SAli.Saidi@ARM.com retval = &table[0]; 1237697SAli.Saidi@ARM.com } else { 1247697SAli.Saidi@ARM.com retval = &table[x]; 1257697SAli.Saidi@ARM.com } 1267404SAli.Saidi@ARM.com break; 1277404SAli.Saidi@ARM.com } 1287404SAli.Saidi@ARM.com x++; 1297404SAli.Saidi@ARM.com } 1307404SAli.Saidi@ARM.com 1317404SAli.Saidi@ARM.com DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n", 1327404SAli.Saidi@ARM.com va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0, 1337404SAli.Saidi@ARM.com retval ? retval->size : 0, retval ? retval->pAddr(va) : 0, 1347404SAli.Saidi@ARM.com retval ? retval->ap : 0); 1357404SAli.Saidi@ARM.com ; 1367404SAli.Saidi@ARM.com return retval; 1376019Shines@cs.fsu.edu} 1386019Shines@cs.fsu.edu 1396019Shines@cs.fsu.edu// insert a new TLB entry 1406019Shines@cs.fsu.eduvoid 1417404SAli.Saidi@ARM.comTLB::insert(Addr addr, TlbEntry &entry) 1426019Shines@cs.fsu.edu{ 1437404SAli.Saidi@ARM.com DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x" 1447404SAli.Saidi@ARM.com " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x" 1457404SAli.Saidi@ARM.com " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid, 1467404SAli.Saidi@ARM.com entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp, 1477404SAli.Saidi@ARM.com entry.xn, entry.ap, entry.domain); 1487404SAli.Saidi@ARM.com 1497697SAli.Saidi@ARM.com if (table[size-1].valid) 1507404SAli.Saidi@ARM.com DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n", 1517697SAli.Saidi@ARM.com table[size-1].vpn << table[size-1].N, table[size-1].asid, 1527697SAli.Saidi@ARM.com table[size-1].pfn << table[size-1].N, table[size-1].size, 1537697SAli.Saidi@ARM.com table[size-1].ap); 1547404SAli.Saidi@ARM.com 1557697SAli.Saidi@ARM.com //inserting to MRU position and evicting the LRU one 1567404SAli.Saidi@ARM.com 1577697SAli.Saidi@ARM.com for(int i = size-1; i > 0; i--) 1587697SAli.Saidi@ARM.com table[i] = table[i-1]; 1597697SAli.Saidi@ARM.com table[0] = entry; 1607734SAli.Saidi@ARM.com 1617734SAli.Saidi@ARM.com inserts++; 1626019Shines@cs.fsu.edu} 1636019Shines@cs.fsu.edu 1646019Shines@cs.fsu.eduvoid 1657404SAli.Saidi@ARM.comTLB::printTlb() 1667404SAli.Saidi@ARM.com{ 1677404SAli.Saidi@ARM.com int x = 0; 1687404SAli.Saidi@ARM.com TlbEntry *te; 1697404SAli.Saidi@ARM.com DPRINTF(TLB, "Current TLB contents:\n"); 1707404SAli.Saidi@ARM.com while (x < size) { 1717404SAli.Saidi@ARM.com te = &table[x]; 1727404SAli.Saidi@ARM.com if (te->valid) 1737404SAli.Saidi@ARM.com DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n", 1747404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 1757404SAli.Saidi@ARM.com x++; 1767404SAli.Saidi@ARM.com } 1777404SAli.Saidi@ARM.com} 1787404SAli.Saidi@ARM.com 1797404SAli.Saidi@ARM.com 1807404SAli.Saidi@ARM.comvoid 1816019Shines@cs.fsu.eduTLB::flushAll() 1826019Shines@cs.fsu.edu{ 1837404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing all TLB entries\n"); 1847404SAli.Saidi@ARM.com int x = 0; 1857404SAli.Saidi@ARM.com TlbEntry *te; 1867404SAli.Saidi@ARM.com while (x < size) { 1877404SAli.Saidi@ARM.com te = &table[x]; 1887734SAli.Saidi@ARM.com if (te->valid) { 1897404SAli.Saidi@ARM.com DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 1907404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 1917734SAli.Saidi@ARM.com flushedEntries++; 1927734SAli.Saidi@ARM.com } 1937404SAli.Saidi@ARM.com x++; 1947404SAli.Saidi@ARM.com } 1957404SAli.Saidi@ARM.com 1968352SChander.Sudanthi@ARM.com memset(table, 0, sizeof(TlbEntry) * size); 1977734SAli.Saidi@ARM.com 1987734SAli.Saidi@ARM.com flushTlb++; 1996019Shines@cs.fsu.edu} 2006019Shines@cs.fsu.edu 2017404SAli.Saidi@ARM.com 2027404SAli.Saidi@ARM.comvoid 2037404SAli.Saidi@ARM.comTLB::flushMvaAsid(Addr mva, uint64_t asn) 2047404SAli.Saidi@ARM.com{ 2057404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn); 2067404SAli.Saidi@ARM.com TlbEntry *te; 2077404SAli.Saidi@ARM.com 2087404SAli.Saidi@ARM.com te = lookup(mva, asn); 2097404SAli.Saidi@ARM.com while (te != NULL) { 2107404SAli.Saidi@ARM.com DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 2117404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 2127404SAli.Saidi@ARM.com te->valid = false; 2137734SAli.Saidi@ARM.com flushedEntries++; 2147404SAli.Saidi@ARM.com te = lookup(mva,asn); 2157404SAli.Saidi@ARM.com } 2167734SAli.Saidi@ARM.com flushTlbMvaAsid++; 2177404SAli.Saidi@ARM.com} 2187404SAli.Saidi@ARM.com 2197404SAli.Saidi@ARM.comvoid 2207404SAli.Saidi@ARM.comTLB::flushAsid(uint64_t asn) 2217404SAli.Saidi@ARM.com{ 2227404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn); 2237404SAli.Saidi@ARM.com 2247404SAli.Saidi@ARM.com int x = 0; 2257404SAli.Saidi@ARM.com TlbEntry *te; 2267404SAli.Saidi@ARM.com 2277404SAli.Saidi@ARM.com while (x < size) { 2287404SAli.Saidi@ARM.com te = &table[x]; 2297404SAli.Saidi@ARM.com if (te->asid == asn) { 2307404SAli.Saidi@ARM.com te->valid = false; 2317404SAli.Saidi@ARM.com DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 2327404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 2337734SAli.Saidi@ARM.com flushedEntries++; 2347404SAli.Saidi@ARM.com } 2357404SAli.Saidi@ARM.com x++; 2367404SAli.Saidi@ARM.com } 2377734SAli.Saidi@ARM.com flushTlbAsid++; 2387404SAli.Saidi@ARM.com} 2397404SAli.Saidi@ARM.com 2407404SAli.Saidi@ARM.comvoid 2417404SAli.Saidi@ARM.comTLB::flushMva(Addr mva) 2427404SAli.Saidi@ARM.com{ 2437404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva); 2447404SAli.Saidi@ARM.com 2457404SAli.Saidi@ARM.com int x = 0; 2467404SAli.Saidi@ARM.com TlbEntry *te; 2477404SAli.Saidi@ARM.com 2487404SAli.Saidi@ARM.com while (x < size) { 2497404SAli.Saidi@ARM.com te = &table[x]; 2507404SAli.Saidi@ARM.com Addr v = te->vpn << te->N; 2517404SAli.Saidi@ARM.com if (mva >= v && mva < v + te->size) { 2527404SAli.Saidi@ARM.com te->valid = false; 2537404SAli.Saidi@ARM.com DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 2547404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 2557734SAli.Saidi@ARM.com flushedEntries++; 2567404SAli.Saidi@ARM.com } 2577404SAli.Saidi@ARM.com x++; 2587404SAli.Saidi@ARM.com } 2597734SAli.Saidi@ARM.com flushTlbMva++; 2607404SAli.Saidi@ARM.com} 2617404SAli.Saidi@ARM.com 2626019Shines@cs.fsu.eduvoid 2636019Shines@cs.fsu.eduTLB::serialize(ostream &os) 2646019Shines@cs.fsu.edu{ 2657733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Serializing Arm TLB\n"); 2667733SAli.Saidi@ARM.com 2677733SAli.Saidi@ARM.com SERIALIZE_SCALAR(_attr); 2688353SAli.Saidi@ARM.com 2698353SAli.Saidi@ARM.com int num_entries = size; 2708353SAli.Saidi@ARM.com SERIALIZE_SCALAR(num_entries); 2717733SAli.Saidi@ARM.com for(int i = 0; i < size; i++){ 2727733SAli.Saidi@ARM.com nameOut(os, csprintf("%s.TlbEntry%d", name(), i)); 2737733SAli.Saidi@ARM.com table[i].serialize(os); 2747733SAli.Saidi@ARM.com } 2756019Shines@cs.fsu.edu} 2766019Shines@cs.fsu.edu 2776019Shines@cs.fsu.eduvoid 2786019Shines@cs.fsu.eduTLB::unserialize(Checkpoint *cp, const string §ion) 2796019Shines@cs.fsu.edu{ 2807733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Unserializing Arm TLB\n"); 2816019Shines@cs.fsu.edu 2827733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(_attr); 2838353SAli.Saidi@ARM.com int num_entries; 2848353SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(num_entries); 2858353SAli.Saidi@ARM.com for(int i = 0; i < min(size, num_entries); i++){ 2867733SAli.Saidi@ARM.com table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i)); 2877733SAli.Saidi@ARM.com } 2887749SAli.Saidi@ARM.com miscRegValid = false; 2896019Shines@cs.fsu.edu} 2906019Shines@cs.fsu.edu 2916019Shines@cs.fsu.eduvoid 2926019Shines@cs.fsu.eduTLB::regStats() 2936019Shines@cs.fsu.edu{ 2947734SAli.Saidi@ARM.com instHits 2957734SAli.Saidi@ARM.com .name(name() + ".inst_hits") 2967734SAli.Saidi@ARM.com .desc("ITB inst hits") 2977734SAli.Saidi@ARM.com ; 2987734SAli.Saidi@ARM.com 2997734SAli.Saidi@ARM.com instMisses 3007734SAli.Saidi@ARM.com .name(name() + ".inst_misses") 3017734SAli.Saidi@ARM.com .desc("ITB inst misses") 3027734SAli.Saidi@ARM.com ; 3037734SAli.Saidi@ARM.com 3047734SAli.Saidi@ARM.com instAccesses 3057734SAli.Saidi@ARM.com .name(name() + ".inst_accesses") 3067734SAli.Saidi@ARM.com .desc("ITB inst accesses") 3077734SAli.Saidi@ARM.com ; 3087734SAli.Saidi@ARM.com 3097734SAli.Saidi@ARM.com readHits 3106019Shines@cs.fsu.edu .name(name() + ".read_hits") 3116019Shines@cs.fsu.edu .desc("DTB read hits") 3126019Shines@cs.fsu.edu ; 3136019Shines@cs.fsu.edu 3147734SAli.Saidi@ARM.com readMisses 3156019Shines@cs.fsu.edu .name(name() + ".read_misses") 3166019Shines@cs.fsu.edu .desc("DTB read misses") 3176019Shines@cs.fsu.edu ; 3186019Shines@cs.fsu.edu 3197734SAli.Saidi@ARM.com readAccesses 3206019Shines@cs.fsu.edu .name(name() + ".read_accesses") 3216019Shines@cs.fsu.edu .desc("DTB read accesses") 3226019Shines@cs.fsu.edu ; 3236019Shines@cs.fsu.edu 3247734SAli.Saidi@ARM.com writeHits 3256019Shines@cs.fsu.edu .name(name() + ".write_hits") 3266019Shines@cs.fsu.edu .desc("DTB write hits") 3276019Shines@cs.fsu.edu ; 3286019Shines@cs.fsu.edu 3297734SAli.Saidi@ARM.com writeMisses 3306019Shines@cs.fsu.edu .name(name() + ".write_misses") 3316019Shines@cs.fsu.edu .desc("DTB write misses") 3326019Shines@cs.fsu.edu ; 3336019Shines@cs.fsu.edu 3347734SAli.Saidi@ARM.com writeAccesses 3356019Shines@cs.fsu.edu .name(name() + ".write_accesses") 3366019Shines@cs.fsu.edu .desc("DTB write accesses") 3376019Shines@cs.fsu.edu ; 3386019Shines@cs.fsu.edu 3396019Shines@cs.fsu.edu hits 3406019Shines@cs.fsu.edu .name(name() + ".hits") 3416019Shines@cs.fsu.edu .desc("DTB hits") 3426019Shines@cs.fsu.edu ; 3436019Shines@cs.fsu.edu 3446019Shines@cs.fsu.edu misses 3456019Shines@cs.fsu.edu .name(name() + ".misses") 3466019Shines@cs.fsu.edu .desc("DTB misses") 3476019Shines@cs.fsu.edu ; 3486019Shines@cs.fsu.edu 3496019Shines@cs.fsu.edu accesses 3506019Shines@cs.fsu.edu .name(name() + ".accesses") 3516019Shines@cs.fsu.edu .desc("DTB accesses") 3526019Shines@cs.fsu.edu ; 3536019Shines@cs.fsu.edu 3547734SAli.Saidi@ARM.com flushTlb 3557734SAli.Saidi@ARM.com .name(name() + ".flush_tlb") 3567734SAli.Saidi@ARM.com .desc("Number of times complete TLB was flushed") 3577734SAli.Saidi@ARM.com ; 3587734SAli.Saidi@ARM.com 3597734SAli.Saidi@ARM.com flushTlbMva 3607734SAli.Saidi@ARM.com .name(name() + ".flush_tlb_mva") 3617734SAli.Saidi@ARM.com .desc("Number of times TLB was flushed by MVA") 3627734SAli.Saidi@ARM.com ; 3637734SAli.Saidi@ARM.com 3647734SAli.Saidi@ARM.com flushTlbMvaAsid 3657734SAli.Saidi@ARM.com .name(name() + ".flush_tlb_mva_asid") 3667734SAli.Saidi@ARM.com .desc("Number of times TLB was flushed by MVA & ASID") 3677734SAli.Saidi@ARM.com ; 3687734SAli.Saidi@ARM.com 3697734SAli.Saidi@ARM.com flushTlbAsid 3707734SAli.Saidi@ARM.com .name(name() + ".flush_tlb_asid") 3717734SAli.Saidi@ARM.com .desc("Number of times TLB was flushed by ASID") 3727734SAli.Saidi@ARM.com ; 3737734SAli.Saidi@ARM.com 3747734SAli.Saidi@ARM.com flushedEntries 3757734SAli.Saidi@ARM.com .name(name() + ".flush_entries") 3767734SAli.Saidi@ARM.com .desc("Number of entries that have been flushed from TLB") 3777734SAli.Saidi@ARM.com ; 3787734SAli.Saidi@ARM.com 3797734SAli.Saidi@ARM.com alignFaults 3807734SAli.Saidi@ARM.com .name(name() + ".align_faults") 3817734SAli.Saidi@ARM.com .desc("Number of TLB faults due to alignment restrictions") 3827734SAli.Saidi@ARM.com ; 3837734SAli.Saidi@ARM.com 3847734SAli.Saidi@ARM.com prefetchFaults 3857734SAli.Saidi@ARM.com .name(name() + ".prefetch_faults") 3867734SAli.Saidi@ARM.com .desc("Number of TLB faults due to prefetch") 3877734SAli.Saidi@ARM.com ; 3887734SAli.Saidi@ARM.com 3897734SAli.Saidi@ARM.com domainFaults 3907734SAli.Saidi@ARM.com .name(name() + ".domain_faults") 3917734SAli.Saidi@ARM.com .desc("Number of TLB faults due to domain restrictions") 3927734SAli.Saidi@ARM.com ; 3937734SAli.Saidi@ARM.com 3947734SAli.Saidi@ARM.com permsFaults 3957734SAli.Saidi@ARM.com .name(name() + ".perms_faults") 3967734SAli.Saidi@ARM.com .desc("Number of TLB faults due to permissions restrictions") 3977734SAli.Saidi@ARM.com ; 3987734SAli.Saidi@ARM.com 3997734SAli.Saidi@ARM.com instAccesses = instHits + instMisses; 4007734SAli.Saidi@ARM.com readAccesses = readHits + readMisses; 4017734SAli.Saidi@ARM.com writeAccesses = writeHits + writeMisses; 4027734SAli.Saidi@ARM.com hits = readHits + writeHits + instHits; 4037734SAli.Saidi@ARM.com misses = readMisses + writeMisses + instMisses; 4047734SAli.Saidi@ARM.com accesses = readAccesses + writeAccesses + instAccesses; 4056019Shines@cs.fsu.edu} 4066019Shines@cs.fsu.edu 4077404SAli.Saidi@ARM.com#if !FULL_SYSTEM 4087404SAli.Saidi@ARM.comFault 4097404SAli.Saidi@ARM.comTLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 4107404SAli.Saidi@ARM.com Translation *translation, bool &delay, bool timing) 4117404SAli.Saidi@ARM.com{ 4127749SAli.Saidi@ARM.com if (!miscRegValid) 4137749SAli.Saidi@ARM.com updateMiscReg(tc); 4147720Sgblack@eecs.umich.edu Addr vaddr = req->getVaddr(); 4157294Sgblack@eecs.umich.edu uint32_t flags = req->getFlags(); 4167294Sgblack@eecs.umich.edu 4177404SAli.Saidi@ARM.com bool is_fetch = (mode == Execute); 4187404SAli.Saidi@ARM.com bool is_write = (mode == Write); 4197404SAli.Saidi@ARM.com 4207404SAli.Saidi@ARM.com if (!is_fetch) { 4217294Sgblack@eecs.umich.edu assert(flags & MustBeOne); 4227404SAli.Saidi@ARM.com if (sctlr.a || !(flags & AllowUnaligned)) { 4237404SAli.Saidi@ARM.com if (vaddr & flags & AlignmentMask) { 4247404SAli.Saidi@ARM.com return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 4257294Sgblack@eecs.umich.edu } 4267294Sgblack@eecs.umich.edu } 4277294Sgblack@eecs.umich.edu } 4286019Shines@cs.fsu.edu 4297093Sgblack@eecs.umich.edu Addr paddr; 4307404SAli.Saidi@ARM.com Process *p = tc->getProcessPtr(); 4317404SAli.Saidi@ARM.com 4327093Sgblack@eecs.umich.edu if (!p->pTable->translate(vaddr, paddr)) 4337093Sgblack@eecs.umich.edu return Fault(new GenericPageTableFault(vaddr)); 4347093Sgblack@eecs.umich.edu req->setPaddr(paddr); 4356019Shines@cs.fsu.edu 4366019Shines@cs.fsu.edu return NoFault; 4377404SAli.Saidi@ARM.com} 4387404SAli.Saidi@ARM.com 4397404SAli.Saidi@ARM.com#else // FULL_SYSTEM 4407404SAli.Saidi@ARM.com 4417404SAli.Saidi@ARM.comFault 4427406SAli.Saidi@ARM.comTLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp) 4437406SAli.Saidi@ARM.com{ 4447406SAli.Saidi@ARM.com return NoFault; 4457406SAli.Saidi@ARM.com} 4467406SAli.Saidi@ARM.com 4477406SAli.Saidi@ARM.comFault 4487406SAli.Saidi@ARM.comTLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec, 4497406SAli.Saidi@ARM.com bool is_write, uint8_t domain, bool sNp) 4507406SAli.Saidi@ARM.com{ 4517406SAli.Saidi@ARM.com return NoFault; 4527406SAli.Saidi@ARM.com} 4537406SAli.Saidi@ARM.com 4547406SAli.Saidi@ARM.comFault 4557404SAli.Saidi@ARM.comTLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 4568733Sgeoffrey.blake@arm.com Translation *translation, bool &delay, bool timing, bool functional) 4577404SAli.Saidi@ARM.com{ 4588733Sgeoffrey.blake@arm.com // No such thing as a functional timing access 4598733Sgeoffrey.blake@arm.com assert(!(timing && functional)); 4608733Sgeoffrey.blake@arm.com 4618202SAli.Saidi@ARM.com if (!miscRegValid) { 4627749SAli.Saidi@ARM.com updateMiscReg(tc); 4638202SAli.Saidi@ARM.com DPRINTF(TLBVerbose, "TLB variables changed!\n"); 4648202SAli.Saidi@ARM.com } 4657749SAli.Saidi@ARM.com 4667720Sgblack@eecs.umich.edu Addr vaddr = req->getVaddr(); 4677404SAli.Saidi@ARM.com uint32_t flags = req->getFlags(); 4687404SAli.Saidi@ARM.com 4697404SAli.Saidi@ARM.com bool is_fetch = (mode == Execute); 4707404SAli.Saidi@ARM.com bool is_write = (mode == Write); 4717749SAli.Saidi@ARM.com bool is_priv = isPriv && !(flags & UserMode); 4727404SAli.Saidi@ARM.com 4738552Sdaniel.johnson@arm.com req->setAsid(contextId.asid); 4748552Sdaniel.johnson@arm.com 4758202SAli.Saidi@ARM.com DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n", 4767749SAli.Saidi@ARM.com isPriv, flags & UserMode); 4777603SGene.Wu@arm.com // If this is a clrex instruction, provide a PA of 0 with no fault 4787603SGene.Wu@arm.com // This will force the monitor to set the tracked address to 0 4797603SGene.Wu@arm.com // a bit of a hack but this effectively clrears this processors monitor 4807705Sgblack@eecs.umich.edu if (flags & Request::CLEAR_LL){ 4817603SGene.Wu@arm.com req->setPaddr(0); 4827606SGene.Wu@arm.com req->setFlags(Request::UNCACHEABLE); 4837705Sgblack@eecs.umich.edu req->setFlags(Request::CLEAR_LL); 4847603SGene.Wu@arm.com return NoFault; 4857603SGene.Wu@arm.com } 4867608SGene.Wu@arm.com if ((req->isInstFetch() && (!sctlr.i)) || 4877608SGene.Wu@arm.com ((!req->isInstFetch()) && (!sctlr.c))){ 4887608SGene.Wu@arm.com req->setFlags(Request::UNCACHEABLE); 4897608SGene.Wu@arm.com } 4907404SAli.Saidi@ARM.com if (!is_fetch) { 4917404SAli.Saidi@ARM.com assert(flags & MustBeOne); 4927404SAli.Saidi@ARM.com if (sctlr.a || !(flags & AllowUnaligned)) { 4937404SAli.Saidi@ARM.com if (vaddr & flags & AlignmentMask) { 4947734SAli.Saidi@ARM.com alignFaults++; 4957404SAli.Saidi@ARM.com return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 4967404SAli.Saidi@ARM.com } 4977404SAli.Saidi@ARM.com } 4987404SAli.Saidi@ARM.com } 4997404SAli.Saidi@ARM.com 5007404SAli.Saidi@ARM.com Fault fault; 5017404SAli.Saidi@ARM.com 5026757SAli.Saidi@ARM.com if (!sctlr.m) { 5037093Sgblack@eecs.umich.edu req->setPaddr(vaddr); 5047404SAli.Saidi@ARM.com if (sctlr.tre == 0) { 5057404SAli.Saidi@ARM.com req->setFlags(Request::UNCACHEABLE); 5067404SAli.Saidi@ARM.com } else { 5077404SAli.Saidi@ARM.com if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 5087404SAli.Saidi@ARM.com req->setFlags(Request::UNCACHEABLE); 5097404SAli.Saidi@ARM.com } 5107436Sdam.sunwoo@arm.com 5117436Sdam.sunwoo@arm.com // Set memory attributes 5127436Sdam.sunwoo@arm.com TlbEntry temp_te; 5137439Sdam.sunwoo@arm.com tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1); 5147436Sdam.sunwoo@arm.com temp_te.shareable = true; 5157436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\ 5167436Sdam.sunwoo@arm.com %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable, 5177436Sdam.sunwoo@arm.com temp_te.innerAttrs, temp_te.outerAttrs); 5187436Sdam.sunwoo@arm.com setAttr(temp_te.attributes); 5197436Sdam.sunwoo@arm.com 5207404SAli.Saidi@ARM.com return trickBoxCheck(req, mode, 0, false); 5217404SAli.Saidi@ARM.com } 5227404SAli.Saidi@ARM.com 5237749SAli.Saidi@ARM.com DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, contextId); 5247404SAli.Saidi@ARM.com // Translation enabled 5257404SAli.Saidi@ARM.com 5267749SAli.Saidi@ARM.com TlbEntry *te = lookup(vaddr, contextId); 5277404SAli.Saidi@ARM.com if (te == NULL) { 5287611SGene.Wu@arm.com if (req->isPrefetch()){ 5297611SGene.Wu@arm.com //if the request is a prefetch don't attempt to fill the TLB 5307611SGene.Wu@arm.com //or go any further with the memory access 5317734SAli.Saidi@ARM.com prefetchFaults++; 5327611SGene.Wu@arm.com return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss); 5337611SGene.Wu@arm.com } 5347734SAli.Saidi@ARM.com 5357734SAli.Saidi@ARM.com if (is_fetch) 5367734SAli.Saidi@ARM.com instMisses++; 5377734SAli.Saidi@ARM.com else if (is_write) 5387734SAli.Saidi@ARM.com writeMisses++; 5397734SAli.Saidi@ARM.com else 5407734SAli.Saidi@ARM.com readMisses++; 5417734SAli.Saidi@ARM.com 5427404SAli.Saidi@ARM.com // start translation table walk, pass variables rather than 5437404SAli.Saidi@ARM.com // re-retreaving in table walker for speed 5447404SAli.Saidi@ARM.com DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n", 5457749SAli.Saidi@ARM.com vaddr, contextId); 5467749SAli.Saidi@ARM.com fault = tableWalker->walk(req, tc, contextId, mode, translation, 5478733Sgeoffrey.blake@arm.com timing, functional); 5488067SAli.Saidi@ARM.com if (timing && fault == NoFault) { 5497404SAli.Saidi@ARM.com delay = true; 5507437Sdam.sunwoo@arm.com // for timing mode, return and wait for table walk 5517437Sdam.sunwoo@arm.com return fault; 5527437Sdam.sunwoo@arm.com } 5537404SAli.Saidi@ARM.com if (fault) 5547404SAli.Saidi@ARM.com return fault; 5557404SAli.Saidi@ARM.com 5567749SAli.Saidi@ARM.com te = lookup(vaddr, contextId); 5577404SAli.Saidi@ARM.com if (!te) 5587404SAli.Saidi@ARM.com printTlb(); 5597404SAli.Saidi@ARM.com assert(te); 5607734SAli.Saidi@ARM.com } else { 5617734SAli.Saidi@ARM.com if (is_fetch) 5627734SAli.Saidi@ARM.com instHits++; 5637734SAli.Saidi@ARM.com else if (is_write) 5647734SAli.Saidi@ARM.com writeHits++; 5657734SAli.Saidi@ARM.com else 5667734SAli.Saidi@ARM.com readHits++; 5677404SAli.Saidi@ARM.com } 5687404SAli.Saidi@ARM.com 5697436Sdam.sunwoo@arm.com // Set memory attributes 5707436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, 5717436Sdam.sunwoo@arm.com "Setting memory attributes: shareable: %d, innerAttrs: %d, \ 5727436Sdam.sunwoo@arm.com outerAttrs: %d\n", 5737436Sdam.sunwoo@arm.com te->shareable, te->innerAttrs, te->outerAttrs); 5747436Sdam.sunwoo@arm.com setAttr(te->attributes); 5757850SMatt.Horsnell@arm.com if (te->nonCacheable) { 5767606SGene.Wu@arm.com req->setFlags(Request::UNCACHEABLE); 5777749SAli.Saidi@ARM.com 5787850SMatt.Horsnell@arm.com // Prevent prefetching from I/O devices. 5797850SMatt.Horsnell@arm.com if (req->isPrefetch()) { 5807850SMatt.Horsnell@arm.com return new PrefetchAbort(vaddr, ArmFault::PrefetchUncacheable); 5817850SMatt.Horsnell@arm.com } 5827850SMatt.Horsnell@arm.com } 5837850SMatt.Horsnell@arm.com 5848527SAli.Saidi@ARM.com 5858527SAli.Saidi@ARM.com if (!bootUncacheability && 5868527SAli.Saidi@ARM.com ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr)) 5878527SAli.Saidi@ARM.com req->setFlags(Request::UNCACHEABLE); 5888527SAli.Saidi@ARM.com 5897404SAli.Saidi@ARM.com switch ( (dacr >> (te->domain * 2)) & 0x3) { 5907404SAli.Saidi@ARM.com case 0: 5917734SAli.Saidi@ARM.com domainFaults++; 5927404SAli.Saidi@ARM.com DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x" 5937404SAli.Saidi@ARM.com " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp); 5947404SAli.Saidi@ARM.com if (is_fetch) 5957404SAli.Saidi@ARM.com return new PrefetchAbort(vaddr, 5967404SAli.Saidi@ARM.com (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 5977404SAli.Saidi@ARM.com else 5987404SAli.Saidi@ARM.com return new DataAbort(vaddr, te->domain, is_write, 5997404SAli.Saidi@ARM.com (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 6007404SAli.Saidi@ARM.com case 1: 6017404SAli.Saidi@ARM.com // Continue with permissions check 6027404SAli.Saidi@ARM.com break; 6037404SAli.Saidi@ARM.com case 2: 6047404SAli.Saidi@ARM.com panic("UNPRED domain\n"); 6057404SAli.Saidi@ARM.com case 3: 6067404SAli.Saidi@ARM.com req->setPaddr(te->pAddr(vaddr)); 6077404SAli.Saidi@ARM.com fault = trickBoxCheck(req, mode, te->domain, te->sNp); 6087404SAli.Saidi@ARM.com if (fault) 6097404SAli.Saidi@ARM.com return fault; 6106757SAli.Saidi@ARM.com return NoFault; 6116757SAli.Saidi@ARM.com } 6127404SAli.Saidi@ARM.com 6137404SAli.Saidi@ARM.com uint8_t ap = te->ap; 6147404SAli.Saidi@ARM.com 6157404SAli.Saidi@ARM.com if (sctlr.afe == 1) 6167404SAli.Saidi@ARM.com ap |= 1; 6177404SAli.Saidi@ARM.com 6187404SAli.Saidi@ARM.com bool abt; 6197404SAli.Saidi@ARM.com 6207406SAli.Saidi@ARM.com /* if (!sctlr.xp) 6217406SAli.Saidi@ARM.com ap &= 0x3; 6227406SAli.Saidi@ARM.com*/ 6237404SAli.Saidi@ARM.com switch (ap) { 6247404SAli.Saidi@ARM.com case 0: 6257406SAli.Saidi@ARM.com DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs); 6267406SAli.Saidi@ARM.com if (!sctlr.xp) { 6277406SAli.Saidi@ARM.com switch ((int)sctlr.rs) { 6287406SAli.Saidi@ARM.com case 2: 6297406SAli.Saidi@ARM.com abt = is_write; 6307406SAli.Saidi@ARM.com break; 6317406SAli.Saidi@ARM.com case 1: 6327406SAli.Saidi@ARM.com abt = is_write || !is_priv; 6337406SAli.Saidi@ARM.com break; 6347406SAli.Saidi@ARM.com case 0: 6357406SAli.Saidi@ARM.com case 3: 6367406SAli.Saidi@ARM.com default: 6377406SAli.Saidi@ARM.com abt = true; 6387406SAli.Saidi@ARM.com break; 6397406SAli.Saidi@ARM.com } 6407406SAli.Saidi@ARM.com } else { 6417406SAli.Saidi@ARM.com abt = true; 6427406SAli.Saidi@ARM.com } 6437404SAli.Saidi@ARM.com break; 6447404SAli.Saidi@ARM.com case 1: 6457404SAli.Saidi@ARM.com abt = !is_priv; 6467404SAli.Saidi@ARM.com break; 6477404SAli.Saidi@ARM.com case 2: 6487404SAli.Saidi@ARM.com abt = !is_priv && is_write; 6497404SAli.Saidi@ARM.com break; 6507404SAli.Saidi@ARM.com case 3: 6517404SAli.Saidi@ARM.com abt = false; 6527404SAli.Saidi@ARM.com break; 6537404SAli.Saidi@ARM.com case 4: 6547404SAli.Saidi@ARM.com panic("UNPRED premissions\n"); 6557404SAli.Saidi@ARM.com case 5: 6567404SAli.Saidi@ARM.com abt = !is_priv || is_write; 6577404SAli.Saidi@ARM.com break; 6587404SAli.Saidi@ARM.com case 6: 6597404SAli.Saidi@ARM.com case 7: 6607404SAli.Saidi@ARM.com abt = is_write; 6617404SAli.Saidi@ARM.com break; 6627404SAli.Saidi@ARM.com default: 6637404SAli.Saidi@ARM.com panic("Unknown permissions\n"); 6647404SAli.Saidi@ARM.com } 6657404SAli.Saidi@ARM.com if ((is_fetch) && (abt || te->xn)) { 6667734SAli.Saidi@ARM.com permsFaults++; 6677404SAli.Saidi@ARM.com DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d" 6687404SAli.Saidi@ARM.com " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 6697404SAli.Saidi@ARM.com return new PrefetchAbort(vaddr, 6707404SAli.Saidi@ARM.com (te->sNp ? ArmFault::Permission0 : 6717404SAli.Saidi@ARM.com ArmFault::Permission1)); 6727404SAli.Saidi@ARM.com } else if (abt) { 6737734SAli.Saidi@ARM.com permsFaults++; 6747404SAli.Saidi@ARM.com DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 6757404SAli.Saidi@ARM.com " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 6767404SAli.Saidi@ARM.com return new DataAbort(vaddr, te->domain, is_write, 6777404SAli.Saidi@ARM.com (te->sNp ? ArmFault::Permission0 : 6787404SAli.Saidi@ARM.com ArmFault::Permission1)); 6797404SAli.Saidi@ARM.com } 6807404SAli.Saidi@ARM.com 6817404SAli.Saidi@ARM.com req->setPaddr(te->pAddr(vaddr)); 6827404SAli.Saidi@ARM.com // Check for a trickbox generated address fault 6837404SAli.Saidi@ARM.com fault = trickBoxCheck(req, mode, te->domain, te->sNp); 6847404SAli.Saidi@ARM.com if (fault) 6857404SAli.Saidi@ARM.com return fault; 6867404SAli.Saidi@ARM.com 6876757SAli.Saidi@ARM.com return NoFault; 6887404SAli.Saidi@ARM.com} 6896757SAli.Saidi@ARM.com 6906019Shines@cs.fsu.edu#endif 6917404SAli.Saidi@ARM.com 6927404SAli.Saidi@ARM.comFault 6937404SAli.Saidi@ARM.comTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 6947404SAli.Saidi@ARM.com{ 6957404SAli.Saidi@ARM.com bool delay = false; 6967404SAli.Saidi@ARM.com Fault fault; 6977404SAli.Saidi@ARM.com#if FULL_SYSTEM 6987404SAli.Saidi@ARM.com fault = translateFs(req, tc, mode, NULL, delay, false); 6997404SAli.Saidi@ARM.com#else 7007404SAli.Saidi@ARM.com fault = translateSe(req, tc, mode, NULL, delay, false); 7017404SAli.Saidi@ARM.com#endif 7027404SAli.Saidi@ARM.com assert(!delay); 7037404SAli.Saidi@ARM.com return fault; 7046019Shines@cs.fsu.edu} 7056019Shines@cs.fsu.edu 7067404SAli.Saidi@ARM.comFault 7078733Sgeoffrey.blake@arm.comTLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) 7088733Sgeoffrey.blake@arm.com{ 7098733Sgeoffrey.blake@arm.com bool delay = false; 7108733Sgeoffrey.blake@arm.com Fault fault; 7118733Sgeoffrey.blake@arm.com#if FULL_SYSTEM 7128733Sgeoffrey.blake@arm.com fault = translateFs(req, tc, mode, NULL, delay, false, true); 7138733Sgeoffrey.blake@arm.com#else 7148733Sgeoffrey.blake@arm.com fault = translateSe(req, tc, mode, NULL, delay, false); 7158733Sgeoffrey.blake@arm.com#endif 7168733Sgeoffrey.blake@arm.com assert(!delay); 7178733Sgeoffrey.blake@arm.com return fault; 7188733Sgeoffrey.blake@arm.com} 7198733Sgeoffrey.blake@arm.com 7208733Sgeoffrey.blake@arm.comFault 7216116Snate@binkert.orgTLB::translateTiming(RequestPtr req, ThreadContext *tc, 7226116Snate@binkert.org Translation *translation, Mode mode) 7236020Sgblack@eecs.umich.edu{ 7246020Sgblack@eecs.umich.edu assert(translation); 7257404SAli.Saidi@ARM.com bool delay = false; 7267404SAli.Saidi@ARM.com Fault fault; 7277404SAli.Saidi@ARM.com#if FULL_SYSTEM 7287404SAli.Saidi@ARM.com fault = translateFs(req, tc, mode, translation, delay, true); 7297404SAli.Saidi@ARM.com#else 7307404SAli.Saidi@ARM.com fault = translateSe(req, tc, mode, translation, delay, true); 7317404SAli.Saidi@ARM.com#endif 7328527SAli.Saidi@ARM.com DPRINTF(TLBVerbose, "Translation returning delay=%d fault=%d\n", delay, fault != 7338067SAli.Saidi@ARM.com NoFault); 7347404SAli.Saidi@ARM.com if (!delay) 7357404SAli.Saidi@ARM.com translation->finish(fault, req, tc, mode); 7367944SGiacomo.Gabrielli@arm.com else 7377944SGiacomo.Gabrielli@arm.com translation->markDelayed(); 7387404SAli.Saidi@ARM.com return fault; 7396020Sgblack@eecs.umich.edu} 7406020Sgblack@eecs.umich.edu 7417781SAli.Saidi@ARM.comPort* 7427781SAli.Saidi@ARM.comTLB::getPort() 7437781SAli.Saidi@ARM.com{ 7447781SAli.Saidi@ARM.com#if FULL_SYSTEM 7457781SAli.Saidi@ARM.com return tableWalker->getPort("port"); 7467781SAli.Saidi@ARM.com#else 7477781SAli.Saidi@ARM.com return NULL; 7487781SAli.Saidi@ARM.com#endif 7497781SAli.Saidi@ARM.com} 7507781SAli.Saidi@ARM.com 7517781SAli.Saidi@ARM.com 7527781SAli.Saidi@ARM.com 7536116Snate@binkert.orgArmISA::TLB * 7546116Snate@binkert.orgArmTLBParams::create() 7556019Shines@cs.fsu.edu{ 7566116Snate@binkert.org return new ArmISA::TLB(this); 7576019Shines@cs.fsu.edu} 758