tlb.cc revision 7734
16019Shines@cs.fsu.edu/* 27093Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * All rights reserved. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 266019Shines@cs.fsu.edu * this software without specific prior written permission. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019Shines@cs.fsu.edu * 407399SAli.Saidi@ARM.com * Authors: Ali Saidi 417399SAli.Saidi@ARM.com * Nathan Binkert 426019Shines@cs.fsu.edu * Steve Reinhardt 436019Shines@cs.fsu.edu */ 446019Shines@cs.fsu.edu 456019Shines@cs.fsu.edu#include <string> 466019Shines@cs.fsu.edu#include <vector> 476019Shines@cs.fsu.edu 486116Snate@binkert.org#include "arch/arm/faults.hh" 496019Shines@cs.fsu.edu#include "arch/arm/pagetable.hh" 506019Shines@cs.fsu.edu#include "arch/arm/tlb.hh" 516019Shines@cs.fsu.edu#include "arch/arm/utility.hh" 526019Shines@cs.fsu.edu#include "base/inifile.hh" 536019Shines@cs.fsu.edu#include "base/str.hh" 546019Shines@cs.fsu.edu#include "base/trace.hh" 556019Shines@cs.fsu.edu#include "cpu/thread_context.hh" 566116Snate@binkert.org#include "mem/page_table.hh" 576116Snate@binkert.org#include "params/ArmTLB.hh" 586019Shines@cs.fsu.edu#include "sim/process.hh" 596019Shines@cs.fsu.edu 607406SAli.Saidi@ARM.com#if FULL_SYSTEM 617406SAli.Saidi@ARM.com#include "arch/arm/table_walker.hh" 627406SAli.Saidi@ARM.com#endif 637406SAli.Saidi@ARM.com 646019Shines@cs.fsu.eduusing namespace std; 656019Shines@cs.fsu.eduusing namespace ArmISA; 666019Shines@cs.fsu.edu 676019Shines@cs.fsu.eduTLB::TLB(const Params *p) 687697SAli.Saidi@ARM.com : BaseTLB(p), size(p->size) 697404SAli.Saidi@ARM.com#if FULL_SYSTEM 707404SAli.Saidi@ARM.com , tableWalker(p->walker) 717404SAli.Saidi@ARM.com#endif 727697SAli.Saidi@ARM.com , rangeMRU(1) 736019Shines@cs.fsu.edu{ 747404SAli.Saidi@ARM.com table = new TlbEntry[size]; 757404SAli.Saidi@ARM.com memset(table, 0, sizeof(TlbEntry[size])); 767399SAli.Saidi@ARM.com 777406SAli.Saidi@ARM.com#if FULL_SYSTEM 787404SAli.Saidi@ARM.com tableWalker->setTlb(this); 797406SAli.Saidi@ARM.com#endif 806019Shines@cs.fsu.edu} 816019Shines@cs.fsu.edu 826019Shines@cs.fsu.eduTLB::~TLB() 836019Shines@cs.fsu.edu{ 846019Shines@cs.fsu.edu if (table) 856019Shines@cs.fsu.edu delete [] table; 866019Shines@cs.fsu.edu} 876019Shines@cs.fsu.edu 887694SAli.Saidi@ARM.combool 897694SAli.Saidi@ARM.comTLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa) 907694SAli.Saidi@ARM.com{ 917694SAli.Saidi@ARM.com uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR); 927694SAli.Saidi@ARM.com TlbEntry *e = lookup(va, context_id, true); 937694SAli.Saidi@ARM.com if (!e) 947694SAli.Saidi@ARM.com return false; 957694SAli.Saidi@ARM.com pa = e->pAddr(va); 967694SAli.Saidi@ARM.com return true; 977694SAli.Saidi@ARM.com} 987694SAli.Saidi@ARM.com 997404SAli.Saidi@ARM.comTlbEntry* 1007694SAli.Saidi@ARM.comTLB::lookup(Addr va, uint8_t cid, bool functional) 1016019Shines@cs.fsu.edu{ 1027404SAli.Saidi@ARM.com 1037404SAli.Saidi@ARM.com TlbEntry *retval = NULL; 1047404SAli.Saidi@ARM.com 1057697SAli.Saidi@ARM.com // Maitaining LRU array 1067404SAli.Saidi@ARM.com 1077404SAli.Saidi@ARM.com int x = 0; 1087404SAli.Saidi@ARM.com while (retval == NULL && x < size) { 1097404SAli.Saidi@ARM.com if (table[x].match(va, cid)) { 1107404SAli.Saidi@ARM.com 1117697SAli.Saidi@ARM.com // We only move the hit entry ahead when the position is higher than rangeMRU 1127697SAli.Saidi@ARM.com if (x > rangeMRU) { 1137697SAli.Saidi@ARM.com TlbEntry tmp_entry = table[x]; 1147697SAli.Saidi@ARM.com for(int i = x; i > 0; i--) 1157697SAli.Saidi@ARM.com table[i] = table[i-1]; 1167697SAli.Saidi@ARM.com table[0] = tmp_entry; 1177697SAli.Saidi@ARM.com retval = &table[0]; 1187697SAli.Saidi@ARM.com } else { 1197697SAli.Saidi@ARM.com retval = &table[x]; 1207697SAli.Saidi@ARM.com } 1217404SAli.Saidi@ARM.com break; 1227404SAli.Saidi@ARM.com } 1237404SAli.Saidi@ARM.com x++; 1247404SAli.Saidi@ARM.com } 1257404SAli.Saidi@ARM.com 1267404SAli.Saidi@ARM.com DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n", 1277404SAli.Saidi@ARM.com va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0, 1287404SAli.Saidi@ARM.com retval ? retval->size : 0, retval ? retval->pAddr(va) : 0, 1297404SAli.Saidi@ARM.com retval ? retval->ap : 0); 1307404SAli.Saidi@ARM.com ; 1317404SAli.Saidi@ARM.com return retval; 1326019Shines@cs.fsu.edu} 1336019Shines@cs.fsu.edu 1346019Shines@cs.fsu.edu// insert a new TLB entry 1356019Shines@cs.fsu.eduvoid 1367404SAli.Saidi@ARM.comTLB::insert(Addr addr, TlbEntry &entry) 1376019Shines@cs.fsu.edu{ 1387404SAli.Saidi@ARM.com DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x" 1397404SAli.Saidi@ARM.com " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x" 1407404SAli.Saidi@ARM.com " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid, 1417404SAli.Saidi@ARM.com entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp, 1427404SAli.Saidi@ARM.com entry.xn, entry.ap, entry.domain); 1437404SAli.Saidi@ARM.com 1447697SAli.Saidi@ARM.com if (table[size-1].valid) 1457404SAli.Saidi@ARM.com DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n", 1467697SAli.Saidi@ARM.com table[size-1].vpn << table[size-1].N, table[size-1].asid, 1477697SAli.Saidi@ARM.com table[size-1].pfn << table[size-1].N, table[size-1].size, 1487697SAli.Saidi@ARM.com table[size-1].ap); 1497404SAli.Saidi@ARM.com 1507697SAli.Saidi@ARM.com //inserting to MRU position and evicting the LRU one 1517404SAli.Saidi@ARM.com 1527697SAli.Saidi@ARM.com for(int i = size-1; i > 0; i--) 1537697SAli.Saidi@ARM.com table[i] = table[i-1]; 1547697SAli.Saidi@ARM.com table[0] = entry; 1557734SAli.Saidi@ARM.com 1567734SAli.Saidi@ARM.com inserts++; 1576019Shines@cs.fsu.edu} 1586019Shines@cs.fsu.edu 1596019Shines@cs.fsu.eduvoid 1607404SAli.Saidi@ARM.comTLB::printTlb() 1617404SAli.Saidi@ARM.com{ 1627404SAli.Saidi@ARM.com int x = 0; 1637404SAli.Saidi@ARM.com TlbEntry *te; 1647404SAli.Saidi@ARM.com DPRINTF(TLB, "Current TLB contents:\n"); 1657404SAli.Saidi@ARM.com while (x < size) { 1667404SAli.Saidi@ARM.com te = &table[x]; 1677404SAli.Saidi@ARM.com if (te->valid) 1687404SAli.Saidi@ARM.com DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n", 1697404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 1707404SAli.Saidi@ARM.com x++; 1717404SAli.Saidi@ARM.com } 1727404SAli.Saidi@ARM.com} 1737404SAli.Saidi@ARM.com 1747404SAli.Saidi@ARM.com 1757404SAli.Saidi@ARM.comvoid 1766019Shines@cs.fsu.eduTLB::flushAll() 1776019Shines@cs.fsu.edu{ 1787404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing all TLB entries\n"); 1797404SAli.Saidi@ARM.com int x = 0; 1807404SAli.Saidi@ARM.com TlbEntry *te; 1817404SAli.Saidi@ARM.com while (x < size) { 1827404SAli.Saidi@ARM.com te = &table[x]; 1837734SAli.Saidi@ARM.com if (te->valid) { 1847404SAli.Saidi@ARM.com DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 1857404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 1867734SAli.Saidi@ARM.com flushedEntries++; 1877734SAli.Saidi@ARM.com } 1887404SAli.Saidi@ARM.com x++; 1897404SAli.Saidi@ARM.com } 1907404SAli.Saidi@ARM.com 1917404SAli.Saidi@ARM.com memset(table, 0, sizeof(TlbEntry[size])); 1927734SAli.Saidi@ARM.com 1937734SAli.Saidi@ARM.com flushTlb++; 1946019Shines@cs.fsu.edu} 1956019Shines@cs.fsu.edu 1967404SAli.Saidi@ARM.com 1977404SAli.Saidi@ARM.comvoid 1987404SAli.Saidi@ARM.comTLB::flushMvaAsid(Addr mva, uint64_t asn) 1997404SAli.Saidi@ARM.com{ 2007404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn); 2017404SAli.Saidi@ARM.com TlbEntry *te; 2027404SAli.Saidi@ARM.com 2037404SAli.Saidi@ARM.com te = lookup(mva, asn); 2047404SAli.Saidi@ARM.com while (te != NULL) { 2057404SAli.Saidi@ARM.com DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 2067404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 2077404SAli.Saidi@ARM.com te->valid = false; 2087734SAli.Saidi@ARM.com flushedEntries++; 2097404SAli.Saidi@ARM.com te = lookup(mva,asn); 2107404SAli.Saidi@ARM.com } 2117734SAli.Saidi@ARM.com flushTlbMvaAsid++; 2127404SAli.Saidi@ARM.com} 2137404SAli.Saidi@ARM.com 2147404SAli.Saidi@ARM.comvoid 2157404SAli.Saidi@ARM.comTLB::flushAsid(uint64_t asn) 2167404SAli.Saidi@ARM.com{ 2177404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn); 2187404SAli.Saidi@ARM.com 2197404SAli.Saidi@ARM.com int x = 0; 2207404SAli.Saidi@ARM.com TlbEntry *te; 2217404SAli.Saidi@ARM.com 2227404SAli.Saidi@ARM.com while (x < size) { 2237404SAli.Saidi@ARM.com te = &table[x]; 2247404SAli.Saidi@ARM.com if (te->asid == asn) { 2257404SAli.Saidi@ARM.com te->valid = false; 2267404SAli.Saidi@ARM.com DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 2277404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 2287734SAli.Saidi@ARM.com flushedEntries++; 2297404SAli.Saidi@ARM.com } 2307404SAli.Saidi@ARM.com x++; 2317404SAli.Saidi@ARM.com } 2327734SAli.Saidi@ARM.com flushTlbAsid++; 2337404SAli.Saidi@ARM.com} 2347404SAli.Saidi@ARM.com 2357404SAli.Saidi@ARM.comvoid 2367404SAli.Saidi@ARM.comTLB::flushMva(Addr mva) 2377404SAli.Saidi@ARM.com{ 2387404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva); 2397404SAli.Saidi@ARM.com 2407404SAli.Saidi@ARM.com int x = 0; 2417404SAli.Saidi@ARM.com TlbEntry *te; 2427404SAli.Saidi@ARM.com 2437404SAli.Saidi@ARM.com while (x < size) { 2447404SAli.Saidi@ARM.com te = &table[x]; 2457404SAli.Saidi@ARM.com Addr v = te->vpn << te->N; 2467404SAli.Saidi@ARM.com if (mva >= v && mva < v + te->size) { 2477404SAli.Saidi@ARM.com te->valid = false; 2487404SAli.Saidi@ARM.com DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 2497404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 2507734SAli.Saidi@ARM.com flushedEntries++; 2517404SAli.Saidi@ARM.com } 2527404SAli.Saidi@ARM.com x++; 2537404SAli.Saidi@ARM.com } 2547734SAli.Saidi@ARM.com flushTlbMva++; 2557404SAli.Saidi@ARM.com} 2567404SAli.Saidi@ARM.com 2576019Shines@cs.fsu.eduvoid 2586019Shines@cs.fsu.eduTLB::serialize(ostream &os) 2596019Shines@cs.fsu.edu{ 2607733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Serializing Arm TLB\n"); 2617733SAli.Saidi@ARM.com 2627733SAli.Saidi@ARM.com SERIALIZE_SCALAR(_attr); 2637733SAli.Saidi@ARM.com for(int i = 0; i < size; i++){ 2647733SAli.Saidi@ARM.com nameOut(os, csprintf("%s.TlbEntry%d", name(), i)); 2657733SAli.Saidi@ARM.com table[i].serialize(os); 2667733SAli.Saidi@ARM.com } 2676019Shines@cs.fsu.edu} 2686019Shines@cs.fsu.edu 2696019Shines@cs.fsu.eduvoid 2706019Shines@cs.fsu.eduTLB::unserialize(Checkpoint *cp, const string §ion) 2716019Shines@cs.fsu.edu{ 2727733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Unserializing Arm TLB\n"); 2736019Shines@cs.fsu.edu 2747733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(_attr); 2757733SAli.Saidi@ARM.com for(int i = 0; i < size; i++){ 2767733SAli.Saidi@ARM.com table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i)); 2777733SAli.Saidi@ARM.com } 2786019Shines@cs.fsu.edu} 2796019Shines@cs.fsu.edu 2806019Shines@cs.fsu.eduvoid 2816019Shines@cs.fsu.eduTLB::regStats() 2826019Shines@cs.fsu.edu{ 2837734SAli.Saidi@ARM.com instHits 2847734SAli.Saidi@ARM.com .name(name() + ".inst_hits") 2857734SAli.Saidi@ARM.com .desc("ITB inst hits") 2867734SAli.Saidi@ARM.com ; 2877734SAli.Saidi@ARM.com 2887734SAli.Saidi@ARM.com instMisses 2897734SAli.Saidi@ARM.com .name(name() + ".inst_misses") 2907734SAli.Saidi@ARM.com .desc("ITB inst misses") 2917734SAli.Saidi@ARM.com ; 2927734SAli.Saidi@ARM.com 2937734SAli.Saidi@ARM.com instAccesses 2947734SAli.Saidi@ARM.com .name(name() + ".inst_accesses") 2957734SAli.Saidi@ARM.com .desc("ITB inst accesses") 2967734SAli.Saidi@ARM.com ; 2977734SAli.Saidi@ARM.com 2987734SAli.Saidi@ARM.com readHits 2996019Shines@cs.fsu.edu .name(name() + ".read_hits") 3006019Shines@cs.fsu.edu .desc("DTB read hits") 3016019Shines@cs.fsu.edu ; 3026019Shines@cs.fsu.edu 3037734SAli.Saidi@ARM.com readMisses 3046019Shines@cs.fsu.edu .name(name() + ".read_misses") 3056019Shines@cs.fsu.edu .desc("DTB read misses") 3066019Shines@cs.fsu.edu ; 3076019Shines@cs.fsu.edu 3087734SAli.Saidi@ARM.com readAccesses 3096019Shines@cs.fsu.edu .name(name() + ".read_accesses") 3106019Shines@cs.fsu.edu .desc("DTB read accesses") 3116019Shines@cs.fsu.edu ; 3126019Shines@cs.fsu.edu 3137734SAli.Saidi@ARM.com writeHits 3146019Shines@cs.fsu.edu .name(name() + ".write_hits") 3156019Shines@cs.fsu.edu .desc("DTB write hits") 3166019Shines@cs.fsu.edu ; 3176019Shines@cs.fsu.edu 3187734SAli.Saidi@ARM.com writeMisses 3196019Shines@cs.fsu.edu .name(name() + ".write_misses") 3206019Shines@cs.fsu.edu .desc("DTB write misses") 3216019Shines@cs.fsu.edu ; 3226019Shines@cs.fsu.edu 3237734SAli.Saidi@ARM.com writeAccesses 3246019Shines@cs.fsu.edu .name(name() + ".write_accesses") 3256019Shines@cs.fsu.edu .desc("DTB write accesses") 3266019Shines@cs.fsu.edu ; 3276019Shines@cs.fsu.edu 3286019Shines@cs.fsu.edu hits 3296019Shines@cs.fsu.edu .name(name() + ".hits") 3306019Shines@cs.fsu.edu .desc("DTB hits") 3316019Shines@cs.fsu.edu ; 3326019Shines@cs.fsu.edu 3336019Shines@cs.fsu.edu misses 3346019Shines@cs.fsu.edu .name(name() + ".misses") 3356019Shines@cs.fsu.edu .desc("DTB misses") 3366019Shines@cs.fsu.edu ; 3376019Shines@cs.fsu.edu 3386019Shines@cs.fsu.edu accesses 3396019Shines@cs.fsu.edu .name(name() + ".accesses") 3406019Shines@cs.fsu.edu .desc("DTB accesses") 3416019Shines@cs.fsu.edu ; 3426019Shines@cs.fsu.edu 3437734SAli.Saidi@ARM.com flushTlb 3447734SAli.Saidi@ARM.com .name(name() + ".flush_tlb") 3457734SAli.Saidi@ARM.com .desc("Number of times complete TLB was flushed") 3467734SAli.Saidi@ARM.com ; 3477734SAli.Saidi@ARM.com 3487734SAli.Saidi@ARM.com flushTlbMva 3497734SAli.Saidi@ARM.com .name(name() + ".flush_tlb_mva") 3507734SAli.Saidi@ARM.com .desc("Number of times TLB was flushed by MVA") 3517734SAli.Saidi@ARM.com ; 3527734SAli.Saidi@ARM.com 3537734SAli.Saidi@ARM.com flushTlbMvaAsid 3547734SAli.Saidi@ARM.com .name(name() + ".flush_tlb_mva_asid") 3557734SAli.Saidi@ARM.com .desc("Number of times TLB was flushed by MVA & ASID") 3567734SAli.Saidi@ARM.com ; 3577734SAli.Saidi@ARM.com 3587734SAli.Saidi@ARM.com flushTlbAsid 3597734SAli.Saidi@ARM.com .name(name() + ".flush_tlb_asid") 3607734SAli.Saidi@ARM.com .desc("Number of times TLB was flushed by ASID") 3617734SAli.Saidi@ARM.com ; 3627734SAli.Saidi@ARM.com 3637734SAli.Saidi@ARM.com flushedEntries 3647734SAli.Saidi@ARM.com .name(name() + ".flush_entries") 3657734SAli.Saidi@ARM.com .desc("Number of entries that have been flushed from TLB") 3667734SAli.Saidi@ARM.com ; 3677734SAli.Saidi@ARM.com 3687734SAli.Saidi@ARM.com alignFaults 3697734SAli.Saidi@ARM.com .name(name() + ".align_faults") 3707734SAli.Saidi@ARM.com .desc("Number of TLB faults due to alignment restrictions") 3717734SAli.Saidi@ARM.com ; 3727734SAli.Saidi@ARM.com 3737734SAli.Saidi@ARM.com prefetchFaults 3747734SAli.Saidi@ARM.com .name(name() + ".prefetch_faults") 3757734SAli.Saidi@ARM.com .desc("Number of TLB faults due to prefetch") 3767734SAli.Saidi@ARM.com ; 3777734SAli.Saidi@ARM.com 3787734SAli.Saidi@ARM.com domainFaults 3797734SAli.Saidi@ARM.com .name(name() + ".domain_faults") 3807734SAli.Saidi@ARM.com .desc("Number of TLB faults due to domain restrictions") 3817734SAli.Saidi@ARM.com ; 3827734SAli.Saidi@ARM.com 3837734SAli.Saidi@ARM.com permsFaults 3847734SAli.Saidi@ARM.com .name(name() + ".perms_faults") 3857734SAli.Saidi@ARM.com .desc("Number of TLB faults due to permissions restrictions") 3867734SAli.Saidi@ARM.com ; 3877734SAli.Saidi@ARM.com 3887734SAli.Saidi@ARM.com instAccesses = instHits + instMisses; 3897734SAli.Saidi@ARM.com readAccesses = readHits + readMisses; 3907734SAli.Saidi@ARM.com writeAccesses = writeHits + writeMisses; 3917734SAli.Saidi@ARM.com hits = readHits + writeHits + instHits; 3927734SAli.Saidi@ARM.com misses = readMisses + writeMisses + instMisses; 3937734SAli.Saidi@ARM.com accesses = readAccesses + writeAccesses + instAccesses; 3946019Shines@cs.fsu.edu} 3956019Shines@cs.fsu.edu 3967404SAli.Saidi@ARM.com#if !FULL_SYSTEM 3977404SAli.Saidi@ARM.comFault 3987404SAli.Saidi@ARM.comTLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 3997404SAli.Saidi@ARM.com Translation *translation, bool &delay, bool timing) 4007404SAli.Saidi@ARM.com{ 4017404SAli.Saidi@ARM.com // XXX Cache misc registers and have miscreg write function inv cache 4027720Sgblack@eecs.umich.edu Addr vaddr = req->getVaddr(); 4037294Sgblack@eecs.umich.edu SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 4047294Sgblack@eecs.umich.edu uint32_t flags = req->getFlags(); 4057294Sgblack@eecs.umich.edu 4067404SAli.Saidi@ARM.com bool is_fetch = (mode == Execute); 4077404SAli.Saidi@ARM.com bool is_write = (mode == Write); 4087404SAli.Saidi@ARM.com 4097404SAli.Saidi@ARM.com if (!is_fetch) { 4107294Sgblack@eecs.umich.edu assert(flags & MustBeOne); 4117404SAli.Saidi@ARM.com if (sctlr.a || !(flags & AllowUnaligned)) { 4127404SAli.Saidi@ARM.com if (vaddr & flags & AlignmentMask) { 4137404SAli.Saidi@ARM.com return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 4147294Sgblack@eecs.umich.edu } 4157294Sgblack@eecs.umich.edu } 4167294Sgblack@eecs.umich.edu } 4176019Shines@cs.fsu.edu 4187093Sgblack@eecs.umich.edu Addr paddr; 4197404SAli.Saidi@ARM.com Process *p = tc->getProcessPtr(); 4207404SAli.Saidi@ARM.com 4217093Sgblack@eecs.umich.edu if (!p->pTable->translate(vaddr, paddr)) 4227093Sgblack@eecs.umich.edu return Fault(new GenericPageTableFault(vaddr)); 4237093Sgblack@eecs.umich.edu req->setPaddr(paddr); 4246019Shines@cs.fsu.edu 4256019Shines@cs.fsu.edu return NoFault; 4267404SAli.Saidi@ARM.com} 4277404SAli.Saidi@ARM.com 4287404SAli.Saidi@ARM.com#else // FULL_SYSTEM 4297404SAli.Saidi@ARM.com 4307404SAli.Saidi@ARM.comFault 4317406SAli.Saidi@ARM.comTLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp) 4327406SAli.Saidi@ARM.com{ 4337406SAli.Saidi@ARM.com return NoFault; 4347406SAli.Saidi@ARM.com} 4357406SAli.Saidi@ARM.com 4367406SAli.Saidi@ARM.comFault 4377406SAli.Saidi@ARM.comTLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec, 4387406SAli.Saidi@ARM.com bool is_write, uint8_t domain, bool sNp) 4397406SAli.Saidi@ARM.com{ 4407406SAli.Saidi@ARM.com return NoFault; 4417406SAli.Saidi@ARM.com} 4427406SAli.Saidi@ARM.com 4437406SAli.Saidi@ARM.comFault 4447404SAli.Saidi@ARM.comTLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 4457404SAli.Saidi@ARM.com Translation *translation, bool &delay, bool timing) 4467404SAli.Saidi@ARM.com{ 4477404SAli.Saidi@ARM.com // XXX Cache misc registers and have miscreg write function inv cache 4487720Sgblack@eecs.umich.edu Addr vaddr = req->getVaddr(); 4497404SAli.Saidi@ARM.com SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 4507404SAli.Saidi@ARM.com CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 4517404SAli.Saidi@ARM.com uint32_t flags = req->getFlags(); 4527404SAli.Saidi@ARM.com 4537404SAli.Saidi@ARM.com bool is_fetch = (mode == Execute); 4547404SAli.Saidi@ARM.com bool is_write = (mode == Write); 4557404SAli.Saidi@ARM.com bool is_priv = (cpsr.mode != MODE_USER) && !(flags & UserMode); 4567404SAli.Saidi@ARM.com 4577404SAli.Saidi@ARM.com DPRINTF(TLBVerbose, "CPSR is user:%d UserMode:%d\n", cpsr.mode == MODE_USER, flags 4587404SAli.Saidi@ARM.com & UserMode); 4597603SGene.Wu@arm.com // If this is a clrex instruction, provide a PA of 0 with no fault 4607603SGene.Wu@arm.com // This will force the monitor to set the tracked address to 0 4617603SGene.Wu@arm.com // a bit of a hack but this effectively clrears this processors monitor 4627705Sgblack@eecs.umich.edu if (flags & Request::CLEAR_LL){ 4637603SGene.Wu@arm.com req->setPaddr(0); 4647606SGene.Wu@arm.com req->setFlags(Request::UNCACHEABLE); 4657705Sgblack@eecs.umich.edu req->setFlags(Request::CLEAR_LL); 4667603SGene.Wu@arm.com return NoFault; 4677603SGene.Wu@arm.com } 4687608SGene.Wu@arm.com if ((req->isInstFetch() && (!sctlr.i)) || 4697608SGene.Wu@arm.com ((!req->isInstFetch()) && (!sctlr.c))){ 4707608SGene.Wu@arm.com req->setFlags(Request::UNCACHEABLE); 4717608SGene.Wu@arm.com } 4727404SAli.Saidi@ARM.com if (!is_fetch) { 4737404SAli.Saidi@ARM.com assert(flags & MustBeOne); 4747404SAli.Saidi@ARM.com if (sctlr.a || !(flags & AllowUnaligned)) { 4757404SAli.Saidi@ARM.com if (vaddr & flags & AlignmentMask) { 4767734SAli.Saidi@ARM.com alignFaults++; 4777404SAli.Saidi@ARM.com return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 4787404SAli.Saidi@ARM.com } 4797404SAli.Saidi@ARM.com } 4807404SAli.Saidi@ARM.com } 4817404SAli.Saidi@ARM.com 4827404SAli.Saidi@ARM.com uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR); 4837404SAli.Saidi@ARM.com Fault fault; 4847404SAli.Saidi@ARM.com 4857404SAli.Saidi@ARM.com 4866757SAli.Saidi@ARM.com if (!sctlr.m) { 4877093Sgblack@eecs.umich.edu req->setPaddr(vaddr); 4887404SAli.Saidi@ARM.com if (sctlr.tre == 0) { 4897404SAli.Saidi@ARM.com req->setFlags(Request::UNCACHEABLE); 4907404SAli.Saidi@ARM.com } else { 4917404SAli.Saidi@ARM.com PRRR prrr = tc->readMiscReg(MISCREG_PRRR); 4927404SAli.Saidi@ARM.com NMRR nmrr = tc->readMiscReg(MISCREG_NMRR); 4937404SAli.Saidi@ARM.com 4947404SAli.Saidi@ARM.com if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 4957404SAli.Saidi@ARM.com req->setFlags(Request::UNCACHEABLE); 4967404SAli.Saidi@ARM.com } 4977436Sdam.sunwoo@arm.com 4987436Sdam.sunwoo@arm.com // Set memory attributes 4997436Sdam.sunwoo@arm.com TlbEntry temp_te; 5007439Sdam.sunwoo@arm.com tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1); 5017436Sdam.sunwoo@arm.com temp_te.shareable = true; 5027436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\ 5037436Sdam.sunwoo@arm.com %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable, 5047436Sdam.sunwoo@arm.com temp_te.innerAttrs, temp_te.outerAttrs); 5057436Sdam.sunwoo@arm.com setAttr(temp_te.attributes); 5067436Sdam.sunwoo@arm.com 5077404SAli.Saidi@ARM.com return trickBoxCheck(req, mode, 0, false); 5087404SAli.Saidi@ARM.com } 5097404SAli.Saidi@ARM.com 5107404SAli.Saidi@ARM.com DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, context_id); 5117404SAli.Saidi@ARM.com // Translation enabled 5127404SAli.Saidi@ARM.com 5137404SAli.Saidi@ARM.com TlbEntry *te = lookup(vaddr, context_id); 5147404SAli.Saidi@ARM.com if (te == NULL) { 5157611SGene.Wu@arm.com if (req->isPrefetch()){ 5167611SGene.Wu@arm.com //if the request is a prefetch don't attempt to fill the TLB 5177611SGene.Wu@arm.com //or go any further with the memory access 5187734SAli.Saidi@ARM.com prefetchFaults++; 5197611SGene.Wu@arm.com return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss); 5207611SGene.Wu@arm.com } 5217734SAli.Saidi@ARM.com 5227734SAli.Saidi@ARM.com if (is_fetch) 5237734SAli.Saidi@ARM.com instMisses++; 5247734SAli.Saidi@ARM.com else if (is_write) 5257734SAli.Saidi@ARM.com writeMisses++; 5267734SAli.Saidi@ARM.com else 5277734SAli.Saidi@ARM.com readMisses++; 5287734SAli.Saidi@ARM.com 5297404SAli.Saidi@ARM.com // start translation table walk, pass variables rather than 5307404SAli.Saidi@ARM.com // re-retreaving in table walker for speed 5317404SAli.Saidi@ARM.com DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n", 5327404SAli.Saidi@ARM.com vaddr, context_id); 5337404SAli.Saidi@ARM.com fault = tableWalker->walk(req, tc, context_id, mode, translation, 5347404SAli.Saidi@ARM.com timing); 5357437Sdam.sunwoo@arm.com if (timing) { 5367404SAli.Saidi@ARM.com delay = true; 5377437Sdam.sunwoo@arm.com // for timing mode, return and wait for table walk 5387437Sdam.sunwoo@arm.com return fault; 5397437Sdam.sunwoo@arm.com } 5407404SAli.Saidi@ARM.com if (fault) 5417404SAli.Saidi@ARM.com return fault; 5427404SAli.Saidi@ARM.com 5437404SAli.Saidi@ARM.com te = lookup(vaddr, context_id); 5447404SAli.Saidi@ARM.com if (!te) 5457404SAli.Saidi@ARM.com printTlb(); 5467404SAli.Saidi@ARM.com assert(te); 5477734SAli.Saidi@ARM.com } else { 5487734SAli.Saidi@ARM.com if (is_fetch) 5497734SAli.Saidi@ARM.com instHits++; 5507734SAli.Saidi@ARM.com else if (is_write) 5517734SAli.Saidi@ARM.com writeHits++; 5527734SAli.Saidi@ARM.com else 5537734SAli.Saidi@ARM.com readHits++; 5547404SAli.Saidi@ARM.com } 5557404SAli.Saidi@ARM.com 5567436Sdam.sunwoo@arm.com // Set memory attributes 5577436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, 5587436Sdam.sunwoo@arm.com "Setting memory attributes: shareable: %d, innerAttrs: %d, \ 5597436Sdam.sunwoo@arm.com outerAttrs: %d\n", 5607436Sdam.sunwoo@arm.com te->shareable, te->innerAttrs, te->outerAttrs); 5617436Sdam.sunwoo@arm.com setAttr(te->attributes); 5627606SGene.Wu@arm.com if (te->nonCacheable) 5637606SGene.Wu@arm.com req->setFlags(Request::UNCACHEABLE); 5647404SAli.Saidi@ARM.com uint32_t dacr = tc->readMiscReg(MISCREG_DACR); 5657404SAli.Saidi@ARM.com switch ( (dacr >> (te->domain * 2)) & 0x3) { 5667404SAli.Saidi@ARM.com case 0: 5677734SAli.Saidi@ARM.com domainFaults++; 5687404SAli.Saidi@ARM.com DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x" 5697404SAli.Saidi@ARM.com " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp); 5707404SAli.Saidi@ARM.com if (is_fetch) 5717404SAli.Saidi@ARM.com return new PrefetchAbort(vaddr, 5727404SAli.Saidi@ARM.com (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 5737404SAli.Saidi@ARM.com else 5747404SAli.Saidi@ARM.com return new DataAbort(vaddr, te->domain, is_write, 5757404SAli.Saidi@ARM.com (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 5767404SAli.Saidi@ARM.com case 1: 5777404SAli.Saidi@ARM.com // Continue with permissions check 5787404SAli.Saidi@ARM.com break; 5797404SAli.Saidi@ARM.com case 2: 5807404SAli.Saidi@ARM.com panic("UNPRED domain\n"); 5817404SAli.Saidi@ARM.com case 3: 5827404SAli.Saidi@ARM.com req->setPaddr(te->pAddr(vaddr)); 5837404SAli.Saidi@ARM.com fault = trickBoxCheck(req, mode, te->domain, te->sNp); 5847404SAli.Saidi@ARM.com if (fault) 5857404SAli.Saidi@ARM.com return fault; 5866757SAli.Saidi@ARM.com return NoFault; 5876757SAli.Saidi@ARM.com } 5887404SAli.Saidi@ARM.com 5897404SAli.Saidi@ARM.com uint8_t ap = te->ap; 5907404SAli.Saidi@ARM.com 5917404SAli.Saidi@ARM.com if (sctlr.afe == 1) 5927404SAli.Saidi@ARM.com ap |= 1; 5937404SAli.Saidi@ARM.com 5947404SAli.Saidi@ARM.com bool abt; 5957404SAli.Saidi@ARM.com 5967406SAli.Saidi@ARM.com /* if (!sctlr.xp) 5977406SAli.Saidi@ARM.com ap &= 0x3; 5987406SAli.Saidi@ARM.com*/ 5997404SAli.Saidi@ARM.com switch (ap) { 6007404SAli.Saidi@ARM.com case 0: 6017406SAli.Saidi@ARM.com DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs); 6027406SAli.Saidi@ARM.com if (!sctlr.xp) { 6037406SAli.Saidi@ARM.com switch ((int)sctlr.rs) { 6047406SAli.Saidi@ARM.com case 2: 6057406SAli.Saidi@ARM.com abt = is_write; 6067406SAli.Saidi@ARM.com break; 6077406SAli.Saidi@ARM.com case 1: 6087406SAli.Saidi@ARM.com abt = is_write || !is_priv; 6097406SAli.Saidi@ARM.com break; 6107406SAli.Saidi@ARM.com case 0: 6117406SAli.Saidi@ARM.com case 3: 6127406SAli.Saidi@ARM.com default: 6137406SAli.Saidi@ARM.com abt = true; 6147406SAli.Saidi@ARM.com break; 6157406SAli.Saidi@ARM.com } 6167406SAli.Saidi@ARM.com } else { 6177406SAli.Saidi@ARM.com abt = true; 6187406SAli.Saidi@ARM.com } 6197404SAli.Saidi@ARM.com break; 6207404SAli.Saidi@ARM.com case 1: 6217404SAli.Saidi@ARM.com abt = !is_priv; 6227404SAli.Saidi@ARM.com break; 6237404SAli.Saidi@ARM.com case 2: 6247404SAli.Saidi@ARM.com abt = !is_priv && is_write; 6257404SAli.Saidi@ARM.com break; 6267404SAli.Saidi@ARM.com case 3: 6277404SAli.Saidi@ARM.com abt = false; 6287404SAli.Saidi@ARM.com break; 6297404SAli.Saidi@ARM.com case 4: 6307404SAli.Saidi@ARM.com panic("UNPRED premissions\n"); 6317404SAli.Saidi@ARM.com case 5: 6327404SAli.Saidi@ARM.com abt = !is_priv || is_write; 6337404SAli.Saidi@ARM.com break; 6347404SAli.Saidi@ARM.com case 6: 6357404SAli.Saidi@ARM.com case 7: 6367404SAli.Saidi@ARM.com abt = is_write; 6377404SAli.Saidi@ARM.com break; 6387404SAli.Saidi@ARM.com default: 6397404SAli.Saidi@ARM.com panic("Unknown permissions\n"); 6407404SAli.Saidi@ARM.com } 6417404SAli.Saidi@ARM.com if ((is_fetch) && (abt || te->xn)) { 6427734SAli.Saidi@ARM.com permsFaults++; 6437404SAli.Saidi@ARM.com DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d" 6447404SAli.Saidi@ARM.com " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 6457404SAli.Saidi@ARM.com return new PrefetchAbort(vaddr, 6467404SAli.Saidi@ARM.com (te->sNp ? ArmFault::Permission0 : 6477404SAli.Saidi@ARM.com ArmFault::Permission1)); 6487404SAli.Saidi@ARM.com } else if (abt) { 6497734SAli.Saidi@ARM.com permsFaults++; 6507404SAli.Saidi@ARM.com DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 6517404SAli.Saidi@ARM.com " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 6527404SAli.Saidi@ARM.com return new DataAbort(vaddr, te->domain, is_write, 6537404SAli.Saidi@ARM.com (te->sNp ? ArmFault::Permission0 : 6547404SAli.Saidi@ARM.com ArmFault::Permission1)); 6557404SAli.Saidi@ARM.com } 6567404SAli.Saidi@ARM.com 6577404SAli.Saidi@ARM.com req->setPaddr(te->pAddr(vaddr)); 6587404SAli.Saidi@ARM.com // Check for a trickbox generated address fault 6597404SAli.Saidi@ARM.com fault = trickBoxCheck(req, mode, te->domain, te->sNp); 6607404SAli.Saidi@ARM.com if (fault) 6617404SAli.Saidi@ARM.com return fault; 6627404SAli.Saidi@ARM.com 6636757SAli.Saidi@ARM.com return NoFault; 6647404SAli.Saidi@ARM.com} 6656757SAli.Saidi@ARM.com 6666019Shines@cs.fsu.edu#endif 6677404SAli.Saidi@ARM.com 6687404SAli.Saidi@ARM.comFault 6697404SAli.Saidi@ARM.comTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 6707404SAli.Saidi@ARM.com{ 6717404SAli.Saidi@ARM.com bool delay = false; 6727404SAli.Saidi@ARM.com Fault fault; 6737404SAli.Saidi@ARM.com#if FULL_SYSTEM 6747404SAli.Saidi@ARM.com fault = translateFs(req, tc, mode, NULL, delay, false); 6757404SAli.Saidi@ARM.com#else 6767404SAli.Saidi@ARM.com fault = translateSe(req, tc, mode, NULL, delay, false); 6777404SAli.Saidi@ARM.com#endif 6787404SAli.Saidi@ARM.com assert(!delay); 6797404SAli.Saidi@ARM.com return fault; 6806019Shines@cs.fsu.edu} 6816019Shines@cs.fsu.edu 6827404SAli.Saidi@ARM.comFault 6836116Snate@binkert.orgTLB::translateTiming(RequestPtr req, ThreadContext *tc, 6846116Snate@binkert.org Translation *translation, Mode mode) 6856020Sgblack@eecs.umich.edu{ 6866020Sgblack@eecs.umich.edu assert(translation); 6877404SAli.Saidi@ARM.com bool delay = false; 6887404SAli.Saidi@ARM.com Fault fault; 6897404SAli.Saidi@ARM.com#if FULL_SYSTEM 6907404SAli.Saidi@ARM.com fault = translateFs(req, tc, mode, translation, delay, true); 6917404SAli.Saidi@ARM.com#else 6927404SAli.Saidi@ARM.com fault = translateSe(req, tc, mode, translation, delay, true); 6937404SAli.Saidi@ARM.com#endif 6947404SAli.Saidi@ARM.com if (!delay) 6957404SAli.Saidi@ARM.com translation->finish(fault, req, tc, mode); 6967404SAli.Saidi@ARM.com return fault; 6976020Sgblack@eecs.umich.edu} 6986020Sgblack@eecs.umich.edu 6996116Snate@binkert.orgArmISA::TLB * 7006116Snate@binkert.orgArmTLBParams::create() 7016019Shines@cs.fsu.edu{ 7026116Snate@binkert.org return new ArmISA::TLB(this); 7036019Shines@cs.fsu.edu} 704