tlb.cc revision 7705
16019Shines@cs.fsu.edu/* 27093Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * All rights reserved. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 266019Shines@cs.fsu.edu * this software without specific prior written permission. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019Shines@cs.fsu.edu * 407399SAli.Saidi@ARM.com * Authors: Ali Saidi 417399SAli.Saidi@ARM.com * Nathan Binkert 426019Shines@cs.fsu.edu * Steve Reinhardt 436019Shines@cs.fsu.edu */ 446019Shines@cs.fsu.edu 456019Shines@cs.fsu.edu#include <string> 466019Shines@cs.fsu.edu#include <vector> 476019Shines@cs.fsu.edu 486116Snate@binkert.org#include "arch/arm/faults.hh" 496019Shines@cs.fsu.edu#include "arch/arm/pagetable.hh" 506019Shines@cs.fsu.edu#include "arch/arm/tlb.hh" 516019Shines@cs.fsu.edu#include "arch/arm/utility.hh" 526019Shines@cs.fsu.edu#include "base/inifile.hh" 536019Shines@cs.fsu.edu#include "base/str.hh" 546019Shines@cs.fsu.edu#include "base/trace.hh" 556019Shines@cs.fsu.edu#include "cpu/thread_context.hh" 566116Snate@binkert.org#include "mem/page_table.hh" 576116Snate@binkert.org#include "params/ArmTLB.hh" 586019Shines@cs.fsu.edu#include "sim/process.hh" 596019Shines@cs.fsu.edu 607406SAli.Saidi@ARM.com#if FULL_SYSTEM 617406SAli.Saidi@ARM.com#include "arch/arm/table_walker.hh" 627406SAli.Saidi@ARM.com#endif 637406SAli.Saidi@ARM.com 646019Shines@cs.fsu.eduusing namespace std; 656019Shines@cs.fsu.eduusing namespace ArmISA; 666019Shines@cs.fsu.edu 676019Shines@cs.fsu.eduTLB::TLB(const Params *p) 687697SAli.Saidi@ARM.com : BaseTLB(p), size(p->size) 697404SAli.Saidi@ARM.com#if FULL_SYSTEM 707404SAli.Saidi@ARM.com , tableWalker(p->walker) 717404SAli.Saidi@ARM.com#endif 727697SAli.Saidi@ARM.com , rangeMRU(1) 736019Shines@cs.fsu.edu{ 747404SAli.Saidi@ARM.com table = new TlbEntry[size]; 757404SAli.Saidi@ARM.com memset(table, 0, sizeof(TlbEntry[size])); 767399SAli.Saidi@ARM.com 777406SAli.Saidi@ARM.com#if FULL_SYSTEM 787404SAli.Saidi@ARM.com tableWalker->setTlb(this); 797406SAli.Saidi@ARM.com#endif 806019Shines@cs.fsu.edu} 816019Shines@cs.fsu.edu 826019Shines@cs.fsu.eduTLB::~TLB() 836019Shines@cs.fsu.edu{ 846019Shines@cs.fsu.edu if (table) 856019Shines@cs.fsu.edu delete [] table; 866019Shines@cs.fsu.edu} 876019Shines@cs.fsu.edu 887694SAli.Saidi@ARM.combool 897694SAli.Saidi@ARM.comTLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa) 907694SAli.Saidi@ARM.com{ 917694SAli.Saidi@ARM.com uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR); 927694SAli.Saidi@ARM.com TlbEntry *e = lookup(va, context_id, true); 937694SAli.Saidi@ARM.com if (!e) 947694SAli.Saidi@ARM.com return false; 957694SAli.Saidi@ARM.com pa = e->pAddr(va); 967694SAli.Saidi@ARM.com return true; 977694SAli.Saidi@ARM.com} 987694SAli.Saidi@ARM.com 997404SAli.Saidi@ARM.comTlbEntry* 1007694SAli.Saidi@ARM.comTLB::lookup(Addr va, uint8_t cid, bool functional) 1016019Shines@cs.fsu.edu{ 1027404SAli.Saidi@ARM.com 1037404SAli.Saidi@ARM.com TlbEntry *retval = NULL; 1047404SAli.Saidi@ARM.com 1057697SAli.Saidi@ARM.com // Maitaining LRU array 1067404SAli.Saidi@ARM.com 1077404SAli.Saidi@ARM.com int x = 0; 1087404SAli.Saidi@ARM.com while (retval == NULL && x < size) { 1097404SAli.Saidi@ARM.com if (table[x].match(va, cid)) { 1107404SAli.Saidi@ARM.com 1117697SAli.Saidi@ARM.com // We only move the hit entry ahead when the position is higher than rangeMRU 1127697SAli.Saidi@ARM.com if (x > rangeMRU) { 1137697SAli.Saidi@ARM.com TlbEntry tmp_entry = table[x]; 1147697SAli.Saidi@ARM.com for(int i = x; i > 0; i--) 1157697SAli.Saidi@ARM.com table[i] = table[i-1]; 1167697SAli.Saidi@ARM.com table[0] = tmp_entry; 1177697SAli.Saidi@ARM.com retval = &table[0]; 1187697SAli.Saidi@ARM.com } else { 1197697SAli.Saidi@ARM.com retval = &table[x]; 1207697SAli.Saidi@ARM.com } 1217404SAli.Saidi@ARM.com break; 1227404SAli.Saidi@ARM.com } 1237404SAli.Saidi@ARM.com x++; 1247404SAli.Saidi@ARM.com } 1257404SAli.Saidi@ARM.com 1267404SAli.Saidi@ARM.com DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n", 1277404SAli.Saidi@ARM.com va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0, 1287404SAli.Saidi@ARM.com retval ? retval->size : 0, retval ? retval->pAddr(va) : 0, 1297404SAli.Saidi@ARM.com retval ? retval->ap : 0); 1307404SAli.Saidi@ARM.com ; 1317404SAli.Saidi@ARM.com return retval; 1326019Shines@cs.fsu.edu} 1336019Shines@cs.fsu.edu 1346019Shines@cs.fsu.edu// insert a new TLB entry 1356019Shines@cs.fsu.eduvoid 1367404SAli.Saidi@ARM.comTLB::insert(Addr addr, TlbEntry &entry) 1376019Shines@cs.fsu.edu{ 1387404SAli.Saidi@ARM.com DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x" 1397404SAli.Saidi@ARM.com " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x" 1407404SAli.Saidi@ARM.com " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid, 1417404SAli.Saidi@ARM.com entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp, 1427404SAli.Saidi@ARM.com entry.xn, entry.ap, entry.domain); 1437404SAli.Saidi@ARM.com 1447697SAli.Saidi@ARM.com if (table[size-1].valid) 1457404SAli.Saidi@ARM.com DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n", 1467697SAli.Saidi@ARM.com table[size-1].vpn << table[size-1].N, table[size-1].asid, 1477697SAli.Saidi@ARM.com table[size-1].pfn << table[size-1].N, table[size-1].size, 1487697SAli.Saidi@ARM.com table[size-1].ap); 1497404SAli.Saidi@ARM.com 1507697SAli.Saidi@ARM.com //inserting to MRU position and evicting the LRU one 1517404SAli.Saidi@ARM.com 1527697SAli.Saidi@ARM.com for(int i = size-1; i > 0; i--) 1537697SAli.Saidi@ARM.com table[i] = table[i-1]; 1547697SAli.Saidi@ARM.com table[0] = entry; 1556019Shines@cs.fsu.edu} 1566019Shines@cs.fsu.edu 1576019Shines@cs.fsu.eduvoid 1587404SAli.Saidi@ARM.comTLB::printTlb() 1597404SAli.Saidi@ARM.com{ 1607404SAli.Saidi@ARM.com int x = 0; 1617404SAli.Saidi@ARM.com TlbEntry *te; 1627404SAli.Saidi@ARM.com DPRINTF(TLB, "Current TLB contents:\n"); 1637404SAli.Saidi@ARM.com while (x < size) { 1647404SAli.Saidi@ARM.com te = &table[x]; 1657404SAli.Saidi@ARM.com if (te->valid) 1667404SAli.Saidi@ARM.com DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n", 1677404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 1687404SAli.Saidi@ARM.com x++; 1697404SAli.Saidi@ARM.com } 1707404SAli.Saidi@ARM.com} 1717404SAli.Saidi@ARM.com 1727404SAli.Saidi@ARM.com 1737404SAli.Saidi@ARM.comvoid 1746019Shines@cs.fsu.eduTLB::flushAll() 1756019Shines@cs.fsu.edu{ 1767404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing all TLB entries\n"); 1777404SAli.Saidi@ARM.com int x = 0; 1787404SAli.Saidi@ARM.com TlbEntry *te; 1797404SAli.Saidi@ARM.com while (x < size) { 1807404SAli.Saidi@ARM.com te = &table[x]; 1817404SAli.Saidi@ARM.com if (te->valid) 1827404SAli.Saidi@ARM.com DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 1837404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 1847404SAli.Saidi@ARM.com x++; 1857404SAli.Saidi@ARM.com } 1867404SAli.Saidi@ARM.com 1877404SAli.Saidi@ARM.com memset(table, 0, sizeof(TlbEntry[size])); 1886019Shines@cs.fsu.edu} 1896019Shines@cs.fsu.edu 1907404SAli.Saidi@ARM.com 1917404SAli.Saidi@ARM.comvoid 1927404SAli.Saidi@ARM.comTLB::flushMvaAsid(Addr mva, uint64_t asn) 1937404SAli.Saidi@ARM.com{ 1947404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn); 1957404SAli.Saidi@ARM.com TlbEntry *te; 1967404SAli.Saidi@ARM.com 1977404SAli.Saidi@ARM.com te = lookup(mva, asn); 1987404SAli.Saidi@ARM.com while (te != NULL) { 1997404SAli.Saidi@ARM.com DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 2007404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 2017404SAli.Saidi@ARM.com te->valid = false; 2027404SAli.Saidi@ARM.com te = lookup(mva,asn); 2037404SAli.Saidi@ARM.com } 2047404SAli.Saidi@ARM.com} 2057404SAli.Saidi@ARM.com 2067404SAli.Saidi@ARM.comvoid 2077404SAli.Saidi@ARM.comTLB::flushAsid(uint64_t asn) 2087404SAli.Saidi@ARM.com{ 2097404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn); 2107404SAli.Saidi@ARM.com 2117404SAli.Saidi@ARM.com int x = 0; 2127404SAli.Saidi@ARM.com TlbEntry *te; 2137404SAli.Saidi@ARM.com 2147404SAli.Saidi@ARM.com while (x < size) { 2157404SAli.Saidi@ARM.com te = &table[x]; 2167404SAli.Saidi@ARM.com if (te->asid == asn) { 2177404SAli.Saidi@ARM.com te->valid = false; 2187404SAli.Saidi@ARM.com DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 2197404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 2207404SAli.Saidi@ARM.com } 2217404SAli.Saidi@ARM.com x++; 2227404SAli.Saidi@ARM.com } 2237404SAli.Saidi@ARM.com} 2247404SAli.Saidi@ARM.com 2257404SAli.Saidi@ARM.comvoid 2267404SAli.Saidi@ARM.comTLB::flushMva(Addr mva) 2277404SAli.Saidi@ARM.com{ 2287404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva); 2297404SAli.Saidi@ARM.com 2307404SAli.Saidi@ARM.com int x = 0; 2317404SAli.Saidi@ARM.com TlbEntry *te; 2327404SAli.Saidi@ARM.com 2337404SAli.Saidi@ARM.com while (x < size) { 2347404SAli.Saidi@ARM.com te = &table[x]; 2357404SAli.Saidi@ARM.com Addr v = te->vpn << te->N; 2367404SAli.Saidi@ARM.com if (mva >= v && mva < v + te->size) { 2377404SAli.Saidi@ARM.com te->valid = false; 2387404SAli.Saidi@ARM.com DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 2397404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 2407404SAli.Saidi@ARM.com } 2417404SAli.Saidi@ARM.com x++; 2427404SAli.Saidi@ARM.com } 2437404SAli.Saidi@ARM.com} 2447404SAli.Saidi@ARM.com 2456019Shines@cs.fsu.eduvoid 2466019Shines@cs.fsu.eduTLB::serialize(ostream &os) 2476019Shines@cs.fsu.edu{ 2487404SAli.Saidi@ARM.com panic("Implement Serialize\n"); 2496019Shines@cs.fsu.edu} 2506019Shines@cs.fsu.edu 2516019Shines@cs.fsu.eduvoid 2526019Shines@cs.fsu.eduTLB::unserialize(Checkpoint *cp, const string §ion) 2536019Shines@cs.fsu.edu{ 2546019Shines@cs.fsu.edu 2557399SAli.Saidi@ARM.com panic("Need to properly unserialize TLB\n"); 2566019Shines@cs.fsu.edu} 2576019Shines@cs.fsu.edu 2586019Shines@cs.fsu.eduvoid 2596019Shines@cs.fsu.eduTLB::regStats() 2606019Shines@cs.fsu.edu{ 2616019Shines@cs.fsu.edu read_hits 2626019Shines@cs.fsu.edu .name(name() + ".read_hits") 2636019Shines@cs.fsu.edu .desc("DTB read hits") 2646019Shines@cs.fsu.edu ; 2656019Shines@cs.fsu.edu 2666019Shines@cs.fsu.edu read_misses 2676019Shines@cs.fsu.edu .name(name() + ".read_misses") 2686019Shines@cs.fsu.edu .desc("DTB read misses") 2696019Shines@cs.fsu.edu ; 2706019Shines@cs.fsu.edu 2716019Shines@cs.fsu.edu 2726019Shines@cs.fsu.edu read_accesses 2736019Shines@cs.fsu.edu .name(name() + ".read_accesses") 2746019Shines@cs.fsu.edu .desc("DTB read accesses") 2756019Shines@cs.fsu.edu ; 2766019Shines@cs.fsu.edu 2776019Shines@cs.fsu.edu write_hits 2786019Shines@cs.fsu.edu .name(name() + ".write_hits") 2796019Shines@cs.fsu.edu .desc("DTB write hits") 2806019Shines@cs.fsu.edu ; 2816019Shines@cs.fsu.edu 2826019Shines@cs.fsu.edu write_misses 2836019Shines@cs.fsu.edu .name(name() + ".write_misses") 2846019Shines@cs.fsu.edu .desc("DTB write misses") 2856019Shines@cs.fsu.edu ; 2866019Shines@cs.fsu.edu 2876019Shines@cs.fsu.edu 2886019Shines@cs.fsu.edu write_accesses 2896019Shines@cs.fsu.edu .name(name() + ".write_accesses") 2906019Shines@cs.fsu.edu .desc("DTB write accesses") 2916019Shines@cs.fsu.edu ; 2926019Shines@cs.fsu.edu 2936019Shines@cs.fsu.edu hits 2946019Shines@cs.fsu.edu .name(name() + ".hits") 2956019Shines@cs.fsu.edu .desc("DTB hits") 2966019Shines@cs.fsu.edu ; 2976019Shines@cs.fsu.edu 2986019Shines@cs.fsu.edu misses 2996019Shines@cs.fsu.edu .name(name() + ".misses") 3006019Shines@cs.fsu.edu .desc("DTB misses") 3016019Shines@cs.fsu.edu ; 3026019Shines@cs.fsu.edu 3036019Shines@cs.fsu.edu accesses 3046019Shines@cs.fsu.edu .name(name() + ".accesses") 3056019Shines@cs.fsu.edu .desc("DTB accesses") 3066019Shines@cs.fsu.edu ; 3076019Shines@cs.fsu.edu 3086019Shines@cs.fsu.edu hits = read_hits + write_hits; 3096019Shines@cs.fsu.edu misses = read_misses + write_misses; 3106019Shines@cs.fsu.edu accesses = read_accesses + write_accesses; 3116019Shines@cs.fsu.edu} 3126019Shines@cs.fsu.edu 3137404SAli.Saidi@ARM.com#if !FULL_SYSTEM 3147404SAli.Saidi@ARM.comFault 3157404SAli.Saidi@ARM.comTLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 3167404SAli.Saidi@ARM.com Translation *translation, bool &delay, bool timing) 3177404SAli.Saidi@ARM.com{ 3187404SAli.Saidi@ARM.com // XXX Cache misc registers and have miscreg write function inv cache 3197093Sgblack@eecs.umich.edu Addr vaddr = req->getVaddr() & ~PcModeMask; 3207294Sgblack@eecs.umich.edu SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 3217294Sgblack@eecs.umich.edu uint32_t flags = req->getFlags(); 3227294Sgblack@eecs.umich.edu 3237404SAli.Saidi@ARM.com bool is_fetch = (mode == Execute); 3247404SAli.Saidi@ARM.com bool is_write = (mode == Write); 3257404SAli.Saidi@ARM.com 3267404SAli.Saidi@ARM.com if (!is_fetch) { 3277294Sgblack@eecs.umich.edu assert(flags & MustBeOne); 3287404SAli.Saidi@ARM.com if (sctlr.a || !(flags & AllowUnaligned)) { 3297404SAli.Saidi@ARM.com if (vaddr & flags & AlignmentMask) { 3307404SAli.Saidi@ARM.com return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 3317294Sgblack@eecs.umich.edu } 3327294Sgblack@eecs.umich.edu } 3337294Sgblack@eecs.umich.edu } 3346019Shines@cs.fsu.edu 3357093Sgblack@eecs.umich.edu Addr paddr; 3367404SAli.Saidi@ARM.com Process *p = tc->getProcessPtr(); 3377404SAli.Saidi@ARM.com 3387093Sgblack@eecs.umich.edu if (!p->pTable->translate(vaddr, paddr)) 3397093Sgblack@eecs.umich.edu return Fault(new GenericPageTableFault(vaddr)); 3407093Sgblack@eecs.umich.edu req->setPaddr(paddr); 3416019Shines@cs.fsu.edu 3426019Shines@cs.fsu.edu return NoFault; 3437404SAli.Saidi@ARM.com} 3447404SAli.Saidi@ARM.com 3457404SAli.Saidi@ARM.com#else // FULL_SYSTEM 3467404SAli.Saidi@ARM.com 3477404SAli.Saidi@ARM.comFault 3487406SAli.Saidi@ARM.comTLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp) 3497406SAli.Saidi@ARM.com{ 3507406SAli.Saidi@ARM.com return NoFault; 3517406SAli.Saidi@ARM.com} 3527406SAli.Saidi@ARM.com 3537406SAli.Saidi@ARM.comFault 3547406SAli.Saidi@ARM.comTLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec, 3557406SAli.Saidi@ARM.com bool is_write, uint8_t domain, bool sNp) 3567406SAli.Saidi@ARM.com{ 3577406SAli.Saidi@ARM.com return NoFault; 3587406SAli.Saidi@ARM.com} 3597406SAli.Saidi@ARM.com 3607406SAli.Saidi@ARM.comFault 3617404SAli.Saidi@ARM.comTLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 3627404SAli.Saidi@ARM.com Translation *translation, bool &delay, bool timing) 3637404SAli.Saidi@ARM.com{ 3647404SAli.Saidi@ARM.com // XXX Cache misc registers and have miscreg write function inv cache 3657404SAli.Saidi@ARM.com Addr vaddr = req->getVaddr() & ~PcModeMask; 3667404SAli.Saidi@ARM.com SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 3677404SAli.Saidi@ARM.com CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 3687404SAli.Saidi@ARM.com uint32_t flags = req->getFlags(); 3697404SAli.Saidi@ARM.com 3707404SAli.Saidi@ARM.com bool is_fetch = (mode == Execute); 3717404SAli.Saidi@ARM.com bool is_write = (mode == Write); 3727404SAli.Saidi@ARM.com bool is_priv = (cpsr.mode != MODE_USER) && !(flags & UserMode); 3737404SAli.Saidi@ARM.com 3747404SAli.Saidi@ARM.com DPRINTF(TLBVerbose, "CPSR is user:%d UserMode:%d\n", cpsr.mode == MODE_USER, flags 3757404SAli.Saidi@ARM.com & UserMode); 3767603SGene.Wu@arm.com // If this is a clrex instruction, provide a PA of 0 with no fault 3777603SGene.Wu@arm.com // This will force the monitor to set the tracked address to 0 3787603SGene.Wu@arm.com // a bit of a hack but this effectively clrears this processors monitor 3797705Sgblack@eecs.umich.edu if (flags & Request::CLEAR_LL){ 3807603SGene.Wu@arm.com req->setPaddr(0); 3817606SGene.Wu@arm.com req->setFlags(Request::UNCACHEABLE); 3827705Sgblack@eecs.umich.edu req->setFlags(Request::CLEAR_LL); 3837603SGene.Wu@arm.com return NoFault; 3847603SGene.Wu@arm.com } 3857608SGene.Wu@arm.com if ((req->isInstFetch() && (!sctlr.i)) || 3867608SGene.Wu@arm.com ((!req->isInstFetch()) && (!sctlr.c))){ 3877608SGene.Wu@arm.com req->setFlags(Request::UNCACHEABLE); 3887608SGene.Wu@arm.com } 3897404SAli.Saidi@ARM.com if (!is_fetch) { 3907404SAli.Saidi@ARM.com assert(flags & MustBeOne); 3917404SAli.Saidi@ARM.com if (sctlr.a || !(flags & AllowUnaligned)) { 3927404SAli.Saidi@ARM.com if (vaddr & flags & AlignmentMask) { 3937404SAli.Saidi@ARM.com return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 3947404SAli.Saidi@ARM.com } 3957404SAli.Saidi@ARM.com } 3967404SAli.Saidi@ARM.com } 3977404SAli.Saidi@ARM.com 3987404SAli.Saidi@ARM.com uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR); 3997404SAli.Saidi@ARM.com Fault fault; 4007404SAli.Saidi@ARM.com 4017404SAli.Saidi@ARM.com 4026757SAli.Saidi@ARM.com if (!sctlr.m) { 4037093Sgblack@eecs.umich.edu req->setPaddr(vaddr); 4047404SAli.Saidi@ARM.com if (sctlr.tre == 0) { 4057404SAli.Saidi@ARM.com req->setFlags(Request::UNCACHEABLE); 4067404SAli.Saidi@ARM.com } else { 4077404SAli.Saidi@ARM.com PRRR prrr = tc->readMiscReg(MISCREG_PRRR); 4087404SAli.Saidi@ARM.com NMRR nmrr = tc->readMiscReg(MISCREG_NMRR); 4097404SAli.Saidi@ARM.com 4107404SAli.Saidi@ARM.com if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 4117404SAli.Saidi@ARM.com req->setFlags(Request::UNCACHEABLE); 4127404SAli.Saidi@ARM.com } 4137436Sdam.sunwoo@arm.com 4147436Sdam.sunwoo@arm.com // Set memory attributes 4157436Sdam.sunwoo@arm.com TlbEntry temp_te; 4167439Sdam.sunwoo@arm.com tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1); 4177436Sdam.sunwoo@arm.com temp_te.shareable = true; 4187436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\ 4197436Sdam.sunwoo@arm.com %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable, 4207436Sdam.sunwoo@arm.com temp_te.innerAttrs, temp_te.outerAttrs); 4217436Sdam.sunwoo@arm.com setAttr(temp_te.attributes); 4227436Sdam.sunwoo@arm.com 4237404SAli.Saidi@ARM.com return trickBoxCheck(req, mode, 0, false); 4247404SAli.Saidi@ARM.com } 4257404SAli.Saidi@ARM.com 4267404SAli.Saidi@ARM.com DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, context_id); 4277404SAli.Saidi@ARM.com // Translation enabled 4287404SAli.Saidi@ARM.com 4297404SAli.Saidi@ARM.com TlbEntry *te = lookup(vaddr, context_id); 4307404SAli.Saidi@ARM.com if (te == NULL) { 4317611SGene.Wu@arm.com if (req->isPrefetch()){ 4327611SGene.Wu@arm.com //if the request is a prefetch don't attempt to fill the TLB 4337611SGene.Wu@arm.com //or go any further with the memory access 4347611SGene.Wu@arm.com return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss); 4357611SGene.Wu@arm.com } 4367404SAli.Saidi@ARM.com // start translation table walk, pass variables rather than 4377404SAli.Saidi@ARM.com // re-retreaving in table walker for speed 4387404SAli.Saidi@ARM.com DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n", 4397404SAli.Saidi@ARM.com vaddr, context_id); 4407404SAli.Saidi@ARM.com fault = tableWalker->walk(req, tc, context_id, mode, translation, 4417404SAli.Saidi@ARM.com timing); 4427437Sdam.sunwoo@arm.com if (timing) { 4437404SAli.Saidi@ARM.com delay = true; 4447437Sdam.sunwoo@arm.com // for timing mode, return and wait for table walk 4457437Sdam.sunwoo@arm.com return fault; 4467437Sdam.sunwoo@arm.com } 4477404SAli.Saidi@ARM.com if (fault) 4487404SAli.Saidi@ARM.com return fault; 4497404SAli.Saidi@ARM.com 4507404SAli.Saidi@ARM.com te = lookup(vaddr, context_id); 4517404SAli.Saidi@ARM.com if (!te) 4527404SAli.Saidi@ARM.com printTlb(); 4537404SAli.Saidi@ARM.com assert(te); 4547404SAli.Saidi@ARM.com } 4557404SAli.Saidi@ARM.com 4567436Sdam.sunwoo@arm.com // Set memory attributes 4577436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, 4587436Sdam.sunwoo@arm.com "Setting memory attributes: shareable: %d, innerAttrs: %d, \ 4597436Sdam.sunwoo@arm.com outerAttrs: %d\n", 4607436Sdam.sunwoo@arm.com te->shareable, te->innerAttrs, te->outerAttrs); 4617436Sdam.sunwoo@arm.com setAttr(te->attributes); 4627606SGene.Wu@arm.com if (te->nonCacheable) 4637606SGene.Wu@arm.com req->setFlags(Request::UNCACHEABLE); 4647404SAli.Saidi@ARM.com uint32_t dacr = tc->readMiscReg(MISCREG_DACR); 4657404SAli.Saidi@ARM.com switch ( (dacr >> (te->domain * 2)) & 0x3) { 4667404SAli.Saidi@ARM.com case 0: 4677404SAli.Saidi@ARM.com DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x" 4687404SAli.Saidi@ARM.com " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp); 4697404SAli.Saidi@ARM.com if (is_fetch) 4707404SAli.Saidi@ARM.com return new PrefetchAbort(vaddr, 4717404SAli.Saidi@ARM.com (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 4727404SAli.Saidi@ARM.com else 4737404SAli.Saidi@ARM.com return new DataAbort(vaddr, te->domain, is_write, 4747404SAli.Saidi@ARM.com (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 4757404SAli.Saidi@ARM.com case 1: 4767404SAli.Saidi@ARM.com // Continue with permissions check 4777404SAli.Saidi@ARM.com break; 4787404SAli.Saidi@ARM.com case 2: 4797404SAli.Saidi@ARM.com panic("UNPRED domain\n"); 4807404SAli.Saidi@ARM.com case 3: 4817404SAli.Saidi@ARM.com req->setPaddr(te->pAddr(vaddr)); 4827404SAli.Saidi@ARM.com fault = trickBoxCheck(req, mode, te->domain, te->sNp); 4837404SAli.Saidi@ARM.com if (fault) 4847404SAli.Saidi@ARM.com return fault; 4856757SAli.Saidi@ARM.com return NoFault; 4866757SAli.Saidi@ARM.com } 4877404SAli.Saidi@ARM.com 4887404SAli.Saidi@ARM.com uint8_t ap = te->ap; 4897404SAli.Saidi@ARM.com 4907404SAli.Saidi@ARM.com if (sctlr.afe == 1) 4917404SAli.Saidi@ARM.com ap |= 1; 4927404SAli.Saidi@ARM.com 4937404SAli.Saidi@ARM.com bool abt; 4947404SAli.Saidi@ARM.com 4957406SAli.Saidi@ARM.com /* if (!sctlr.xp) 4967406SAli.Saidi@ARM.com ap &= 0x3; 4977406SAli.Saidi@ARM.com*/ 4987404SAli.Saidi@ARM.com switch (ap) { 4997404SAli.Saidi@ARM.com case 0: 5007406SAli.Saidi@ARM.com DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs); 5017406SAli.Saidi@ARM.com if (!sctlr.xp) { 5027406SAli.Saidi@ARM.com switch ((int)sctlr.rs) { 5037406SAli.Saidi@ARM.com case 2: 5047406SAli.Saidi@ARM.com abt = is_write; 5057406SAli.Saidi@ARM.com break; 5067406SAli.Saidi@ARM.com case 1: 5077406SAli.Saidi@ARM.com abt = is_write || !is_priv; 5087406SAli.Saidi@ARM.com break; 5097406SAli.Saidi@ARM.com case 0: 5107406SAli.Saidi@ARM.com case 3: 5117406SAli.Saidi@ARM.com default: 5127406SAli.Saidi@ARM.com abt = true; 5137406SAli.Saidi@ARM.com break; 5147406SAli.Saidi@ARM.com } 5157406SAli.Saidi@ARM.com } else { 5167406SAli.Saidi@ARM.com abt = true; 5177406SAli.Saidi@ARM.com } 5187404SAli.Saidi@ARM.com break; 5197404SAli.Saidi@ARM.com case 1: 5207404SAli.Saidi@ARM.com abt = !is_priv; 5217404SAli.Saidi@ARM.com break; 5227404SAli.Saidi@ARM.com case 2: 5237404SAli.Saidi@ARM.com abt = !is_priv && is_write; 5247404SAli.Saidi@ARM.com break; 5257404SAli.Saidi@ARM.com case 3: 5267404SAli.Saidi@ARM.com abt = false; 5277404SAli.Saidi@ARM.com break; 5287404SAli.Saidi@ARM.com case 4: 5297404SAli.Saidi@ARM.com panic("UNPRED premissions\n"); 5307404SAli.Saidi@ARM.com case 5: 5317404SAli.Saidi@ARM.com abt = !is_priv || is_write; 5327404SAli.Saidi@ARM.com break; 5337404SAli.Saidi@ARM.com case 6: 5347404SAli.Saidi@ARM.com case 7: 5357404SAli.Saidi@ARM.com abt = is_write; 5367404SAli.Saidi@ARM.com break; 5377404SAli.Saidi@ARM.com default: 5387404SAli.Saidi@ARM.com panic("Unknown permissions\n"); 5397404SAli.Saidi@ARM.com } 5407404SAli.Saidi@ARM.com if ((is_fetch) && (abt || te->xn)) { 5417404SAli.Saidi@ARM.com DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d" 5427404SAli.Saidi@ARM.com " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 5437404SAli.Saidi@ARM.com return new PrefetchAbort(vaddr, 5447404SAli.Saidi@ARM.com (te->sNp ? ArmFault::Permission0 : 5457404SAli.Saidi@ARM.com ArmFault::Permission1)); 5467404SAli.Saidi@ARM.com } else if (abt) { 5477404SAli.Saidi@ARM.com DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 5487404SAli.Saidi@ARM.com " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 5497404SAli.Saidi@ARM.com return new DataAbort(vaddr, te->domain, is_write, 5507404SAli.Saidi@ARM.com (te->sNp ? ArmFault::Permission0 : 5517404SAli.Saidi@ARM.com ArmFault::Permission1)); 5527404SAli.Saidi@ARM.com } 5537404SAli.Saidi@ARM.com 5547404SAli.Saidi@ARM.com req->setPaddr(te->pAddr(vaddr)); 5557404SAli.Saidi@ARM.com // Check for a trickbox generated address fault 5567404SAli.Saidi@ARM.com fault = trickBoxCheck(req, mode, te->domain, te->sNp); 5577404SAli.Saidi@ARM.com if (fault) 5587404SAli.Saidi@ARM.com return fault; 5597404SAli.Saidi@ARM.com 5606757SAli.Saidi@ARM.com return NoFault; 5617404SAli.Saidi@ARM.com} 5626757SAli.Saidi@ARM.com 5636019Shines@cs.fsu.edu#endif 5647404SAli.Saidi@ARM.com 5657404SAli.Saidi@ARM.comFault 5667404SAli.Saidi@ARM.comTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 5677404SAli.Saidi@ARM.com{ 5687404SAli.Saidi@ARM.com bool delay = false; 5697404SAli.Saidi@ARM.com Fault fault; 5707404SAli.Saidi@ARM.com#if FULL_SYSTEM 5717404SAli.Saidi@ARM.com fault = translateFs(req, tc, mode, NULL, delay, false); 5727404SAli.Saidi@ARM.com#else 5737404SAli.Saidi@ARM.com fault = translateSe(req, tc, mode, NULL, delay, false); 5747404SAli.Saidi@ARM.com#endif 5757404SAli.Saidi@ARM.com assert(!delay); 5767404SAli.Saidi@ARM.com return fault; 5776019Shines@cs.fsu.edu} 5786019Shines@cs.fsu.edu 5797404SAli.Saidi@ARM.comFault 5806116Snate@binkert.orgTLB::translateTiming(RequestPtr req, ThreadContext *tc, 5816116Snate@binkert.org Translation *translation, Mode mode) 5826020Sgblack@eecs.umich.edu{ 5836020Sgblack@eecs.umich.edu assert(translation); 5847404SAli.Saidi@ARM.com bool delay = false; 5857404SAli.Saidi@ARM.com Fault fault; 5867404SAli.Saidi@ARM.com#if FULL_SYSTEM 5877404SAli.Saidi@ARM.com fault = translateFs(req, tc, mode, translation, delay, true); 5887404SAli.Saidi@ARM.com#else 5897404SAli.Saidi@ARM.com fault = translateSe(req, tc, mode, translation, delay, true); 5907404SAli.Saidi@ARM.com#endif 5917404SAli.Saidi@ARM.com if (!delay) 5927404SAli.Saidi@ARM.com translation->finish(fault, req, tc, mode); 5937404SAli.Saidi@ARM.com return fault; 5946020Sgblack@eecs.umich.edu} 5956020Sgblack@eecs.umich.edu 5966116Snate@binkert.orgArmISA::TLB * 5976116Snate@binkert.orgArmTLBParams::create() 5986019Shines@cs.fsu.edu{ 5996116Snate@binkert.org return new ArmISA::TLB(this); 6006019Shines@cs.fsu.edu} 601